1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3  * Author: Andy Yan <andy.yan@rock-chips.com>
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #include <common.h>
8 #include <bitfield.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <syscon.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cru_rv1108.h>
16 #include <asm/arch/hardware.h>
17 #include <dm/lists.h>
18 #include <dt-bindings/clock/rv1108-cru.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 enum {
23 	VCO_MAX_HZ	= 2400U * 1000000,
24 	VCO_MIN_HZ	= 600 * 1000000,
25 	OUTPUT_MAX_HZ	= 2400U * 1000000,
26 	OUTPUT_MIN_HZ	= 24 * 1000000,
27 };
28 
29 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
30 
31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
32 	.refdiv = _refdiv,\
33 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
34 	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
35 	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
37 			 #hz "Hz cannot be hit with PLL "\
38 			 "divisors on line " __stringify(__LINE__));
39 
40 /* use integer mode */
41 static inline int rv1108_pll_id(enum rk_clk_id clk_id)
42 {
43 	int id = 0;
44 
45 	switch (clk_id) {
46 	case CLK_ARM:
47 	case CLK_DDR:
48 		id = clk_id - 1;
49 		break;
50 	case CLK_GENERAL:
51 		id = 2;
52 		break;
53 	default:
54 		printf("invalid pll id:%d\n", clk_id);
55 		id = -1;
56 		break;
57 	}
58 
59 	return id;
60 }
61 
62 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
63 				   enum rk_clk_id clk_id)
64 {
65 	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
66 	uint32_t con0, con1, con3;
67 	int pll_id = rv1108_pll_id(clk_id);
68 	struct rv1108_pll *pll = &cru->pll[pll_id];
69 	uint32_t freq;
70 
71 	con3 = readl(&pll->con3);
72 
73 	if (con3 & WORK_MODE_MASK) {
74 		con0 = readl(&pll->con0);
75 		con1 = readl(&pll->con1);
76 		fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
77 		postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
78 		postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
79 		refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT;
80 		freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
81 	} else {
82 		freq = OSC_HZ;
83 	}
84 
85 	return freq;
86 }
87 
88 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
89 {
90 	uint32_t con = readl(&cru->clksel_con[24]);
91 	ulong pll_rate;
92 	uint8_t div;
93 
94 	if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
95 		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
96 	else
97 		pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
98 
99 	/*default set 50MHZ for gmac*/
100 	if (!rate)
101 		rate = 50000000;
102 
103 	div = DIV_ROUND_UP(pll_rate, rate) - 1;
104 	if (div <= 0x1f)
105 		rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
106 			     div << MAC_CLK_DIV_SHIFT);
107 	else
108 		debug("Unsupported div for gmac:%d\n", div);
109 
110 	return DIV_TO_RATE(pll_rate, div);
111 }
112 
113 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
114 {
115 	u32 con = readl(&cru->clksel_con[27]);
116 	u32 pll_rate;
117 	u32 div;
118 
119 	if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
120 		pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
121 	else
122 		pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
123 
124 	div = DIV_ROUND_UP(pll_rate, rate) - 1;
125 	if (div <= 0x3f)
126 		rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
127 			     div << SFC_CLK_DIV_SHIFT);
128 	else
129 		debug("Unsupported sfc clk rate:%d\n", rate);
130 
131 	return DIV_TO_RATE(pll_rate, div);
132 }
133 
134 static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
135 {
136 	u32 div, val;
137 
138 	val = readl(&cru->clksel_con[22]);
139 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
140 			       CLK_SARADC_DIV_CON_WIDTH);
141 
142 	return DIV_TO_RATE(OSC_HZ, div);
143 }
144 
145 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
146 {
147 	int src_clk_div;
148 
149 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
150 	assert(src_clk_div < 128);
151 
152 	rk_clrsetreg(&cru->clksel_con[22],
153 		     CLK_SARADC_DIV_CON_MASK,
154 		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
155 
156 	return rv1108_saradc_get_clk(cru);
157 }
158 
159 static ulong rv1108_clk_get_rate(struct clk *clk)
160 {
161 	struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
162 
163 	switch (clk->id) {
164 	case 0 ... 63:
165 		return rkclk_pll_get_rate(priv->cru, clk->id);
166 	case SCLK_SARADC:
167 		return rv1108_saradc_get_clk(priv->cru);
168 	default:
169 		return -ENOENT;
170 	}
171 }
172 
173 static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
174 {
175 	struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
176 	ulong new_rate;
177 
178 	switch (clk->id) {
179 	case SCLK_MAC:
180 		new_rate = rv1108_mac_set_clk(priv->cru, rate);
181 		break;
182 	case SCLK_SFC:
183 		new_rate = rv1108_sfc_set_clk(priv->cru, rate);
184 		break;
185 	case SCLK_SARADC:
186 		new_rate = rv1108_saradc_set_clk(priv->cru, rate);
187 		break;
188 	default:
189 		return -ENOENT;
190 	}
191 
192 	return new_rate;
193 }
194 
195 static const struct clk_ops rv1108_clk_ops = {
196 	.get_rate	= rv1108_clk_get_rate,
197 	.set_rate	= rv1108_clk_set_rate,
198 };
199 
200 static void rkclk_init(struct rv1108_cru *cru)
201 {
202 	unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM);
203 	unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR);
204 	unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
205 
206 	rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
207 		     0 << MAC_CLK_DIV_SHIFT);
208 
209 	printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
210 }
211 
212 static int rv1108_clk_probe(struct udevice *dev)
213 {
214 	struct rv1108_clk_priv *priv = dev_get_priv(dev);
215 
216 	priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev);
217 
218 	rkclk_init(priv->cru);
219 
220 	return 0;
221 }
222 
223 static int rv1108_clk_bind(struct udevice *dev)
224 {
225 	int ret;
226 	struct udevice *sys_child;
227 	struct sysreset_reg *priv;
228 
229 	/* The reset driver does not have a device node, so bind it here */
230 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
231 				 &sys_child);
232 	if (ret) {
233 		debug("Warning: No sysreset driver: ret=%d\n", ret);
234 	} else {
235 		priv = malloc(sizeof(struct sysreset_reg));
236 		priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
237 						    glb_srst_fst_val);
238 		priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
239 						    glb_srst_snd_val);
240 		sys_child->priv = priv;
241 	}
242 
243 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
244 	ret = offsetof(struct rk3368_cru, softrst_con[0]);
245 	ret = rockchip_reset_bind(dev, ret, 13);
246 	if (ret)
247 		debug("Warning: software reset driver bind faile\n");
248 #endif
249 
250 	return 0;
251 }
252 
253 static const struct udevice_id rv1108_clk_ids[] = {
254 	{ .compatible = "rockchip,rv1108-cru" },
255 	{ }
256 };
257 
258 U_BOOT_DRIVER(clk_rv1108) = {
259 	.name		= "clk_rv1108",
260 	.id		= UCLASS_CLK,
261 	.of_match	= rv1108_clk_ids,
262 	.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
263 	.ops		= &rv1108_clk_ops,
264 	.bind		= rv1108_clk_bind,
265 	.probe		= rv1108_clk_probe,
266 };
267