1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 * Author: Andy Yan <andy.yan@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cru_rv1108.h> 16 #include <asm/arch/hardware.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/rv1108-cru.h> 19 20 enum { 21 VCO_MAX_HZ = 2400U * 1000000, 22 VCO_MIN_HZ = 600 * 1000000, 23 OUTPUT_MAX_HZ = 2400U * 1000000, 24 OUTPUT_MIN_HZ = 24 * 1000000, 25 }; 26 27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 28 29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 30 .refdiv = _refdiv,\ 31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 33 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 34 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 35 #hz "Hz cannot be hit with PLL "\ 36 "divisors on line " __stringify(__LINE__)); 37 38 /* use integer mode */ 39 static inline int rv1108_pll_id(enum rk_clk_id clk_id) 40 { 41 int id = 0; 42 43 switch (clk_id) { 44 case CLK_ARM: 45 case CLK_DDR: 46 id = clk_id - 1; 47 break; 48 case CLK_GENERAL: 49 id = 2; 50 break; 51 default: 52 printf("invalid pll id:%d\n", clk_id); 53 id = -1; 54 break; 55 } 56 57 return id; 58 } 59 60 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, 61 enum rk_clk_id clk_id) 62 { 63 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 64 uint32_t con0, con1, con3; 65 int pll_id = rv1108_pll_id(clk_id); 66 struct rv1108_pll *pll = &cru->pll[pll_id]; 67 uint32_t freq; 68 69 con3 = readl(&pll->con3); 70 71 if (con3 & WORK_MODE_MASK) { 72 con0 = readl(&pll->con0); 73 con1 = readl(&pll->con1); 74 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; 75 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; 76 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; 77 refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; 78 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 79 } else { 80 freq = OSC_HZ; 81 } 82 83 return freq; 84 } 85 86 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) 87 { 88 uint32_t con = readl(&cru->clksel_con[24]); 89 ulong pll_rate; 90 uint8_t div; 91 92 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) 93 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); 94 else 95 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); 96 97 /*default set 50MHZ for gmac*/ 98 if (!rate) 99 rate = 50000000; 100 101 div = DIV_ROUND_UP(pll_rate, rate) - 1; 102 if (div <= 0x1f) 103 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, 104 div << MAC_CLK_DIV_SHIFT); 105 else 106 debug("Unsupported div for gmac:%d\n", div); 107 108 return DIV_TO_RATE(pll_rate, div); 109 } 110 111 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) 112 { 113 u32 con = readl(&cru->clksel_con[27]); 114 u32 pll_rate; 115 u32 div; 116 117 if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL) 118 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); 119 else 120 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); 121 122 div = DIV_ROUND_UP(pll_rate, rate) - 1; 123 if (div <= 0x3f) 124 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, 125 div << SFC_CLK_DIV_SHIFT); 126 else 127 debug("Unsupported sfc clk rate:%d\n", rate); 128 129 return DIV_TO_RATE(pll_rate, div); 130 } 131 132 static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru) 133 { 134 u32 div, val; 135 136 val = readl(&cru->clksel_con[22]); 137 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 138 CLK_SARADC_DIV_CON_WIDTH); 139 140 return DIV_TO_RATE(OSC_HZ, div); 141 } 142 143 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) 144 { 145 int src_clk_div; 146 147 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 148 assert(src_clk_div < 128); 149 150 rk_clrsetreg(&cru->clksel_con[22], 151 CLK_SARADC_DIV_CON_MASK, 152 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 153 154 return rv1108_saradc_get_clk(cru); 155 } 156 157 static ulong rv1108_clk_get_rate(struct clk *clk) 158 { 159 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); 160 161 switch (clk->id) { 162 case 0 ... 63: 163 return rkclk_pll_get_rate(priv->cru, clk->id); 164 case SCLK_SARADC: 165 return rv1108_saradc_get_clk(priv->cru); 166 default: 167 return -ENOENT; 168 } 169 } 170 171 static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) 172 { 173 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); 174 ulong new_rate; 175 176 switch (clk->id) { 177 case SCLK_MAC: 178 new_rate = rv1108_mac_set_clk(priv->cru, rate); 179 break; 180 case SCLK_SFC: 181 new_rate = rv1108_sfc_set_clk(priv->cru, rate); 182 break; 183 case SCLK_SARADC: 184 new_rate = rv1108_saradc_set_clk(priv->cru, rate); 185 break; 186 default: 187 return -ENOENT; 188 } 189 190 return new_rate; 191 } 192 193 static const struct clk_ops rv1108_clk_ops = { 194 .get_rate = rv1108_clk_get_rate, 195 .set_rate = rv1108_clk_set_rate, 196 }; 197 198 static void rkclk_init(struct rv1108_cru *cru) 199 { 200 unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM); 201 unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); 202 unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); 203 204 rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, 205 0 << MAC_CLK_DIV_SHIFT); 206 207 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); 208 } 209 210 static int rv1108_clk_ofdata_to_platdata(struct udevice *dev) 211 { 212 struct rv1108_clk_priv *priv = dev_get_priv(dev); 213 214 priv->cru = dev_read_addr_ptr(dev); 215 216 return 0; 217 } 218 219 static int rv1108_clk_probe(struct udevice *dev) 220 { 221 struct rv1108_clk_priv *priv = dev_get_priv(dev); 222 223 rkclk_init(priv->cru); 224 225 return 0; 226 } 227 228 static int rv1108_clk_bind(struct udevice *dev) 229 { 230 int ret; 231 struct udevice *sys_child; 232 struct sysreset_reg *priv; 233 234 /* The reset driver does not have a device node, so bind it here */ 235 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 236 &sys_child); 237 if (ret) { 238 debug("Warning: No sysreset driver: ret=%d\n", ret); 239 } else { 240 priv = malloc(sizeof(struct sysreset_reg)); 241 priv->glb_srst_fst_value = offsetof(struct rv1108_cru, 242 glb_srst_fst_val); 243 priv->glb_srst_snd_value = offsetof(struct rv1108_cru, 244 glb_srst_snd_val); 245 sys_child->priv = priv; 246 } 247 248 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) 249 ret = offsetof(struct rk3368_cru, softrst_con[0]); 250 ret = rockchip_reset_bind(dev, ret, 13); 251 if (ret) 252 debug("Warning: software reset driver bind faile\n"); 253 #endif 254 255 return 0; 256 } 257 258 static const struct udevice_id rv1108_clk_ids[] = { 259 { .compatible = "rockchip,rv1108-cru" }, 260 { } 261 }; 262 263 U_BOOT_DRIVER(clk_rv1108) = { 264 .name = "clk_rv1108", 265 .id = UCLASS_CLK, 266 .of_match = rv1108_clk_ids, 267 .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv), 268 .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata, 269 .ops = &rv1108_clk_ops, 270 .bind = rv1108_clk_bind, 271 .probe = rv1108_clk_probe, 272 }; 273