1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 }; 42 43 #define RATE_TO_DIV(input_rate, output_rate) \ 44 ((input_rate) / (output_rate) - 1); 45 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 46 47 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 48 .refdiv = _refdiv,\ 49 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 50 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 51 52 #if defined(CONFIG_SPL_BUILD) 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); 55 #else 56 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 57 #endif 58 59 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 60 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 61 62 static const struct pll_div *apll_l_cfgs[] = { 63 [APLL_L_1600_MHZ] = &apll_l_1600_cfg, 64 [APLL_L_600_MHZ] = &apll_l_600_cfg, 65 }; 66 67 enum { 68 /* PLL_CON0 */ 69 PLL_FBDIV_MASK = 0xfff, 70 PLL_FBDIV_SHIFT = 0, 71 72 /* PLL_CON1 */ 73 PLL_POSTDIV2_SHIFT = 12, 74 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 75 PLL_POSTDIV1_SHIFT = 8, 76 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 77 PLL_REFDIV_MASK = 0x3f, 78 PLL_REFDIV_SHIFT = 0, 79 80 /* PLL_CON2 */ 81 PLL_LOCK_STATUS_SHIFT = 31, 82 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 83 PLL_FRACDIV_MASK = 0xffffff, 84 PLL_FRACDIV_SHIFT = 0, 85 86 /* PLL_CON3 */ 87 PLL_MODE_SHIFT = 8, 88 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 89 PLL_MODE_SLOW = 0, 90 PLL_MODE_NORM, 91 PLL_MODE_DEEP, 92 PLL_DSMPD_SHIFT = 3, 93 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 94 PLL_INTEGER_MODE = 1, 95 96 /* PMUCRU_CLKSEL_CON0 */ 97 PMU_PCLK_DIV_CON_MASK = 0x1f, 98 PMU_PCLK_DIV_CON_SHIFT = 0, 99 100 /* PMUCRU_CLKSEL_CON1 */ 101 SPI3_PLL_SEL_SHIFT = 7, 102 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 103 SPI3_PLL_SEL_24M = 0, 104 SPI3_PLL_SEL_PPLL = 1, 105 SPI3_DIV_CON_SHIFT = 0x0, 106 SPI3_DIV_CON_MASK = 0x7f, 107 108 /* PMUCRU_CLKSEL_CON2 */ 109 I2C_DIV_CON_MASK = 0x7f, 110 CLK_I2C8_DIV_CON_SHIFT = 8, 111 CLK_I2C0_DIV_CON_SHIFT = 0, 112 113 /* PMUCRU_CLKSEL_CON3 */ 114 CLK_I2C4_DIV_CON_SHIFT = 0, 115 116 /* CLKSEL_CON0 */ 117 ACLKM_CORE_L_DIV_CON_SHIFT = 8, 118 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT, 119 CLK_CORE_L_PLL_SEL_SHIFT = 6, 120 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT, 121 CLK_CORE_L_PLL_SEL_ALPLL = 0x0, 122 CLK_CORE_L_PLL_SEL_ABPLL = 0x1, 123 CLK_CORE_L_PLL_SEL_DPLL = 0x10, 124 CLK_CORE_L_PLL_SEL_GPLL = 0x11, 125 CLK_CORE_L_DIV_MASK = 0x1f, 126 CLK_CORE_L_DIV_SHIFT = 0, 127 128 /* CLKSEL_CON1 */ 129 PCLK_DBG_L_DIV_SHIFT = 0x8, 130 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT, 131 ATCLK_CORE_L_DIV_SHIFT = 0, 132 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, 133 134 /* CLKSEL_CON14 */ 135 PCLK_PERIHP_DIV_CON_SHIFT = 12, 136 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 137 HCLK_PERIHP_DIV_CON_SHIFT = 8, 138 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 139 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 140 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 141 ACLK_PERIHP_PLL_SEL_CPLL = 0, 142 ACLK_PERIHP_PLL_SEL_GPLL = 1, 143 ACLK_PERIHP_DIV_CON_SHIFT = 0, 144 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 145 146 /* CLKSEL_CON21 */ 147 ACLK_EMMC_PLL_SEL_SHIFT = 7, 148 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 149 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 150 ACLK_EMMC_DIV_CON_SHIFT = 0, 151 ACLK_EMMC_DIV_CON_MASK = 0x1f, 152 153 /* CLKSEL_CON22 */ 154 CLK_EMMC_PLL_SHIFT = 8, 155 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 156 CLK_EMMC_PLL_SEL_GPLL = 0x1, 157 CLK_EMMC_PLL_SEL_24M = 0x5, 158 CLK_EMMC_DIV_CON_SHIFT = 0, 159 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 160 161 /* CLKSEL_CON23 */ 162 PCLK_PERILP0_DIV_CON_SHIFT = 12, 163 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 164 HCLK_PERILP0_DIV_CON_SHIFT = 8, 165 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 166 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 167 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 168 ACLK_PERILP0_PLL_SEL_CPLL = 0, 169 ACLK_PERILP0_PLL_SEL_GPLL = 1, 170 ACLK_PERILP0_DIV_CON_SHIFT = 0, 171 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 172 173 /* CLKSEL_CON25 */ 174 PCLK_PERILP1_DIV_CON_SHIFT = 8, 175 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 176 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 177 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 178 HCLK_PERILP1_PLL_SEL_CPLL = 0, 179 HCLK_PERILP1_PLL_SEL_GPLL = 1, 180 HCLK_PERILP1_DIV_CON_SHIFT = 0, 181 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 182 183 /* CLKSEL_CON26 */ 184 CLK_SARADC_DIV_CON_SHIFT = 8, 185 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 186 CLK_SARADC_DIV_CON_WIDTH = 8, 187 188 /* CLKSEL_CON27 */ 189 CLK_TSADC_SEL_X24M = 0x0, 190 CLK_TSADC_SEL_SHIFT = 15, 191 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 192 CLK_TSADC_DIV_CON_SHIFT = 0, 193 CLK_TSADC_DIV_CON_MASK = 0x3ff, 194 195 /* CLKSEL_CON47 & CLKSEL_CON48 */ 196 ACLK_VOP_PLL_SEL_SHIFT = 6, 197 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 198 ACLK_VOP_PLL_SEL_CPLL = 0x1, 199 ACLK_VOP_DIV_CON_SHIFT = 0, 200 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 201 202 /* CLKSEL_CON49 & CLKSEL_CON50 */ 203 DCLK_VOP_DCLK_SEL_SHIFT = 11, 204 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 205 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 206 DCLK_VOP_PLL_SEL_SHIFT = 8, 207 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 208 DCLK_VOP_PLL_SEL_VPLL = 0, 209 DCLK_VOP_DIV_CON_MASK = 0xff, 210 DCLK_VOP_DIV_CON_SHIFT = 0, 211 212 /* CLKSEL_CON58 */ 213 CLK_SPI_PLL_SEL_WIDTH = 1, 214 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 215 CLK_SPI_PLL_SEL_CPLL = 0, 216 CLK_SPI_PLL_SEL_GPLL = 1, 217 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 218 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 219 220 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 221 CLK_SPI5_PLL_SEL_SHIFT = 15, 222 223 /* CLKSEL_CON59 */ 224 CLK_SPI1_PLL_SEL_SHIFT = 15, 225 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 226 CLK_SPI0_PLL_SEL_SHIFT = 7, 227 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 228 229 /* CLKSEL_CON60 */ 230 CLK_SPI4_PLL_SEL_SHIFT = 15, 231 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 232 CLK_SPI2_PLL_SEL_SHIFT = 7, 233 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 234 235 /* CLKSEL_CON61 */ 236 CLK_I2C_PLL_SEL_MASK = 1, 237 CLK_I2C_PLL_SEL_CPLL = 0, 238 CLK_I2C_PLL_SEL_GPLL = 1, 239 CLK_I2C5_PLL_SEL_SHIFT = 15, 240 CLK_I2C5_DIV_CON_SHIFT = 8, 241 CLK_I2C1_PLL_SEL_SHIFT = 7, 242 CLK_I2C1_DIV_CON_SHIFT = 0, 243 244 /* CLKSEL_CON62 */ 245 CLK_I2C6_PLL_SEL_SHIFT = 15, 246 CLK_I2C6_DIV_CON_SHIFT = 8, 247 CLK_I2C2_PLL_SEL_SHIFT = 7, 248 CLK_I2C2_DIV_CON_SHIFT = 0, 249 250 /* CLKSEL_CON63 */ 251 CLK_I2C7_PLL_SEL_SHIFT = 15, 252 CLK_I2C7_DIV_CON_SHIFT = 8, 253 CLK_I2C3_PLL_SEL_SHIFT = 7, 254 CLK_I2C3_DIV_CON_SHIFT = 0, 255 256 /* CRU_SOFTRST_CON4 */ 257 RESETN_DDR0_REQ_SHIFT = 8, 258 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 259 RESETN_DDRPHY0_REQ_SHIFT = 9, 260 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 261 RESETN_DDR1_REQ_SHIFT = 12, 262 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 263 RESETN_DDRPHY1_REQ_SHIFT = 13, 264 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 265 }; 266 267 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 268 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 269 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 270 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 271 272 /* 273 * the div restructions of pll in integer mode, these are defined in 274 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 275 */ 276 #define PLL_DIV_MIN 16 277 #define PLL_DIV_MAX 3200 278 279 /* 280 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 281 * Formulas also embedded within the Fractional PLL Verilog model: 282 * If DSMPD = 1 (DSM is disabled, "integer mode") 283 * FOUTVCO = FREF / REFDIV * FBDIV 284 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 285 * Where: 286 * FOUTVCO = Fractional PLL non-divided output frequency 287 * FOUTPOSTDIV = Fractional PLL divided output frequency 288 * (output of second post divider) 289 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 290 * REFDIV = Fractional PLL input reference clock divider 291 * FBDIV = Integer value programmed into feedback divide 292 * 293 */ 294 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 295 { 296 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 297 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 298 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 299 300 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 301 "postdiv2=%d, vco=%u khz, output=%u khz\n", 302 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 303 div->postdiv2, vco_khz, output_khz); 304 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 305 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 306 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 307 308 /* 309 * When power on or changing PLL setting, 310 * we must force PLL into slow mode to ensure output stable clock. 311 */ 312 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 313 PLL_MODE_SLOW << PLL_MODE_SHIFT); 314 315 /* use integer mode */ 316 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 317 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 318 319 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 320 div->fbdiv << PLL_FBDIV_SHIFT); 321 rk_clrsetreg(&pll_con[1], 322 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 323 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 324 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 325 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 326 (div->refdiv << PLL_REFDIV_SHIFT)); 327 328 /* waiting for pll lock */ 329 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 330 udelay(1); 331 332 /* pll enter normal mode */ 333 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 334 PLL_MODE_NORM << PLL_MODE_SHIFT); 335 } 336 337 static int pll_para_config(u32 freq_hz, struct pll_div *div) 338 { 339 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 340 u32 postdiv1, postdiv2 = 1; 341 u32 fref_khz; 342 u32 diff_khz, best_diff_khz; 343 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 344 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 345 u32 vco_khz; 346 u32 freq_khz = freq_hz / KHz; 347 348 if (!freq_hz) { 349 printf("%s: the frequency can't be 0 Hz\n", __func__); 350 return -1; 351 } 352 353 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 354 if (postdiv1 > max_postdiv1) { 355 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 356 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 357 } 358 359 vco_khz = freq_khz * postdiv1 * postdiv2; 360 361 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 362 postdiv2 > max_postdiv2) { 363 printf("%s: Cannot find out a supported VCO" 364 " for Frequency (%uHz).\n", __func__, freq_hz); 365 return -1; 366 } 367 368 div->postdiv1 = postdiv1; 369 div->postdiv2 = postdiv2; 370 371 best_diff_khz = vco_khz; 372 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 373 fref_khz = ref_khz / refdiv; 374 375 fbdiv = vco_khz / fref_khz; 376 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 377 continue; 378 diff_khz = vco_khz - fbdiv * fref_khz; 379 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 380 fbdiv++; 381 diff_khz = fref_khz - diff_khz; 382 } 383 384 if (diff_khz >= best_diff_khz) 385 continue; 386 387 best_diff_khz = diff_khz; 388 div->refdiv = refdiv; 389 div->fbdiv = fbdiv; 390 } 391 392 if (best_diff_khz > 4 * (MHz/KHz)) { 393 printf("%s: Failed to match output frequency %u, " 394 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 395 best_diff_khz * KHz); 396 return -1; 397 } 398 return 0; 399 } 400 401 #ifdef CONFIG_SPL_BUILD 402 static void rkclk_init(struct rk3399_cru *cru) 403 { 404 u32 aclk_div; 405 u32 hclk_div; 406 u32 pclk_div; 407 408 /* 409 * some cru registers changed by bootrom, we'd better reset them to 410 * reset/default values described in TRM to avoid confusion in kernel. 411 * Please consider these three lines as a fix of bootrom bug. 412 */ 413 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 414 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 415 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 416 417 /* configure gpll cpll */ 418 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 419 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); 420 421 /* configure perihp aclk, hclk, pclk */ 422 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 423 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 424 425 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 426 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 427 PERIHP_ACLK_HZ && (hclk_div < 0x4)); 428 429 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 430 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 431 PERIHP_ACLK_HZ && (pclk_div < 0x7)); 432 433 rk_clrsetreg(&cru->clksel_con[14], 434 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 435 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 436 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 437 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 438 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 439 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 440 441 /* configure perilp0 aclk, hclk, pclk */ 442 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 443 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 444 445 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 446 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 447 PERILP0_ACLK_HZ && (hclk_div < 0x4)); 448 449 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 450 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 451 PERILP0_ACLK_HZ && (pclk_div < 0x7)); 452 453 rk_clrsetreg(&cru->clksel_con[23], 454 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 455 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 456 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 457 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 458 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 459 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 460 461 /* perilp1 hclk select gpll as source */ 462 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 463 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 464 GPLL_HZ && (hclk_div < 0x1f)); 465 466 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; 467 assert((pclk_div + 1) * PERILP1_HCLK_HZ == 468 PERILP1_HCLK_HZ && (hclk_div < 0x7)); 469 470 rk_clrsetreg(&cru->clksel_con[25], 471 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 472 HCLK_PERILP1_PLL_SEL_MASK, 473 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 474 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 475 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 476 } 477 #endif 478 479 void rk3399_configure_cpu(struct rk3399_cru *cru, 480 enum apll_l_frequencies apll_l_freq) 481 { 482 u32 aclkm_div; 483 u32 pclk_dbg_div; 484 u32 atclk_div; 485 486 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); 487 488 aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; 489 assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && 490 aclkm_div < 0x1f); 491 492 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; 493 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && 494 pclk_dbg_div < 0x1f); 495 496 atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; 497 assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && 498 atclk_div < 0x1f); 499 500 rk_clrsetreg(&cru->clksel_con[0], 501 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK | 502 CLK_CORE_L_DIV_MASK, 503 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | 504 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT | 505 0 << CLK_CORE_L_DIV_SHIFT); 506 507 rk_clrsetreg(&cru->clksel_con[1], 508 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK, 509 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | 510 atclk_div << ATCLK_CORE_L_DIV_SHIFT); 511 } 512 #define I2C_CLK_REG_MASK(bus) \ 513 (I2C_DIV_CON_MASK << \ 514 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 515 CLK_I2C_PLL_SEL_MASK << \ 516 CLK_I2C ##bus## _PLL_SEL_SHIFT) 517 518 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 519 ((clk_div - 1) << \ 520 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 521 CLK_I2C_PLL_SEL_GPLL << \ 522 CLK_I2C ##bus## _PLL_SEL_SHIFT) 523 524 #define I2C_CLK_DIV_VALUE(con, bus) \ 525 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 526 I2C_DIV_CON_MASK; 527 528 #define I2C_PMUCLK_REG_MASK(bus) \ 529 (I2C_DIV_CON_MASK << \ 530 CLK_I2C ##bus## _DIV_CON_SHIFT) 531 532 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 533 ((clk_div - 1) << \ 534 CLK_I2C ##bus## _DIV_CON_SHIFT) 535 536 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 537 { 538 u32 div, con; 539 540 switch (clk_id) { 541 case SCLK_I2C1: 542 con = readl(&cru->clksel_con[61]); 543 div = I2C_CLK_DIV_VALUE(con, 1); 544 break; 545 case SCLK_I2C2: 546 con = readl(&cru->clksel_con[62]); 547 div = I2C_CLK_DIV_VALUE(con, 2); 548 break; 549 case SCLK_I2C3: 550 con = readl(&cru->clksel_con[63]); 551 div = I2C_CLK_DIV_VALUE(con, 3); 552 break; 553 case SCLK_I2C5: 554 con = readl(&cru->clksel_con[61]); 555 div = I2C_CLK_DIV_VALUE(con, 5); 556 break; 557 case SCLK_I2C6: 558 con = readl(&cru->clksel_con[62]); 559 div = I2C_CLK_DIV_VALUE(con, 6); 560 break; 561 case SCLK_I2C7: 562 con = readl(&cru->clksel_con[63]); 563 div = I2C_CLK_DIV_VALUE(con, 7); 564 break; 565 default: 566 printf("do not support this i2c bus\n"); 567 return -EINVAL; 568 } 569 570 return DIV_TO_RATE(GPLL_HZ, div); 571 } 572 573 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 574 { 575 int src_clk_div; 576 577 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 578 src_clk_div = GPLL_HZ / hz; 579 assert(src_clk_div - 1 < 127); 580 581 switch (clk_id) { 582 case SCLK_I2C1: 583 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 584 I2C_CLK_REG_VALUE(1, src_clk_div)); 585 break; 586 case SCLK_I2C2: 587 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 588 I2C_CLK_REG_VALUE(2, src_clk_div)); 589 break; 590 case SCLK_I2C3: 591 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 592 I2C_CLK_REG_VALUE(3, src_clk_div)); 593 break; 594 case SCLK_I2C5: 595 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 596 I2C_CLK_REG_VALUE(5, src_clk_div)); 597 break; 598 case SCLK_I2C6: 599 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 600 I2C_CLK_REG_VALUE(6, src_clk_div)); 601 break; 602 case SCLK_I2C7: 603 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 604 I2C_CLK_REG_VALUE(7, src_clk_div)); 605 break; 606 default: 607 printf("do not support this i2c bus\n"); 608 return -EINVAL; 609 } 610 611 return rk3399_i2c_get_clk(cru, clk_id); 612 } 613 614 /* 615 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 616 * to select either CPLL or GPLL as the clock-parent. The location within 617 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 618 */ 619 620 struct spi_clkreg { 621 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 622 uint8_t div_shift; 623 uint8_t sel_shift; 624 }; 625 626 /* 627 * The entries are numbered relative to their offset from SCLK_SPI0. 628 * 629 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 630 * logic is not supported). 631 */ 632 static const struct spi_clkreg spi_clkregs[] = { 633 [0] = { .reg = 59, 634 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 635 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 636 [1] = { .reg = 59, 637 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 638 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 639 [2] = { .reg = 60, 640 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 641 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 642 [3] = { .reg = 60, 643 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 644 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 645 [4] = { .reg = 58, 646 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 647 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 648 }; 649 650 static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) 651 { 652 return (val >> shift) & ((1 << width) - 1); 653 } 654 655 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 656 { 657 const struct spi_clkreg *spiclk = NULL; 658 u32 div, val; 659 660 switch (clk_id) { 661 case SCLK_SPI0 ... SCLK_SPI5: 662 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 663 break; 664 665 default: 666 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 667 return -EINVAL; 668 } 669 670 val = readl(&cru->clksel_con[spiclk->reg]); 671 div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift); 672 673 return DIV_TO_RATE(GPLL_HZ, div); 674 } 675 676 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 677 { 678 const struct spi_clkreg *spiclk = NULL; 679 int src_clk_div; 680 681 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 682 assert(src_clk_div < 128); 683 684 switch (clk_id) { 685 case SCLK_SPI1 ... SCLK_SPI5: 686 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 687 break; 688 689 default: 690 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 691 return -EINVAL; 692 } 693 694 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 695 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 696 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 697 ((src_clk_div << spiclk->div_shift) | 698 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 699 700 return rk3399_spi_get_clk(cru, clk_id); 701 } 702 703 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 704 { 705 struct pll_div vpll_config = {0}; 706 int aclk_vop = 198*MHz; 707 void *aclkreg_addr, *dclkreg_addr; 708 u32 div; 709 710 switch (clk_id) { 711 case DCLK_VOP0: 712 aclkreg_addr = &cru->clksel_con[47]; 713 dclkreg_addr = &cru->clksel_con[49]; 714 break; 715 case DCLK_VOP1: 716 aclkreg_addr = &cru->clksel_con[48]; 717 dclkreg_addr = &cru->clksel_con[50]; 718 break; 719 default: 720 return -EINVAL; 721 } 722 /* vop aclk source clk: cpll */ 723 div = CPLL_HZ / aclk_vop; 724 assert(div - 1 < 32); 725 726 rk_clrsetreg(aclkreg_addr, 727 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 728 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | 729 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 730 731 /* vop dclk source from vpll, and equals to vpll(means div == 1) */ 732 if (pll_para_config(hz, &vpll_config)) 733 return -1; 734 735 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 736 737 rk_clrsetreg(dclkreg_addr, 738 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| 739 DCLK_VOP_DIV_CON_MASK, 740 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 741 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | 742 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 743 744 return hz; 745 } 746 747 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 748 { 749 u32 div, con; 750 751 switch (clk_id) { 752 case HCLK_SDMMC: 753 case SCLK_SDMMC: 754 con = readl(&cru->clksel_con[16]); 755 /* dwmmc controller have internal div 2 */ 756 div = 2; 757 break; 758 case SCLK_EMMC: 759 con = readl(&cru->clksel_con[21]); 760 div = 1; 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 767 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 768 == CLK_EMMC_PLL_SEL_24M) 769 return DIV_TO_RATE(OSC_HZ, div); 770 else 771 return DIV_TO_RATE(GPLL_HZ, div); 772 } 773 774 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 775 ulong clk_id, ulong set_rate) 776 { 777 int src_clk_div; 778 int aclk_emmc = 198*MHz; 779 780 switch (clk_id) { 781 case HCLK_SDMMC: 782 case SCLK_SDMMC: 783 /* Select clk_sdmmc source from GPLL by default */ 784 /* mmc clock defaulg div 2 internal, provide double in cru */ 785 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 786 787 if (src_clk_div > 128) { 788 /* use 24MHz source for 400KHz clock */ 789 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 790 assert(src_clk_div - 1 < 128); 791 rk_clrsetreg(&cru->clksel_con[16], 792 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 793 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 794 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 795 } else { 796 rk_clrsetreg(&cru->clksel_con[16], 797 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 798 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 799 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 800 } 801 break; 802 case SCLK_EMMC: 803 /* Select aclk_emmc source from GPLL */ 804 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 805 assert(src_clk_div - 1 < 32); 806 807 rk_clrsetreg(&cru->clksel_con[21], 808 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 809 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 810 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 811 812 /* Select clk_emmc source from GPLL too */ 813 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 814 assert(src_clk_div - 1 < 128); 815 816 rk_clrsetreg(&cru->clksel_con[22], 817 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 818 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 819 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 820 break; 821 default: 822 return -EINVAL; 823 } 824 return rk3399_mmc_get_clk(cru, clk_id); 825 } 826 827 #define PMUSGRF_DDR_RGN_CON16 0xff330040 828 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 829 ulong set_rate) 830 { 831 struct pll_div dpll_cfg; 832 833 /* IC ECO bug, need to set this register */ 834 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 835 836 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 837 switch (set_rate) { 838 case 200*MHz: 839 dpll_cfg = (struct pll_div) 840 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 841 break; 842 case 300*MHz: 843 dpll_cfg = (struct pll_div) 844 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 845 break; 846 case 666*MHz: 847 dpll_cfg = (struct pll_div) 848 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 849 break; 850 case 800*MHz: 851 dpll_cfg = (struct pll_div) 852 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 853 break; 854 case 933*MHz: 855 dpll_cfg = (struct pll_div) 856 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 857 break; 858 default: 859 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 860 } 861 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 862 863 return set_rate; 864 } 865 866 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 867 { 868 u32 div, val; 869 870 val = readl(&cru->clksel_con[26]); 871 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 872 CLK_SARADC_DIV_CON_WIDTH); 873 874 return DIV_TO_RATE(OSC_HZ, div); 875 } 876 877 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 878 { 879 int src_clk_div; 880 881 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 882 assert(src_clk_div < 128); 883 884 rk_clrsetreg(&cru->clksel_con[26], 885 CLK_SARADC_DIV_CON_MASK, 886 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 887 888 return rk3399_saradc_get_clk(cru); 889 } 890 891 static ulong rk3399_clk_get_rate(struct clk *clk) 892 { 893 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 894 ulong rate = 0; 895 896 switch (clk->id) { 897 case 0 ... 63: 898 return 0; 899 case HCLK_SDMMC: 900 case SCLK_SDMMC: 901 case SCLK_EMMC: 902 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 903 break; 904 case SCLK_I2C1: 905 case SCLK_I2C2: 906 case SCLK_I2C3: 907 case SCLK_I2C5: 908 case SCLK_I2C6: 909 case SCLK_I2C7: 910 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 911 break; 912 case SCLK_SPI0...SCLK_SPI5: 913 rate = rk3399_spi_get_clk(priv->cru, clk->id); 914 break; 915 case SCLK_UART0: 916 case SCLK_UART2: 917 return 24000000; 918 break; 919 case PCLK_HDMI_CTRL: 920 break; 921 case DCLK_VOP0: 922 case DCLK_VOP1: 923 break; 924 case PCLK_EFUSE1024NS: 925 break; 926 case SCLK_SARADC: 927 rate = rk3399_saradc_get_clk(priv->cru); 928 break; 929 default: 930 return -ENOENT; 931 } 932 933 return rate; 934 } 935 936 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 937 { 938 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 939 ulong ret = 0; 940 941 switch (clk->id) { 942 case 0 ... 63: 943 return 0; 944 case HCLK_SDMMC: 945 case SCLK_SDMMC: 946 case SCLK_EMMC: 947 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 948 break; 949 case SCLK_MAC: 950 /* nothing to do, as this is an external clock */ 951 ret = rate; 952 break; 953 case SCLK_I2C1: 954 case SCLK_I2C2: 955 case SCLK_I2C3: 956 case SCLK_I2C5: 957 case SCLK_I2C6: 958 case SCLK_I2C7: 959 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 960 break; 961 case SCLK_SPI0...SCLK_SPI5: 962 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 963 break; 964 case PCLK_HDMI_CTRL: 965 case PCLK_VIO_GRF: 966 /* the PCLK gates for video are enabled by default */ 967 break; 968 case DCLK_VOP0: 969 case DCLK_VOP1: 970 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 971 break; 972 case SCLK_DDRCLK: 973 ret = rk3399_ddr_set_clk(priv->cru, rate); 974 break; 975 case PCLK_EFUSE1024NS: 976 break; 977 case SCLK_SARADC: 978 ret = rk3399_saradc_set_clk(priv->cru, rate); 979 break; 980 default: 981 return -ENOENT; 982 } 983 984 return ret; 985 } 986 987 static int rk3399_clk_enable(struct clk *clk) 988 { 989 switch (clk->id) { 990 case HCLK_HOST0: 991 case HCLK_HOST0_ARB: 992 case HCLK_HOST1: 993 case HCLK_HOST1_ARB: 994 return 0; 995 } 996 997 debug("%s: unsupported clk %ld\n", __func__, clk->id); 998 return -ENOENT; 999 } 1000 1001 static struct clk_ops rk3399_clk_ops = { 1002 .get_rate = rk3399_clk_get_rate, 1003 .set_rate = rk3399_clk_set_rate, 1004 .enable = rk3399_clk_enable, 1005 }; 1006 1007 static int rk3399_clk_probe(struct udevice *dev) 1008 { 1009 #ifdef CONFIG_SPL_BUILD 1010 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1011 1012 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1013 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1014 1015 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1016 #endif 1017 rkclk_init(priv->cru); 1018 #endif 1019 return 0; 1020 } 1021 1022 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1023 { 1024 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1025 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1026 1027 priv->cru = dev_read_addr_ptr(dev); 1028 #endif 1029 return 0; 1030 } 1031 1032 static int rk3399_clk_bind(struct udevice *dev) 1033 { 1034 int ret; 1035 1036 /* The reset driver does not have a device node, so bind it here */ 1037 ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev); 1038 if (ret) 1039 printf("Warning: No RK3399 reset driver: ret=%d\n", ret); 1040 1041 return 0; 1042 } 1043 1044 static const struct udevice_id rk3399_clk_ids[] = { 1045 { .compatible = "rockchip,rk3399-cru" }, 1046 { } 1047 }; 1048 1049 U_BOOT_DRIVER(clk_rk3399) = { 1050 .name = "rockchip_rk3399_cru", 1051 .id = UCLASS_CLK, 1052 .of_match = rk3399_clk_ids, 1053 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1054 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1055 .ops = &rk3399_clk_ops, 1056 .bind = rk3399_clk_bind, 1057 .probe = rk3399_clk_probe, 1058 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1059 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1060 #endif 1061 }; 1062 1063 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1064 { 1065 u32 div, con; 1066 1067 switch (clk_id) { 1068 case SCLK_I2C0_PMU: 1069 con = readl(&pmucru->pmucru_clksel[2]); 1070 div = I2C_CLK_DIV_VALUE(con, 0); 1071 break; 1072 case SCLK_I2C4_PMU: 1073 con = readl(&pmucru->pmucru_clksel[3]); 1074 div = I2C_CLK_DIV_VALUE(con, 4); 1075 break; 1076 case SCLK_I2C8_PMU: 1077 con = readl(&pmucru->pmucru_clksel[2]); 1078 div = I2C_CLK_DIV_VALUE(con, 8); 1079 break; 1080 default: 1081 printf("do not support this i2c bus\n"); 1082 return -EINVAL; 1083 } 1084 1085 return DIV_TO_RATE(PPLL_HZ, div); 1086 } 1087 1088 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1089 uint hz) 1090 { 1091 int src_clk_div; 1092 1093 src_clk_div = PPLL_HZ / hz; 1094 assert(src_clk_div - 1 < 127); 1095 1096 switch (clk_id) { 1097 case SCLK_I2C0_PMU: 1098 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1099 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1100 break; 1101 case SCLK_I2C4_PMU: 1102 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1103 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1104 break; 1105 case SCLK_I2C8_PMU: 1106 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1107 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1108 break; 1109 default: 1110 printf("do not support this i2c bus\n"); 1111 return -EINVAL; 1112 } 1113 1114 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1115 } 1116 1117 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1118 { 1119 u32 div, con; 1120 1121 /* PWM closk rate is same as pclk_pmu */ 1122 con = readl(&pmucru->pmucru_clksel[0]); 1123 div = con & PMU_PCLK_DIV_CON_MASK; 1124 1125 return DIV_TO_RATE(PPLL_HZ, div); 1126 } 1127 1128 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1129 { 1130 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1131 ulong rate = 0; 1132 1133 switch (clk->id) { 1134 case PCLK_RKPWM_PMU: 1135 rate = rk3399_pwm_get_clk(priv->pmucru); 1136 break; 1137 case SCLK_I2C0_PMU: 1138 case SCLK_I2C4_PMU: 1139 case SCLK_I2C8_PMU: 1140 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1141 break; 1142 default: 1143 return -ENOENT; 1144 } 1145 1146 return rate; 1147 } 1148 1149 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1150 { 1151 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1152 ulong ret = 0; 1153 1154 switch (clk->id) { 1155 case SCLK_I2C0_PMU: 1156 case SCLK_I2C4_PMU: 1157 case SCLK_I2C8_PMU: 1158 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1159 break; 1160 default: 1161 return -ENOENT; 1162 } 1163 1164 return ret; 1165 } 1166 1167 static struct clk_ops rk3399_pmuclk_ops = { 1168 .get_rate = rk3399_pmuclk_get_rate, 1169 .set_rate = rk3399_pmuclk_set_rate, 1170 }; 1171 1172 #ifndef CONFIG_SPL_BUILD 1173 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1174 { 1175 u32 pclk_div; 1176 1177 /* configure pmu pll(ppll) */ 1178 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1179 1180 /* configure pmu pclk */ 1181 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1182 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1183 PMU_PCLK_DIV_CON_MASK, 1184 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1185 } 1186 #endif 1187 1188 static int rk3399_pmuclk_probe(struct udevice *dev) 1189 { 1190 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1191 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1192 #endif 1193 1194 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1195 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1196 1197 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1198 #endif 1199 1200 #ifndef CONFIG_SPL_BUILD 1201 pmuclk_init(priv->pmucru); 1202 #endif 1203 return 0; 1204 } 1205 1206 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1207 { 1208 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1209 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1210 1211 priv->pmucru = dev_read_addr_ptr(dev); 1212 #endif 1213 return 0; 1214 } 1215 1216 static const struct udevice_id rk3399_pmuclk_ids[] = { 1217 { .compatible = "rockchip,rk3399-pmucru" }, 1218 { } 1219 }; 1220 1221 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1222 .name = "rockchip_rk3399_pmucru", 1223 .id = UCLASS_CLK, 1224 .of_match = rk3399_pmuclk_ids, 1225 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1226 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1227 .ops = &rk3399_pmuclk_ops, 1228 .probe = rk3399_pmuclk_probe, 1229 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1230 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1231 #endif 1232 }; 1233