1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2015 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <bitfield.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <dt-structs.h> 11 #include <errno.h> 12 #include <mapmem.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cru_rk3288.h> 17 #include <asm/arch/grf_rk3288.h> 18 #include <asm/arch/hardware.h> 19 #include <dt-bindings/clock/rk3288-cru.h> 20 #include <dm/device-internal.h> 21 #include <dm/lists.h> 22 #include <dm/uclass-internal.h> 23 #include <linux/log2.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 struct rk3288_clk_plat { 28 #if CONFIG_IS_ENABLED(OF_PLATDATA) 29 struct dtd_rockchip_rk3288_cru dtd; 30 #endif 31 }; 32 33 struct pll_div { 34 u32 nr; 35 u32 nf; 36 u32 no; 37 }; 38 39 enum { 40 VCO_MAX_HZ = 2200U * 1000000, 41 VCO_MIN_HZ = 440 * 1000000, 42 OUTPUT_MAX_HZ = 2200U * 1000000, 43 OUTPUT_MIN_HZ = 27500000, 44 FREF_MAX_HZ = 2200U * 1000000, 45 FREF_MIN_HZ = 269 * 1000, 46 }; 47 48 enum { 49 /* PLL CON0 */ 50 PLL_OD_MASK = 0x0f, 51 52 /* PLL CON1 */ 53 PLL_NF_MASK = 0x1fff, 54 55 /* PLL CON2 */ 56 PLL_BWADJ_MASK = 0x0fff, 57 58 /* PLL CON3 */ 59 PLL_RESET_SHIFT = 5, 60 61 /* CLKSEL0 */ 62 CORE_SEL_PLL_SHIFT = 15, 63 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT, 64 A17_DIV_SHIFT = 8, 65 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT, 66 MP_DIV_SHIFT = 4, 67 MP_DIV_MASK = 0xf << MP_DIV_SHIFT, 68 M0_DIV_SHIFT = 0, 69 M0_DIV_MASK = 0xf << M0_DIV_SHIFT, 70 71 /* CLKSEL1: pd bus clk pll sel: codec or general */ 72 PD_BUS_SEL_PLL_MASK = 15, 73 PD_BUS_SEL_CPLL = 0, 74 PD_BUS_SEL_GPLL, 75 76 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */ 77 PD_BUS_PCLK_DIV_SHIFT = 12, 78 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT, 79 80 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 81 PD_BUS_HCLK_DIV_SHIFT = 8, 82 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT, 83 84 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */ 85 PD_BUS_ACLK_DIV0_SHIFT = 3, 86 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT, 87 PD_BUS_ACLK_DIV1_SHIFT = 0, 88 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT, 89 90 /* 91 * CLKSEL10 92 * peripheral bus pclk div: 93 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1 94 */ 95 PERI_SEL_PLL_SHIFT = 15, 96 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, 97 PERI_SEL_CPLL = 0, 98 PERI_SEL_GPLL, 99 100 PERI_PCLK_DIV_SHIFT = 12, 101 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, 102 103 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */ 104 PERI_HCLK_DIV_SHIFT = 8, 105 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, 106 107 /* 108 * peripheral bus aclk div: 109 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1) 110 */ 111 PERI_ACLK_DIV_SHIFT = 0, 112 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, 113 114 /* 115 * CLKSEL24 116 * saradc_div_con: 117 * clk_saradc=24MHz/(saradc_div_con+1) 118 */ 119 CLK_SARADC_DIV_CON_SHIFT = 8, 120 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 121 CLK_SARADC_DIV_CON_WIDTH = 8, 122 123 SOCSTS_DPLL_LOCK = 1 << 5, 124 SOCSTS_APLL_LOCK = 1 << 6, 125 SOCSTS_CPLL_LOCK = 1 << 7, 126 SOCSTS_GPLL_LOCK = 1 << 8, 127 SOCSTS_NPLL_LOCK = 1 << 9, 128 }; 129 130 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 131 132 #define PLL_DIVISORS(hz, _nr, _no) {\ 133 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ 134 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ 135 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ 136 "divisors on line " __stringify(__LINE__)); 137 138 /* Keep divisors as low as possible to reduce jitter and power usage */ 139 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); 140 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); 141 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); 142 143 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, 144 const struct pll_div *div) 145 { 146 int pll_id = rk_pll_id(clk_id); 147 struct rk3288_pll *pll = &cru->pll[pll_id]; 148 /* All PLLs have same VCO and output frequency range restrictions. */ 149 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; 150 uint output_hz = vco_hz / div->no; 151 152 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", 153 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); 154 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 155 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && 156 (div->no == 1 || !(div->no % 2))); 157 158 /* enter reset */ 159 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); 160 161 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, 162 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); 163 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); 164 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); 165 166 udelay(10); 167 168 /* return from reset */ 169 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); 170 171 return 0; 172 } 173 174 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, 175 unsigned int hz) 176 { 177 static const struct pll_div dpll_cfg[] = { 178 {.nf = 25, .nr = 2, .no = 1}, 179 {.nf = 400, .nr = 9, .no = 2}, 180 {.nf = 500, .nr = 9, .no = 2}, 181 {.nf = 100, .nr = 3, .no = 1}, 182 }; 183 int cfg; 184 185 switch (hz) { 186 case 300000000: 187 cfg = 0; 188 break; 189 case 533000000: /* actually 533.3P MHz */ 190 cfg = 1; 191 break; 192 case 666000000: /* actually 666.6P MHz */ 193 cfg = 2; 194 break; 195 case 800000000: 196 cfg = 3; 197 break; 198 default: 199 debug("Unsupported SDRAM frequency"); 200 return -EINVAL; 201 } 202 203 /* pll enter slow-mode */ 204 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 205 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 206 207 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); 208 209 /* wait for pll lock */ 210 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK)) 211 udelay(1); 212 213 /* PLL enter normal-mode */ 214 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, 215 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); 216 217 return 0; 218 } 219 220 #ifndef CONFIG_SPL_BUILD 221 #define VCO_MAX_KHZ 2200000 222 #define VCO_MIN_KHZ 440000 223 #define FREF_MAX_KHZ 2200000 224 #define FREF_MIN_KHZ 269 225 226 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) 227 { 228 uint ref_khz = OSC_HZ / 1000, nr, nf = 0; 229 uint fref_khz; 230 uint diff_khz, best_diff_khz; 231 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4; 232 uint vco_khz; 233 uint no = 1; 234 uint freq_khz = freq_hz / 1000; 235 236 if (!freq_hz) { 237 printf("%s: the frequency can not be 0 Hz\n", __func__); 238 return -EINVAL; 239 } 240 241 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 242 if (ext_div) { 243 *ext_div = DIV_ROUND_UP(no, max_no); 244 no = DIV_ROUND_UP(no, *ext_div); 245 } 246 247 /* only even divisors (and 1) are supported */ 248 if (no > 1) 249 no = DIV_ROUND_UP(no, 2) * 2; 250 251 vco_khz = freq_khz * no; 252 if (ext_div) 253 vco_khz *= *ext_div; 254 255 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) { 256 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n", 257 __func__, freq_hz); 258 return -1; 259 } 260 261 div->no = no; 262 263 best_diff_khz = vco_khz; 264 for (nr = 1; nr < max_nr && best_diff_khz; nr++) { 265 fref_khz = ref_khz / nr; 266 if (fref_khz < FREF_MIN_KHZ) 267 break; 268 if (fref_khz > FREF_MAX_KHZ) 269 continue; 270 271 nf = vco_khz / fref_khz; 272 if (nf >= max_nf) 273 continue; 274 diff_khz = vco_khz - nf * fref_khz; 275 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) { 276 nf++; 277 diff_khz = fref_khz - diff_khz; 278 } 279 280 if (diff_khz >= best_diff_khz) 281 continue; 282 283 best_diff_khz = diff_khz; 284 div->nr = nr; 285 div->nf = nf; 286 } 287 288 if (best_diff_khz > 4 * 1000) { 289 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n", 290 __func__, freq_hz, best_diff_khz * 1000); 291 return -EINVAL; 292 } 293 294 return 0; 295 } 296 297 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) 298 { 299 ulong ret; 300 301 /* 302 * The gmac clock can be derived either from an external clock 303 * or can be generated from internally by a divider from SCLK_MAC. 304 */ 305 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { 306 /* An external clock will always generate the right rate... */ 307 ret = freq; 308 } else { 309 u32 con = readl(&cru->cru_clksel_con[21]); 310 ulong pll_rate; 311 u8 div; 312 313 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 314 EMAC_PLL_SELECT_GENERAL) 315 pll_rate = GPLL_HZ; 316 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 317 EMAC_PLL_SELECT_CODEC) 318 pll_rate = CPLL_HZ; 319 else 320 pll_rate = NPLL_HZ; 321 322 div = DIV_ROUND_UP(pll_rate, freq) - 1; 323 if (div <= 0x1f) 324 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, 325 div << MAC_DIV_CON_SHIFT); 326 else 327 debug("Unsupported div for gmac:%d\n", div); 328 329 return DIV_TO_RATE(pll_rate, div); 330 } 331 332 return ret; 333 } 334 335 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, 336 int periph, unsigned int rate_hz) 337 { 338 struct pll_div npll_config = {0}; 339 u32 lcdc_div; 340 int ret; 341 342 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div); 343 if (ret) 344 return ret; 345 346 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, 347 NPLL_MODE_SLOW << NPLL_MODE_SHIFT); 348 rkclk_set_pll(cru, CLK_NEW, &npll_config); 349 350 /* waiting for pll lock */ 351 while (1) { 352 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK) 353 break; 354 udelay(1); 355 } 356 357 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, 358 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT); 359 360 /* vop dclk source clk: npll,dclk_div: 1 */ 361 switch (periph) { 362 case DCLK_VOP0: 363 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, 364 (lcdc_div - 1) << 8 | 2 << 0); 365 break; 366 case DCLK_VOP1: 367 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, 368 (lcdc_div - 1) << 8 | 2 << 6); 369 break; 370 } 371 372 return 0; 373 } 374 #endif /* CONFIG_SPL_BUILD */ 375 376 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) 377 { 378 u32 aclk_div; 379 u32 hclk_div; 380 u32 pclk_div; 381 382 /* pll enter slow-mode */ 383 rk_clrsetreg(&cru->cru_mode_con, 384 GPLL_MODE_MASK | CPLL_MODE_MASK, 385 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 386 CPLL_MODE_SLOW << CPLL_MODE_SHIFT); 387 388 /* init pll */ 389 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 390 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); 391 392 /* waiting for pll lock */ 393 while ((readl(&grf->soc_status[1]) & 394 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != 395 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) 396 udelay(1); 397 398 /* 399 * pd_bus clock pll source selection and 400 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 401 */ 402 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; 403 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 404 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; 405 assert((hclk_div + 1) * PD_BUS_HCLK_HZ == 406 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); 407 408 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; 409 assert((pclk_div + 1) * PD_BUS_PCLK_HZ == 410 PD_BUS_ACLK_HZ && pclk_div < 0x7); 411 412 rk_clrsetreg(&cru->cru_clksel_con[1], 413 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK | 414 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK, 415 pclk_div << PD_BUS_PCLK_DIV_SHIFT | 416 hclk_div << PD_BUS_HCLK_DIV_SHIFT | 417 aclk_div << PD_BUS_ACLK_DIV0_SHIFT | 418 0 << 0); 419 420 /* 421 * peri clock pll source selection and 422 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 423 */ 424 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 425 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 426 427 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 428 assert((1 << hclk_div) * PERI_HCLK_HZ == 429 PERI_ACLK_HZ && (hclk_div < 0x4)); 430 431 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 432 assert((1 << pclk_div) * PERI_PCLK_HZ == 433 PERI_ACLK_HZ && (pclk_div < 0x4)); 434 435 rk_clrsetreg(&cru->cru_clksel_con[10], 436 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK | 437 PERI_ACLK_DIV_MASK, 438 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | 439 pclk_div << PERI_PCLK_DIV_SHIFT | 440 hclk_div << PERI_HCLK_DIV_SHIFT | 441 aclk_div << PERI_ACLK_DIV_SHIFT); 442 443 /* PLL enter normal-mode */ 444 rk_clrsetreg(&cru->cru_mode_con, 445 GPLL_MODE_MASK | CPLL_MODE_MASK, 446 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | 447 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); 448 } 449 450 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) 451 { 452 /* pll enter slow-mode */ 453 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 454 APLL_MODE_SLOW << APLL_MODE_SHIFT); 455 456 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 457 458 /* waiting for pll lock */ 459 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK)) 460 udelay(1); 461 462 /* 463 * core clock pll source selection and 464 * set up dependent divisors for MPAXI/M0AXI and ARM clocks. 465 * core clock select apll, apll clk = 1800MHz 466 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz 467 */ 468 rk_clrsetreg(&cru->cru_clksel_con[0], 469 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK | 470 M0_DIV_MASK, 471 0 << A17_DIV_SHIFT | 472 3 << MP_DIV_SHIFT | 473 1 << M0_DIV_SHIFT); 474 475 /* 476 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks. 477 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz 478 */ 479 rk_clrsetreg(&cru->cru_clksel_con[37], 480 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK | 481 PCLK_CORE_DBG_DIV_MASK, 482 1 << CLK_L2RAM_DIV_SHIFT | 483 3 << ATCLK_CORE_DIV_CON_SHIFT | 484 3 << PCLK_CORE_DBG_DIV_SHIFT); 485 486 /* PLL enter normal-mode */ 487 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, 488 APLL_MODE_NORMAL << APLL_MODE_SHIFT); 489 } 490 491 /* Get pll rate by id */ 492 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru, 493 enum rk_clk_id clk_id) 494 { 495 uint32_t nr, no, nf; 496 uint32_t con; 497 int pll_id = rk_pll_id(clk_id); 498 struct rk3288_pll *pll = &cru->pll[pll_id]; 499 static u8 clk_shift[CLK_COUNT] = { 500 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 501 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT 502 }; 503 uint shift; 504 505 con = readl(&cru->cru_mode_con); 506 shift = clk_shift[clk_id]; 507 switch ((con >> shift) & CRU_MODE_MASK) { 508 case APLL_MODE_SLOW: 509 return OSC_HZ; 510 case APLL_MODE_NORMAL: 511 /* normal mode */ 512 con = readl(&pll->con0); 513 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; 514 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; 515 con = readl(&pll->con1); 516 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; 517 518 return (24 * nf / (nr * no)) * 1000000; 519 case APLL_MODE_DEEP: 520 default: 521 return 32768; 522 } 523 } 524 525 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate, 526 int periph) 527 { 528 uint src_rate; 529 uint div, mux; 530 u32 con; 531 532 switch (periph) { 533 case HCLK_EMMC: 534 case SCLK_EMMC: 535 con = readl(&cru->cru_clksel_con[12]); 536 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 537 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 538 break; 539 case HCLK_SDMMC: 540 case SCLK_SDMMC: 541 con = readl(&cru->cru_clksel_con[11]); 542 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 543 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 544 break; 545 case HCLK_SDIO0: 546 case SCLK_SDIO0: 547 con = readl(&cru->cru_clksel_con[12]); 548 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; 549 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; 550 break; 551 default: 552 return -EINVAL; 553 } 554 555 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate; 556 return DIV_TO_RATE(src_rate, div); 557 } 558 559 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, 560 int periph, uint freq) 561 { 562 int src_clk_div; 563 int mux; 564 565 debug("%s: gclk_rate=%u\n", __func__, gclk_rate); 566 /* mmc clock default div 2 internal, need provide double in cru */ 567 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); 568 569 if (src_clk_div > 0x3f) { 570 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 571 assert(src_clk_div < 0x40); 572 mux = EMMC_PLL_SELECT_24MHZ; 573 assert((int)EMMC_PLL_SELECT_24MHZ == 574 (int)MMC0_PLL_SELECT_24MHZ); 575 } else { 576 mux = EMMC_PLL_SELECT_GENERAL; 577 assert((int)EMMC_PLL_SELECT_GENERAL == 578 (int)MMC0_PLL_SELECT_GENERAL); 579 } 580 switch (periph) { 581 case HCLK_EMMC: 582 case SCLK_EMMC: 583 rk_clrsetreg(&cru->cru_clksel_con[12], 584 EMMC_PLL_MASK | EMMC_DIV_MASK, 585 mux << EMMC_PLL_SHIFT | 586 (src_clk_div - 1) << EMMC_DIV_SHIFT); 587 break; 588 case HCLK_SDMMC: 589 case SCLK_SDMMC: 590 rk_clrsetreg(&cru->cru_clksel_con[11], 591 MMC0_PLL_MASK | MMC0_DIV_MASK, 592 mux << MMC0_PLL_SHIFT | 593 (src_clk_div - 1) << MMC0_DIV_SHIFT); 594 break; 595 case HCLK_SDIO0: 596 case SCLK_SDIO0: 597 rk_clrsetreg(&cru->cru_clksel_con[12], 598 SDIO0_PLL_MASK | SDIO0_DIV_MASK, 599 mux << SDIO0_PLL_SHIFT | 600 (src_clk_div - 1) << SDIO0_DIV_SHIFT); 601 break; 602 default: 603 return -EINVAL; 604 } 605 606 return rockchip_mmc_get_clk(cru, gclk_rate, periph); 607 } 608 609 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate, 610 int periph) 611 { 612 uint div, mux; 613 u32 con; 614 615 switch (periph) { 616 case SCLK_SPI0: 617 con = readl(&cru->cru_clksel_con[25]); 618 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; 619 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; 620 break; 621 case SCLK_SPI1: 622 con = readl(&cru->cru_clksel_con[25]); 623 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; 624 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; 625 break; 626 case SCLK_SPI2: 627 con = readl(&cru->cru_clksel_con[39]); 628 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; 629 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; 630 break; 631 default: 632 return -EINVAL; 633 } 634 assert(mux == SPI0_PLL_SELECT_GENERAL); 635 636 return DIV_TO_RATE(gclk_rate, div); 637 } 638 639 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, 640 int periph, uint freq) 641 { 642 int src_clk_div; 643 644 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); 645 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; 646 assert(src_clk_div < 128); 647 switch (periph) { 648 case SCLK_SPI0: 649 rk_clrsetreg(&cru->cru_clksel_con[25], 650 SPI0_PLL_MASK | SPI0_DIV_MASK, 651 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT | 652 src_clk_div << SPI0_DIV_SHIFT); 653 break; 654 case SCLK_SPI1: 655 rk_clrsetreg(&cru->cru_clksel_con[25], 656 SPI1_PLL_MASK | SPI1_DIV_MASK, 657 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT | 658 src_clk_div << SPI1_DIV_SHIFT); 659 break; 660 case SCLK_SPI2: 661 rk_clrsetreg(&cru->cru_clksel_con[39], 662 SPI2_PLL_MASK | SPI2_DIV_MASK, 663 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT | 664 src_clk_div << SPI2_DIV_SHIFT); 665 break; 666 default: 667 return -EINVAL; 668 } 669 670 return rockchip_spi_get_clk(cru, gclk_rate, periph); 671 } 672 673 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru) 674 { 675 u32 div, val; 676 677 val = readl(&cru->cru_clksel_con[24]); 678 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 679 CLK_SARADC_DIV_CON_WIDTH); 680 681 return DIV_TO_RATE(OSC_HZ, div); 682 } 683 684 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) 685 { 686 int src_clk_div; 687 688 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 689 assert(src_clk_div < 128); 690 691 rk_clrsetreg(&cru->cru_clksel_con[24], 692 CLK_SARADC_DIV_CON_MASK, 693 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 694 695 return rockchip_saradc_get_clk(cru); 696 } 697 698 static ulong rk3288_clk_get_rate(struct clk *clk) 699 { 700 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 701 ulong new_rate, gclk_rate; 702 703 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 704 switch (clk->id) { 705 case 0 ... 63: 706 new_rate = rkclk_pll_get_rate(priv->cru, clk->id); 707 break; 708 case HCLK_EMMC: 709 case HCLK_SDMMC: 710 case HCLK_SDIO0: 711 case SCLK_EMMC: 712 case SCLK_SDMMC: 713 case SCLK_SDIO0: 714 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); 715 break; 716 case SCLK_SPI0: 717 case SCLK_SPI1: 718 case SCLK_SPI2: 719 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id); 720 break; 721 case PCLK_I2C0: 722 case PCLK_I2C1: 723 case PCLK_I2C2: 724 case PCLK_I2C3: 725 case PCLK_I2C4: 726 case PCLK_I2C5: 727 return gclk_rate; 728 case PCLK_PWM: 729 return PD_BUS_PCLK_HZ; 730 case SCLK_SARADC: 731 new_rate = rockchip_saradc_get_clk(priv->cru); 732 break; 733 default: 734 return -ENOENT; 735 } 736 737 return new_rate; 738 } 739 740 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) 741 { 742 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 743 struct rk3288_cru *cru = priv->cru; 744 ulong new_rate, gclk_rate; 745 746 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 747 switch (clk->id) { 748 case PLL_APLL: 749 /* We only support a fixed rate here */ 750 if (rate != 1800000000) 751 return -EINVAL; 752 rk3288_clk_configure_cpu(priv->cru, priv->grf); 753 new_rate = rate; 754 break; 755 case CLK_DDR: 756 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate); 757 break; 758 case HCLK_EMMC: 759 case HCLK_SDMMC: 760 case HCLK_SDIO0: 761 case SCLK_EMMC: 762 case SCLK_SDMMC: 763 case SCLK_SDIO0: 764 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate); 765 break; 766 case SCLK_SPI0: 767 case SCLK_SPI1: 768 case SCLK_SPI2: 769 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); 770 break; 771 #ifndef CONFIG_SPL_BUILD 772 case SCLK_MAC: 773 new_rate = rockchip_mac_set_clk(priv->cru, rate); 774 break; 775 case DCLK_VOP0: 776 case DCLK_VOP1: 777 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate); 778 break; 779 case SCLK_EDP_24M: 780 /* clk_edp_24M source: 24M */ 781 rk_setreg(&cru->cru_clksel_con[28], 1 << 15); 782 783 /* rst edp */ 784 rk_setreg(&cru->cru_clksel_con[6], 1 << 15); 785 udelay(1); 786 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); 787 new_rate = rate; 788 break; 789 case ACLK_VOP0: 790 case ACLK_VOP1: { 791 u32 div; 792 793 /* vop aclk source clk: cpll */ 794 div = CPLL_HZ / rate; 795 assert((div - 1 < 64) && (div * rate == CPLL_HZ)); 796 797 switch (clk->id) { 798 case ACLK_VOP0: 799 rk_clrsetreg(&cru->cru_clksel_con[31], 800 3 << 6 | 0x1f << 0, 801 0 << 6 | (div - 1) << 0); 802 break; 803 case ACLK_VOP1: 804 rk_clrsetreg(&cru->cru_clksel_con[31], 805 3 << 14 | 0x1f << 8, 806 0 << 14 | (div - 1) << 8); 807 break; 808 } 809 new_rate = rate; 810 break; 811 } 812 case PCLK_HDMI_CTRL: 813 /* enable pclk hdmi ctrl */ 814 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); 815 816 /* software reset hdmi */ 817 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9); 818 udelay(1); 819 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); 820 new_rate = rate; 821 break; 822 #endif 823 case SCLK_SARADC: 824 new_rate = rockchip_saradc_set_clk(priv->cru, rate); 825 break; 826 case PLL_GPLL: 827 case PLL_CPLL: 828 case PLL_NPLL: 829 case ACLK_CPU: 830 case HCLK_CPU: 831 case PCLK_CPU: 832 case ACLK_PERI: 833 case HCLK_PERI: 834 case PCLK_PERI: 835 case SCLK_UART0: 836 return 0; 837 default: 838 return -ENOENT; 839 } 840 841 return new_rate; 842 } 843 844 static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent) 845 { 846 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev); 847 struct rk3288_cru *cru = priv->cru; 848 const char *clock_output_name; 849 int ret; 850 851 /* 852 * If the requested parent is in the same clock-controller and 853 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal 854 * clock. 855 */ 856 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { 857 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); 858 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); 859 return 0; 860 } 861 862 /* 863 * Otherwise, we need to check the clock-output-names of the 864 * requested parent to see if the requested id is "ext_gmac". 865 */ 866 ret = dev_read_string_index(parent->dev, "clock-output-names", 867 parent->id, &clock_output_name); 868 if (ret < 0) 869 return -ENODATA; 870 871 /* If this is "ext_gmac", switch to the external clock input */ 872 if (!strcmp(clock_output_name, "ext_gmac")) { 873 debug("%s: switching GMAC to external clock\n", __func__); 874 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 875 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); 876 return 0; 877 } 878 879 return -EINVAL; 880 } 881 882 static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent) 883 { 884 switch (clk->id) { 885 case SCLK_MAC: 886 return rk3288_gmac_set_parent(clk, parent); 887 case SCLK_USBPHY480M_SRC: 888 return 0; 889 } 890 891 debug("%s: unsupported clk %ld\n", __func__, clk->id); 892 return -ENOENT; 893 } 894 895 static int rk3288_clk_enable(struct clk *clk) 896 { 897 switch (clk->id) { 898 case HCLK_USBHOST0: 899 case HCLK_HSIC: 900 return 0; 901 902 case SCLK_MAC: 903 case SCLK_MAC_RX: 904 case SCLK_MAC_TX: 905 case SCLK_MACREF: 906 case SCLK_MACREF_OUT: 907 case ACLK_GMAC: 908 case PCLK_GMAC: 909 /* Required to successfully probe the Designware GMAC driver */ 910 return 0; 911 } 912 913 debug("%s: unsupported clk %ld\n", __func__, clk->id); 914 return -ENOENT; 915 } 916 917 static struct clk_ops rk3288_clk_ops = { 918 .get_rate = rk3288_clk_get_rate, 919 .set_rate = rk3288_clk_set_rate, 920 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 921 .set_parent = rk3288_clk_set_parent, 922 #endif 923 .enable = rk3288_clk_enable, 924 }; 925 926 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) 927 { 928 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 929 struct rk3288_clk_priv *priv = dev_get_priv(dev); 930 931 priv->cru = dev_read_addr_ptr(dev); 932 #endif 933 934 return 0; 935 } 936 937 static int rk3288_clk_probe(struct udevice *dev) 938 { 939 struct rk3288_clk_priv *priv = dev_get_priv(dev); 940 bool init_clocks = false; 941 942 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 943 if (IS_ERR(priv->grf)) 944 return PTR_ERR(priv->grf); 945 #ifdef CONFIG_SPL_BUILD 946 #if CONFIG_IS_ENABLED(OF_PLATDATA) 947 struct rk3288_clk_plat *plat = dev_get_platdata(dev); 948 949 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 950 #endif 951 init_clocks = true; 952 #endif 953 if (!(gd->flags & GD_FLG_RELOC)) { 954 u32 reg; 955 956 /* 957 * Init clocks in U-Boot proper if the NPLL is runnning. This 958 * indicates that a previous boot loader set up the clocks, so 959 * we need to redo it. U-Boot's SPL does not set this clock. 960 */ 961 reg = readl(&priv->cru->cru_mode_con); 962 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) == 963 NPLL_MODE_NORMAL) 964 init_clocks = true; 965 } 966 967 if (init_clocks) 968 rkclk_init(priv->cru, priv->grf); 969 970 return 0; 971 } 972 973 static int rk3288_clk_bind(struct udevice *dev) 974 { 975 int ret; 976 struct udevice *sys_child; 977 struct sysreset_reg *priv; 978 979 /* The reset driver does not have a device node, so bind it here */ 980 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 981 &sys_child); 982 if (ret) { 983 debug("Warning: No sysreset driver: ret=%d\n", ret); 984 } else { 985 priv = malloc(sizeof(struct sysreset_reg)); 986 priv->glb_srst_fst_value = offsetof(struct rk3288_cru, 987 cru_glb_srst_fst_value); 988 priv->glb_srst_snd_value = offsetof(struct rk3288_cru, 989 cru_glb_srst_snd_value); 990 sys_child->priv = priv; 991 } 992 993 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) 994 ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); 995 ret = rockchip_reset_bind(dev, ret, 12); 996 if (ret) 997 debug("Warning: software reset driver bind faile\n"); 998 #endif 999 1000 return 0; 1001 } 1002 1003 static const struct udevice_id rk3288_clk_ids[] = { 1004 { .compatible = "rockchip,rk3288-cru" }, 1005 { } 1006 }; 1007 1008 U_BOOT_DRIVER(rockchip_rk3288_cru) = { 1009 .name = "rockchip_rk3288_cru", 1010 .id = UCLASS_CLK, 1011 .of_match = rk3288_clk_ids, 1012 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), 1013 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), 1014 .ops = &rk3288_clk_ops, 1015 .bind = rk3288_clk_bind, 1016 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, 1017 .probe = rk3288_clk_probe, 1018 }; 1019