1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <syscon.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk322x.h>
15 #include <asm/arch/hardware.h>
16 #include <dm/lists.h>
17 #include <dt-bindings/clock/rk3228-cru.h>
18 #include <linux/log2.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 enum {
23 	VCO_MAX_HZ	= 3200U * 1000000,
24 	VCO_MIN_HZ	= 800 * 1000000,
25 	OUTPUT_MAX_HZ	= 3200U * 1000000,
26 	OUTPUT_MIN_HZ	= 24 * 1000000,
27 };
28 
29 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
30 
31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
32 	.refdiv = _refdiv,\
33 	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
34 	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
35 	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
36 			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
37 			 #hz "Hz cannot be hit with PLL "\
38 			 "divisors on line " __stringify(__LINE__));
39 
40 /* use integer mode*/
41 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
43 
44 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
45 			 const struct pll_div *div)
46 {
47 	int pll_id = rk_pll_id(clk_id);
48 	struct rk322x_pll *pll = &cru->pll[pll_id];
49 
50 	/* All PLLs have same VCO and output frequency range restrictions. */
51 	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
52 	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
53 
54 	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
55 	      pll, div->fbdiv, div->refdiv, div->postdiv1,
56 	      div->postdiv2, vco_hz, output_hz);
57 	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
58 	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
59 
60 	/* use integer mode */
61 	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
62 	/* Power down */
63 	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
64 
65 	rk_clrsetreg(&pll->con0,
66 		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
67 		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
68 	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
69 		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
70 		     div->refdiv << PLL_REFDIV_SHIFT));
71 
72 	/* Power Up */
73 	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
74 
75 	/* waiting for pll lock */
76 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
77 		udelay(1);
78 
79 	return 0;
80 }
81 
82 static void rkclk_init(struct rk322x_cru *cru)
83 {
84 	u32 aclk_div;
85 	u32 hclk_div;
86 	u32 pclk_div;
87 
88 	/* pll enter slow-mode */
89 	rk_clrsetreg(&cru->cru_mode_con,
90 		     GPLL_MODE_MASK | APLL_MODE_MASK,
91 		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
92 		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
93 
94 	/* init pll */
95 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
96 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
97 
98 	/*
99 	 * select apll as cpu/core clock pll source and
100 	 * set up dependent divisors for PERI and ACLK clocks.
101 	 * core hz : apll = 1:1
102 	 */
103 	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
104 	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
105 
106 	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
107 	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
108 
109 	rk_clrsetreg(&cru->cru_clksel_con[0],
110 		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
111 		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
112 		     0 << CORE_DIV_CON_SHIFT);
113 
114 	rk_clrsetreg(&cru->cru_clksel_con[1],
115 		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
116 		     aclk_div << CORE_ACLK_DIV_SHIFT |
117 		     pclk_div << CORE_PERI_DIV_SHIFT);
118 
119 	/*
120 	 * select gpll as pd_bus bus clock source and
121 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
122 	 */
123 	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
124 	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
125 
126 	pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
127 	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
128 
129 	hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
130 	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
131 
132 	rk_clrsetreg(&cru->cru_clksel_con[0],
133 		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
134 		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
135 		     aclk_div << BUS_ACLK_DIV_SHIFT);
136 
137 	rk_clrsetreg(&cru->cru_clksel_con[1],
138 		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
139 		     pclk_div << BUS_PCLK_DIV_SHIFT |
140 		     hclk_div << BUS_HCLK_DIV_SHIFT);
141 
142 	/*
143 	 * select gpll as pd_peri bus clock source and
144 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
145 	 */
146 	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
147 	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
148 
149 	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
150 	assert((1 << hclk_div) * PERI_HCLK_HZ ==
151 		PERI_ACLK_HZ && (hclk_div < 0x4));
152 
153 	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
154 	assert((1 << pclk_div) * PERI_PCLK_HZ ==
155 		PERI_ACLK_HZ && pclk_div < 0x8);
156 
157 	rk_clrsetreg(&cru->cru_clksel_con[10],
158 		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
159 		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
160 		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
161 		     pclk_div << PERI_PCLK_DIV_SHIFT |
162 		     hclk_div << PERI_HCLK_DIV_SHIFT |
163 		     aclk_div << PERI_ACLK_DIV_SHIFT);
164 
165 	/* PLL enter normal-mode */
166 	rk_clrsetreg(&cru->cru_mode_con,
167 		     GPLL_MODE_MASK | APLL_MODE_MASK,
168 		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
169 		     APLL_MODE_NORM << APLL_MODE_SHIFT);
170 }
171 
172 /* Get pll rate by id */
173 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
174 				   enum rk_clk_id clk_id)
175 {
176 	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
177 	uint32_t con;
178 	int pll_id = rk_pll_id(clk_id);
179 	struct rk322x_pll *pll = &cru->pll[pll_id];
180 	static u8 clk_shift[CLK_COUNT] = {
181 		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
182 		GPLL_MODE_SHIFT, 0xff
183 	};
184 	static u32 clk_mask[CLK_COUNT] = {
185 		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
186 		GPLL_MODE_MASK, 0xff
187 	};
188 	uint shift;
189 	uint mask;
190 
191 	con = readl(&cru->cru_mode_con);
192 	shift = clk_shift[clk_id];
193 	mask = clk_mask[clk_id];
194 
195 	switch ((con & mask) >> shift) {
196 	case GPLL_MODE_SLOW:
197 		return OSC_HZ;
198 	case GPLL_MODE_NORM:
199 
200 		/* normal mode */
201 		con = readl(&pll->con0);
202 		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
203 		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
204 		con = readl(&pll->con1);
205 		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
206 		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
207 		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
208 	default:
209 		return 32768;
210 	}
211 }
212 
213 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
214 				  int periph)
215 {
216 	uint src_rate;
217 	uint div, mux;
218 	u32 con;
219 
220 	switch (periph) {
221 	case HCLK_EMMC:
222 	case SCLK_EMMC:
223 		con = readl(&cru->cru_clksel_con[11]);
224 		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
225 		con = readl(&cru->cru_clksel_con[12]);
226 		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
227 		break;
228 	case HCLK_SDMMC:
229 	case SCLK_SDMMC:
230 		con = readl(&cru->cru_clksel_con[11]);
231 		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
232 		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
233 		break;
234 	default:
235 		return -EINVAL;
236 	}
237 
238 	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
239 	return DIV_TO_RATE(src_rate, div) / 2;
240 }
241 
242 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
243 				  int periph, uint freq)
244 {
245 	int src_clk_div;
246 	int mux;
247 
248 	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
249 
250 	/* mmc clock defaulg div 2 internal, need provide double in cru */
251 	src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
252 
253 	if (src_clk_div > 128) {
254 		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
255 		assert(src_clk_div - 1 < 128);
256 		mux = EMMC_SEL_24M;
257 	} else {
258 		mux = EMMC_SEL_GPLL;
259 	}
260 
261 	switch (periph) {
262 	case HCLK_EMMC:
263 	case SCLK_EMMC:
264 		rk_clrsetreg(&cru->cru_clksel_con[11],
265 			     EMMC_PLL_MASK,
266 			     mux << EMMC_PLL_SHIFT);
267 		rk_clrsetreg(&cru->cru_clksel_con[12],
268 			     EMMC_DIV_MASK,
269 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
270 		break;
271 	case HCLK_SDMMC:
272 	case SCLK_SDMMC:
273 		rk_clrsetreg(&cru->cru_clksel_con[11],
274 			     MMC0_PLL_MASK | MMC0_DIV_MASK,
275 			     mux << MMC0_PLL_SHIFT |
276 			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
277 		break;
278 	default:
279 		return -EINVAL;
280 	}
281 
282 	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
283 }
284 
285 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
286 {
287 	struct pll_div dpll_cfg;
288 
289 	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
290 	switch (set_rate) {
291 	case 400*MHz:
292 		dpll_cfg = (struct pll_div)
293 		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
294 		break;
295 	case 600*MHz:
296 		dpll_cfg = (struct pll_div)
297 		{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
298 		break;
299 	case 800*MHz:
300 		dpll_cfg = (struct pll_div)
301 		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
302 		break;
303 	}
304 
305 	/* pll enter slow-mode */
306 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
307 		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
308 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
309 	/* PLL enter normal-mode */
310 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
311 		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);
312 
313 	return set_rate;
314 }
315 static ulong rk322x_clk_get_rate(struct clk *clk)
316 {
317 	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
318 	ulong rate, gclk_rate;
319 
320 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
321 	switch (clk->id) {
322 	case 0 ... 63:
323 		rate = rkclk_pll_get_rate(priv->cru, clk->id);
324 		break;
325 	case HCLK_EMMC:
326 	case SCLK_EMMC:
327 	case HCLK_SDMMC:
328 	case SCLK_SDMMC:
329 		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
330 		break;
331 	default:
332 		return -ENOENT;
333 	}
334 
335 	return rate;
336 }
337 
338 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
339 {
340 	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
341 	ulong new_rate, gclk_rate;
342 
343 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
344 	switch (clk->id) {
345 	case HCLK_EMMC:
346 	case SCLK_EMMC:
347 	case HCLK_SDMMC:
348 	case SCLK_SDMMC:
349 		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
350 						clk->id, rate);
351 		break;
352 	case CLK_DDR:
353 		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
354 		break;
355 	default:
356 		return -ENOENT;
357 	}
358 
359 	return new_rate;
360 }
361 
362 static struct clk_ops rk322x_clk_ops = {
363 	.get_rate	= rk322x_clk_get_rate,
364 	.set_rate	= rk322x_clk_set_rate,
365 };
366 
367 static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
368 {
369 	struct rk322x_clk_priv *priv = dev_get_priv(dev);
370 
371 	priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
372 
373 	return 0;
374 }
375 
376 static int rk322x_clk_probe(struct udevice *dev)
377 {
378 	struct rk322x_clk_priv *priv = dev_get_priv(dev);
379 
380 	rkclk_init(priv->cru);
381 
382 	return 0;
383 }
384 
385 static int rk322x_clk_bind(struct udevice *dev)
386 {
387 	int ret;
388 	struct udevice *sys_child;
389 	struct sysreset_reg *priv;
390 
391 	/* The reset driver does not have a device node, so bind it here */
392 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
393 				 &sys_child);
394 	if (ret) {
395 		debug("Warning: No sysreset driver: ret=%d\n", ret);
396 	} else {
397 		priv = malloc(sizeof(struct sysreset_reg));
398 		priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
399 						    cru_glb_srst_fst_value);
400 		priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
401 						    cru_glb_srst_snd_value);
402 		sys_child->priv = priv;
403 	}
404 
405 #if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
406 	ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
407 	ret = rockchip_reset_bind(dev, ret, 9);
408 	if (ret)
409 		debug("Warning: software reset driver bind faile\n");
410 #endif
411 
412 	return 0;
413 }
414 
415 static const struct udevice_id rk322x_clk_ids[] = {
416 	{ .compatible = "rockchip,rk3228-cru" },
417 	{ }
418 };
419 
420 U_BOOT_DRIVER(rockchip_rk322x_cru) = {
421 	.name		= "clk_rk322x",
422 	.id		= UCLASS_CLK,
423 	.of_match	= rk322x_clk_ids,
424 	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
425 	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
426 	.ops		= &rk322x_clk_ops,
427 	.bind		= rk322x_clk_bind,
428 	.probe		= rk322x_clk_probe,
429 };
430