1 /*
2  * (C) Copyright 2015 Google, Inc
3  * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
4  *
5  * SPDX-License-Identifier:	GPL-2.0
6  */
7 
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <dt-structs.h>
12 #include <errno.h>
13 #include <mapmem.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3188.h>
18 #include <asm/arch/grf_rk3188.h>
19 #include <asm/arch/hardware.h>
20 #include <dt-bindings/clock/rk3188-cru.h>
21 #include <dm/device-internal.h>
22 #include <dm/lists.h>
23 #include <dm/uclass-internal.h>
24 #include <linux/log2.h>
25 
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 enum rk3188_clk_type {
29 	RK3188_CRU,
30 	RK3188A_CRU,
31 };
32 
33 struct rk3188_clk_plat {
34 #if CONFIG_IS_ENABLED(OF_PLATDATA)
35 	struct dtd_rockchip_rk3188_cru dtd;
36 #endif
37 };
38 
39 struct pll_div {
40 	u32 nr;
41 	u32 nf;
42 	u32 no;
43 };
44 
45 enum {
46 	VCO_MAX_HZ	= 2200U * 1000000,
47 	VCO_MIN_HZ	= 440 * 1000000,
48 	OUTPUT_MAX_HZ	= 2200U * 1000000,
49 	OUTPUT_MIN_HZ	= 30 * 1000000,
50 	FREF_MAX_HZ	= 2200U * 1000000,
51 	FREF_MIN_HZ	= 30 * 1000,
52 };
53 
54 enum {
55 	/* PLL CON0 */
56 	PLL_OD_MASK		= 0x0f,
57 
58 	/* PLL CON1 */
59 	PLL_NF_MASK		= 0x1fff,
60 
61 	/* PLL CON2 */
62 	PLL_BWADJ_MASK		= 0x0fff,
63 
64 	/* PLL CON3 */
65 	PLL_RESET_SHIFT		= 5,
66 
67 	/* GRF_SOC_STATUS0 */
68 	SOCSTS_DPLL_LOCK	= 1 << 5,
69 	SOCSTS_APLL_LOCK	= 1 << 6,
70 	SOCSTS_CPLL_LOCK	= 1 << 7,
71 	SOCSTS_GPLL_LOCK	= 1 << 8,
72 };
73 
74 #define RATE_TO_DIV(input_rate, output_rate) \
75 	((input_rate) / (output_rate) - 1);
76 
77 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
78 
79 #define PLL_DIVISORS(hz, _nr, _no) {\
80 	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
81 	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
82 		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
83 		       "divisors on line " __stringify(__LINE__));
84 
85 /* Keep divisors as low as possible to reduce jitter and power usage */
86 #ifdef CONFIG_SPL_BUILD
87 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
88 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
89 #endif
90 
91 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
92 			 const struct pll_div *div, bool has_bwadj)
93 {
94 	int pll_id = rk_pll_id(clk_id);
95 	struct rk3188_pll *pll = &cru->pll[pll_id];
96 	/* All PLLs have same VCO and output frequency range restrictions. */
97 	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
98 	uint output_hz = vco_hz / div->no;
99 
100 	debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
101 	      (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
102 	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
103 	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
104 	       (div->no == 1 || !(div->no % 2)));
105 
106 	/* enter reset */
107 	rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
108 
109 	rk_clrsetreg(&pll->con0,
110 		     CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
111 		     ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
112 	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
113 
114 	if (has_bwadj)
115 		rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
116 
117 	udelay(10);
118 
119 	/* return from reset */
120 	rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
121 
122 	return 0;
123 }
124 
125 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
126 			       unsigned int hz, bool has_bwadj)
127 {
128 	static const struct pll_div dpll_cfg[] = {
129 		{.nf = 25, .nr = 2, .no = 1},
130 		{.nf = 400, .nr = 9, .no = 2},
131 		{.nf = 500, .nr = 9, .no = 2},
132 		{.nf = 100, .nr = 3, .no = 1},
133 	};
134 	int cfg;
135 
136 	switch (hz) {
137 	case 300000000:
138 		cfg = 0;
139 		break;
140 	case 533000000:	/* actually 533.3P MHz */
141 		cfg = 1;
142 		break;
143 	case 666000000:	/* actually 666.6P MHz */
144 		cfg = 2;
145 		break;
146 	case 800000000:
147 		cfg = 3;
148 		break;
149 	default:
150 		debug("Unsupported SDRAM frequency");
151 		return -EINVAL;
152 	}
153 
154 	/* pll enter slow-mode */
155 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
156 		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
157 
158 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
159 
160 	/* wait for pll lock */
161 	while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
162 		udelay(1);
163 
164 	/* PLL enter normal-mode */
165 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
166 		     DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
167 
168 	return 0;
169 }
170 
171 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
172 			      unsigned int hz, bool has_bwadj)
173 {
174 	static const struct pll_div apll_cfg[] = {
175 		{.nf = 50, .nr = 1, .no = 2},
176 		{.nf = 67, .nr = 1, .no = 1},
177 	};
178 	int div_core_peri, div_aclk_core, cfg;
179 
180 	/*
181 	 * We support two possible frequencies, the safe 600MHz
182 	 * which will work with default pmic settings and will
183 	 * be set in SPL to get away from the 24MHz default and
184 	 * the maximum of 1.6Ghz, which boards can set if they
185 	 * were able to get pmic support for it.
186 	 */
187 	switch (hz) {
188 	case APLL_SAFE_HZ:
189 		cfg = 0;
190 		div_core_peri = 1;
191 		div_aclk_core = 3;
192 		break;
193 	case APLL_HZ:
194 		cfg = 1;
195 		div_core_peri = 2;
196 		div_aclk_core = 3;
197 		break;
198 	default:
199 		debug("Unsupported ARMCLK frequency");
200 		return -EINVAL;
201 	}
202 
203 	/* pll enter slow-mode */
204 	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
205 		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
206 
207 	rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
208 
209 	/* waiting for pll lock */
210 	while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
211 		udelay(1);
212 
213 	/* Set divider for peripherals attached to the cpu core. */
214 	rk_clrsetreg(&cru->cru_clksel_con[0],
215 		CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
216 		div_core_peri << CORE_PERI_DIV_SHIFT);
217 
218 	/* set up dependent divisor for aclk_core */
219 	rk_clrsetreg(&cru->cru_clksel_con[1],
220 		CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
221 		div_aclk_core << CORE_ACLK_DIV_SHIFT);
222 
223 	/* PLL enter normal-mode */
224 	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
225 		     APLL_MODE_NORMAL << APLL_MODE_SHIFT);
226 
227 	return hz;
228 }
229 
230 /* Get pll rate by id */
231 static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
232 				   enum rk_clk_id clk_id)
233 {
234 	uint32_t nr, no, nf;
235 	uint32_t con;
236 	int pll_id = rk_pll_id(clk_id);
237 	struct rk3188_pll *pll = &cru->pll[pll_id];
238 	static u8 clk_shift[CLK_COUNT] = {
239 		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
240 		GPLL_MODE_SHIFT
241 	};
242 	uint shift;
243 
244 	con = readl(&cru->cru_mode_con);
245 	shift = clk_shift[clk_id];
246 	switch ((con >> shift) & APLL_MODE_MASK) {
247 	case APLL_MODE_SLOW:
248 		return OSC_HZ;
249 	case APLL_MODE_NORMAL:
250 		/* normal mode */
251 		con = readl(&pll->con0);
252 		no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
253 		nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
254 		con = readl(&pll->con1);
255 		nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
256 
257 		return (24 * nf / (nr * no)) * 1000000;
258 	case APLL_MODE_DEEP:
259 	default:
260 		return 32768;
261 	}
262 }
263 
264 static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
265 				  int periph)
266 {
267 	uint div;
268 	u32 con;
269 
270 	switch (periph) {
271 	case HCLK_EMMC:
272 	case SCLK_EMMC:
273 		con = readl(&cru->cru_clksel_con[12]);
274 		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
275 		break;
276 	case HCLK_SDMMC:
277 	case SCLK_SDMMC:
278 		con = readl(&cru->cru_clksel_con[11]);
279 		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
280 		break;
281 	case HCLK_SDIO:
282 	case SCLK_SDIO:
283 		con = readl(&cru->cru_clksel_con[12]);
284 		div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
285 		break;
286 	default:
287 		return -EINVAL;
288 	}
289 
290 	return DIV_TO_RATE(gclk_rate, div);
291 }
292 
293 static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
294 				  int  periph, uint freq)
295 {
296 	int src_clk_div;
297 
298 	debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
299 	src_clk_div = RATE_TO_DIV(gclk_rate, freq);
300 	assert(src_clk_div <= 0x3f);
301 
302 	switch (periph) {
303 	case HCLK_EMMC:
304 	case SCLK_EMMC:
305 		rk_clrsetreg(&cru->cru_clksel_con[12],
306 			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
307 			     src_clk_div << EMMC_DIV_SHIFT);
308 		break;
309 	case HCLK_SDMMC:
310 	case SCLK_SDMMC:
311 		rk_clrsetreg(&cru->cru_clksel_con[11],
312 			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
313 			     src_clk_div << MMC0_DIV_SHIFT);
314 		break;
315 	case HCLK_SDIO:
316 	case SCLK_SDIO:
317 		rk_clrsetreg(&cru->cru_clksel_con[12],
318 			     SDIO_DIV_MASK << SDIO_DIV_SHIFT,
319 			     src_clk_div << SDIO_DIV_SHIFT);
320 		break;
321 	default:
322 		return -EINVAL;
323 	}
324 
325 	return rockchip_mmc_get_clk(cru, gclk_rate, periph);
326 }
327 
328 static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
329 				  int periph)
330 {
331 	uint div;
332 	u32 con;
333 
334 	switch (periph) {
335 	case SCLK_SPI0:
336 		con = readl(&cru->cru_clksel_con[25]);
337 		div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
338 		break;
339 	case SCLK_SPI1:
340 		con = readl(&cru->cru_clksel_con[25]);
341 		div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
342 		break;
343 	default:
344 		return -EINVAL;
345 	}
346 
347 	return DIV_TO_RATE(gclk_rate, div);
348 }
349 
350 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
351 				  int periph, uint freq)
352 {
353 	int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
354 
355 	switch (periph) {
356 	case SCLK_SPI0:
357 		assert(src_clk_div <= SPI0_DIV_MASK);
358 		rk_clrsetreg(&cru->cru_clksel_con[25],
359 			     SPI0_DIV_MASK << SPI0_DIV_SHIFT,
360 			     src_clk_div << SPI0_DIV_SHIFT);
361 		break;
362 	case SCLK_SPI1:
363 		assert(src_clk_div <= SPI1_DIV_MASK);
364 		rk_clrsetreg(&cru->cru_clksel_con[25],
365 			     SPI1_DIV_MASK << SPI1_DIV_SHIFT,
366 			     src_clk_div << SPI1_DIV_SHIFT);
367 		break;
368 	default:
369 		return -EINVAL;
370 	}
371 
372 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
373 }
374 
375 #ifdef CONFIG_SPL_BUILD
376 static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
377 		       bool has_bwadj)
378 {
379 	u32 aclk_div, hclk_div, pclk_div, h2p_div;
380 
381 	/* pll enter slow-mode */
382 	rk_clrsetreg(&cru->cru_mode_con,
383 		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
384 		     CPLL_MODE_MASK << CPLL_MODE_SHIFT,
385 		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
386 		     CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
387 
388 	/* init pll */
389 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
390 	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
391 
392 	/* waiting for pll lock */
393 	while ((readl(&grf->soc_status0) &
394 			(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
395 			(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
396 		udelay(1);
397 
398 	/*
399 	 * cpu clock pll source selection and
400 	 * reparent aclk_cpu_pre from apll to gpll
401 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
402 	 */
403 	aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
404 	assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
405 
406 	rk_clrsetreg(&cru->cru_clksel_con[0],
407 		     CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
408 		     A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
409 		     CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
410 		     aclk_div << A9_CPU_DIV_SHIFT);
411 
412 	hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
413 	assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
414 	pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
415 	assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
416 	h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
417 	assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
418 
419 	rk_clrsetreg(&cru->cru_clksel_con[1],
420 		     AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
421 		     CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
422 		     CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
423 		     h2p_div << AHB2APB_DIV_SHIFT |
424 		     pclk_div << CPU_PCLK_DIV_SHIFT |
425 		     hclk_div << CPU_HCLK_DIV_SHIFT);
426 
427 	/*
428 	 * peri clock pll source selection and
429 	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
430 	 */
431 	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
432 	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
433 
434 	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
435 	assert((1 << hclk_div) * PERI_HCLK_HZ ==
436 		PERI_ACLK_HZ && (hclk_div < 0x4));
437 
438 	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
439 	assert((1 << pclk_div) * PERI_PCLK_HZ ==
440 		PERI_ACLK_HZ && (pclk_div < 0x4));
441 
442 	rk_clrsetreg(&cru->cru_clksel_con[10],
443 		     PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
444 		     PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
445 		     PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
446 		     PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
447 		     pclk_div << PERI_PCLK_DIV_SHIFT |
448 		     hclk_div << PERI_HCLK_DIV_SHIFT |
449 		     aclk_div << PERI_ACLK_DIV_SHIFT);
450 
451 	/* PLL enter normal-mode */
452 	rk_clrsetreg(&cru->cru_mode_con,
453 		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
454 		     CPLL_MODE_MASK << CPLL_MODE_SHIFT,
455 		     GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
456 		     CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
457 
458 	rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
459 }
460 #endif
461 
462 static ulong rk3188_clk_get_rate(struct clk *clk)
463 {
464 	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
465 	ulong new_rate, gclk_rate;
466 
467 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
468 	switch (clk->id) {
469 	case 1 ... 4:
470 		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
471 		break;
472 	case HCLK_EMMC:
473 	case HCLK_SDMMC:
474 	case HCLK_SDIO:
475 	case SCLK_EMMC:
476 	case SCLK_SDMMC:
477 	case SCLK_SDIO:
478 		new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
479 						clk->id);
480 		break;
481 	case SCLK_SPI0:
482 	case SCLK_SPI1:
483 		new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
484 						clk->id);
485 		break;
486 	case PCLK_I2C0:
487 	case PCLK_I2C1:
488 	case PCLK_I2C2:
489 	case PCLK_I2C3:
490 	case PCLK_I2C4:
491 		return gclk_rate;
492 	default:
493 		return -ENOENT;
494 	}
495 
496 	return new_rate;
497 }
498 
499 static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
500 {
501 	struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
502 	struct rk3188_cru *cru = priv->cru;
503 	ulong new_rate;
504 
505 	switch (clk->id) {
506 	case PLL_APLL:
507 		new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
508 					       priv->has_bwadj);
509 		break;
510 	case CLK_DDR:
511 		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
512 					       priv->has_bwadj);
513 		break;
514 	case HCLK_EMMC:
515 	case HCLK_SDMMC:
516 	case HCLK_SDIO:
517 	case SCLK_EMMC:
518 	case SCLK_SDMMC:
519 	case SCLK_SDIO:
520 		new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
521 						clk->id, rate);
522 		break;
523 	case SCLK_SPI0:
524 	case SCLK_SPI1:
525 		new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
526 						clk->id, rate);
527 		break;
528 	default:
529 		return -ENOENT;
530 	}
531 
532 	return new_rate;
533 }
534 
535 static struct clk_ops rk3188_clk_ops = {
536 	.get_rate	= rk3188_clk_get_rate,
537 	.set_rate	= rk3188_clk_set_rate,
538 };
539 
540 static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
541 {
542 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
543 	struct rk3188_clk_priv *priv = dev_get_priv(dev);
544 
545 	priv->cru = (struct rk3188_cru *)dev_get_addr(dev);
546 #endif
547 
548 	return 0;
549 }
550 
551 static int rk3188_clk_probe(struct udevice *dev)
552 {
553 	struct rk3188_clk_priv *priv = dev_get_priv(dev);
554 	enum rk3188_clk_type type = dev_get_driver_data(dev);
555 
556 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
557 	if (IS_ERR(priv->grf))
558 		return PTR_ERR(priv->grf);
559 	priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
560 
561 #ifdef CONFIG_SPL_BUILD
562 #if CONFIG_IS_ENABLED(OF_PLATDATA)
563 	struct rk3188_clk_plat *plat = dev_get_platdata(dev);
564 
565 	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
566 #endif
567 
568 	rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
569 #endif
570 
571 	return 0;
572 }
573 
574 static int rk3188_clk_bind(struct udevice *dev)
575 {
576 	int ret;
577 
578 	/* The reset driver does not have a device node, so bind it here */
579 	ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev);
580 	if (ret)
581 		debug("Warning: No rk3188 reset driver: ret=%d\n", ret);
582 
583 	return 0;
584 }
585 
586 static const struct udevice_id rk3188_clk_ids[] = {
587 	{ .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
588 	{ .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
589 	{ }
590 };
591 
592 U_BOOT_DRIVER(rockchip_rk3188_cru) = {
593 	.name			= "rockchip_rk3188_cru",
594 	.id			= UCLASS_CLK,
595 	.of_match		= rk3188_clk_ids,
596 	.priv_auto_alloc_size	= sizeof(struct rk3188_clk_priv),
597 	.platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat),
598 	.ops			= &rk3188_clk_ops,
599 	.bind			= rk3188_clk_bind,
600 	.ofdata_to_platdata	= rk3188_clk_ofdata_to_platdata,
601 	.probe			= rk3188_clk_probe,
602 };
603