1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Renesas RCar Gen3 CPG MSSR driver
4  *
5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6  *
7  * Based on the following driver from Linux kernel:
8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9  *
10  * Copyright (C) 2016 Glider bvba
11  */
12 #include <common.h>
13 #include <clk-uclass.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18 
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
20 
21 #include "renesas-cpg-mssr.h"
22 
23 /*
24  * Module Standby and Software Reset register offets.
25  *
26  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
27  * R-Car Gen2, R-Car Gen3, and RZ/G1.
28  * These are NOT valid for R-Car Gen1 and RZ/A1!
29  */
30 
31 /*
32  * Module Stop Status Register offsets
33  */
34 
35 static const u16 mstpsr[] = {
36 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
37 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
38 };
39 
40 #define	MSTPSR(i)	mstpsr[i]
41 
42 
43 /*
44  * System Module Stop Control Register offsets
45  */
46 
47 static const u16 smstpcr[] = {
48 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
49 	0x990, 0x994, 0x998, 0x99C,
50 };
51 
52 #define	SMSTPCR(i)	smstpcr[i]
53 
54 
55 /* Realtime Module Stop Control Register offsets */
56 #define RMSTPCR(i)	(smstpcr[i] - 0x20)
57 
58 /* Modem Module Stop Control Register offsets (r8a73a4) */
59 #define MMSTPCR(i)	(smstpcr[i] + 0x20)
60 
61 /* Software Reset Clearing Register offsets */
62 #define	SRSTCLR(i)	(0x940 + (i) * 4)
63 
64 bool renesas_clk_is_mod(struct clk *clk)
65 {
66 	return (clk->id >> 16) == CPG_MOD;
67 }
68 
69 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
70 			const struct mssr_mod_clk **mssr)
71 {
72 	const unsigned long clkid = clk->id & 0xffff;
73 	int i;
74 
75 	for (i = 0; i < info->mod_clk_size; i++) {
76 		if (info->mod_clk[i].id !=
77 		    (info->mod_clk_base + MOD_CLK_PACK(clkid)))
78 			continue;
79 
80 		*mssr = &info->mod_clk[i];
81 		return 0;
82 	}
83 
84 	return -ENODEV;
85 }
86 
87 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
88 			 const struct cpg_core_clk **core)
89 {
90 	const unsigned long clkid = clk->id & 0xffff;
91 	int i;
92 
93 	for (i = 0; i < info->core_clk_size; i++) {
94 		if (info->core_clk[i].id != clkid)
95 			continue;
96 
97 		*core = &info->core_clk[i];
98 		return 0;
99 	}
100 
101 	return -ENODEV;
102 }
103 
104 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
105 			   struct clk *parent)
106 {
107 	const struct cpg_core_clk *core;
108 	const struct mssr_mod_clk *mssr;
109 	int ret;
110 
111 	if (renesas_clk_is_mod(clk)) {
112 		ret = renesas_clk_get_mod(clk, info, &mssr);
113 		if (ret)
114 			return ret;
115 
116 		parent->id = mssr->parent;
117 	} else {
118 		ret = renesas_clk_get_core(clk, info, &core);
119 		if (ret)
120 			return ret;
121 
122 		if (core->type == CLK_TYPE_IN)
123 			parent->id = ~0;	/* Top-level clock */
124 		else
125 			parent->id = core->parent;
126 	}
127 
128 	parent->dev = clk->dev;
129 
130 	return 0;
131 }
132 
133 int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
134 {
135 	const unsigned long clkid = clk->id & 0xffff;
136 	const unsigned int reg = clkid / 100;
137 	const unsigned int bit = clkid % 100;
138 	const u32 bitmask = BIT(bit);
139 
140 	if (!renesas_clk_is_mod(clk))
141 		return -EINVAL;
142 
143 	debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
144 	      clkid, reg, bit, enable ? "ON" : "OFF");
145 
146 	if (enable) {
147 		clrbits_le32(base + SMSTPCR(reg), bitmask);
148 		return wait_for_bit_le32(base + MSTPSR(reg),
149 				    bitmask, 0, 100, 0);
150 	} else {
151 		setbits_le32(base + SMSTPCR(reg), bitmask);
152 		return 0;
153 	}
154 }
155 
156 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
157 {
158 	unsigned int i;
159 
160 	/* Stop TMU0 */
161 	clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
162 
163 	/* Stop module clock */
164 	for (i = 0; i < info->mstp_table_size; i++) {
165 		clrsetbits_le32(base + SMSTPCR(i),
166 				info->mstp_table[i].sdis,
167 				info->mstp_table[i].sen);
168 		clrsetbits_le32(base + RMSTPCR(i),
169 				info->mstp_table[i].rdis,
170 				info->mstp_table[i].ren);
171 	}
172 
173 	return 0;
174 }
175