1 /* 2 * Renesas R8A77995 CPG MSSR driver 3 * 4 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * Based on the following driver from Linux kernel: 7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 8 * 9 * Copyright (C) 2016 Glider bvba 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <clk-uclass.h> 16 #include <dm.h> 17 18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h> 19 20 #include "renesas-cpg-mssr.h" 21 #include "rcar-gen3-cpg.h" 22 23 enum clk_ids { 24 /* Core Clock Outputs exported to DT */ 25 LAST_DT_CORE_CLK = R8A77995_CLK_CP, 26 27 /* External Input Clocks */ 28 CLK_EXTAL, 29 30 /* Internal Core Clocks */ 31 CLK_MAIN, 32 CLK_PLL0, 33 CLK_PLL1, 34 CLK_PLL3, 35 CLK_PLL0D2, 36 CLK_PLL0D3, 37 CLK_PLL0D5, 38 CLK_PLL1D2, 39 CLK_PE, 40 CLK_S0, 41 CLK_S1, 42 CLK_S2, 43 CLK_S3, 44 CLK_SDSRC, 45 CLK_SSPSRC, 46 47 /* Module Clocks */ 48 MOD_CLK_BASE 49 }; 50 51 static const struct cpg_core_clk r8a77995_core_clks[] = { 52 /* External Clock Inputs */ 53 DEF_INPUT("extal", CLK_EXTAL), 54 55 /* Internal Core Clocks */ 56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 57 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 58 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 59 60 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250), 61 DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1), 62 DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1), 63 DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1), 64 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), 65 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1), 66 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), 67 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), 68 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), 69 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), 70 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), 71 72 /* Core Clock Outputs */ 73 DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), 74 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), 75 DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), 76 DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1), 77 DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1), 78 DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1), 79 DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1), 80 DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1), 81 DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1), 82 DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1), 83 DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1), 84 DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1), 85 DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1), 86 DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1), 87 88 DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), 89 DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), 90 DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), 91 DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), 92 93 DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), 94 DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), 95 DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), 96 DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), 97 98 DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), 99 }; 100 101 static const struct mssr_mod_clk r8a77995_mod_clks[] = { 102 DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C), 103 DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C), 104 DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C), 105 DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C), 106 DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C), 107 DEF_MOD("msiof3", 208, R8A77995_CLK_MSO), 108 DEF_MOD("msiof2", 209, R8A77995_CLK_MSO), 109 DEF_MOD("msiof1", 210, R8A77995_CLK_MSO), 110 DEF_MOD("msiof0", 211, R8A77995_CLK_MSO), 111 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), 112 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), 113 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), 114 DEF_MOD("cmt3", 300, R8A77995_CLK_R), 115 DEF_MOD("cmt2", 301, R8A77995_CLK_R), 116 DEF_MOD("cmt1", 302, R8A77995_CLK_R), 117 DEF_MOD("cmt0", 303, R8A77995_CLK_R), 118 DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C), 119 DEF_MOD("emmc0", 312, R8A77995_CLK_SD0), 120 DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1), 121 DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1), 122 DEF_MOD("rwdt", 402, R8A77995_CLK_R), 123 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), 124 DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1), 125 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), 126 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), 127 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), 128 DEF_MOD("thermal", 522, R8A77995_CLK_CP), 129 DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C), 130 DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2), 131 DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2), 132 DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1), 133 DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2), 134 DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2), 135 DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1), 136 DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2), 137 DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2), 138 DEF_MOD("du1", 723, R8A77995_CLK_S2D1), 139 DEF_MOD("du0", 724, R8A77995_CLK_S2D1), 140 DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), 141 DEF_MOD("vin7", 804, R8A77995_CLK_S1D2), 142 DEF_MOD("vin6", 805, R8A77995_CLK_S1D2), 143 DEF_MOD("vin5", 806, R8A77995_CLK_S1D2), 144 DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), 145 DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), 146 DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), 147 DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4), 148 DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4), 149 DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4), 150 DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4), 151 DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4), 152 DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4), 153 DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4), 154 DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), 155 DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), 156 DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), 157 DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), 158 DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), 159 DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), 160 DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2), 161 DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4), 162 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 163 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 164 DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4), 165 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 166 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 167 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 168 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 169 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 170 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 171 }; 172 173 /* 174 * CPG Clock Data 175 */ 176 177 /* 178 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 179 *-------------------------------------------------------------------- 180 * 0 48 x 1 x250/4 x100/3 x100/3 181 * 1 48 x 1 x250/4 x100/3 x116/6 182 */ 183 #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) 184 185 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = { 186 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 187 { 1, 100, 3, 100, 3, }, 188 { 1, 100, 3, 116, 6, }, 189 }; 190 191 static const struct mstp_stop_table r8a77995_mstp_table[] = { 192 { 0x00200000, 0x0, 0x00200000, 0 }, 193 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, 194 { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, 195 { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, 196 { 0x80000184, 0x180, 0x80000184, 0 }, 197 { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, 198 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, 199 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, 200 { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, 201 { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, 202 { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, 203 { 0x000000B7, 0x0, 0x000000B7, 0 }, 204 }; 205 206 static const void *r8a77995_get_pll_config(const u32 cpg_mode) 207 { 208 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 209 } 210 211 static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { 212 .core_clk = r8a77995_core_clks, 213 .core_clk_size = ARRAY_SIZE(r8a77995_core_clks), 214 .mod_clk = r8a77995_mod_clks, 215 .mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks), 216 .mstp_table = r8a77995_mstp_table, 217 .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table), 218 .reset_node = "renesas,r8a77995-rst", 219 .mod_clk_base = MOD_CLK_BASE, 220 .clk_extal_id = CLK_EXTAL, 221 .clk_extalr_id = ~0, 222 .get_pll_config = r8a77995_get_pll_config, 223 }; 224 225 static const struct udevice_id r8a77995_clk_ids[] = { 226 { 227 .compatible = "renesas,r8a77995-cpg-mssr", 228 .data = (ulong)&r8a77995_cpg_mssr_info 229 }, 230 { } 231 }; 232 233 U_BOOT_DRIVER(clk_r8a77995) = { 234 .name = "clk_r8a77995", 235 .id = UCLASS_CLK, 236 .of_match = r8a77995_clk_ids, 237 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), 238 .ops = &gen3_clk_ops, 239 .probe = gen3_clk_probe, 240 .remove = gen3_clk_remove, 241 }; 242