1 /*
2  * Renesas R8A77970 CPG MSSR driver
3  *
4  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * Based on the following driver from Linux kernel:
7  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
8  *
9  * Copyright (C) 2016 Glider bvba
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #include <common.h>
15 #include <clk-uclass.h>
16 #include <dm.h>
17 
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
19 
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
22 
23 enum clk_ids {
24 	/* Core Clock Outputs exported to DT */
25 	LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
26 
27 	/* External Input Clocks */
28 	CLK_EXTAL,
29 	CLK_EXTALR,
30 
31 	/* Internal Core Clocks */
32 	CLK_MAIN,
33 	CLK_PLL0,
34 	CLK_PLL1,
35 	CLK_PLL2,
36 	CLK_PLL3,
37 	CLK_PLL4,
38 	CLK_PLL1_DIV2,
39 	CLK_PLL1_DIV4,
40 	CLK_PLL0D2,
41 	CLK_PLL0D3,
42 	CLK_PLL0D5,
43 	CLK_PLL1D2,
44 	CLK_PE,
45 	CLK_S0,
46 	CLK_S1,
47 	CLK_S2,
48 	CLK_S3,
49 	CLK_SDSRC,
50 	CLK_RPCSRC,
51 	CLK_SSPSRC,
52 	CLK_RINT,
53 
54 	/* Module Clocks */
55 	MOD_CLK_BASE
56 };
57 
58 static const struct cpg_core_clk r8a77970_core_clks[] = {
59 	/* External Clock Inputs */
60 	DEF_INPUT("extal",  CLK_EXTAL),
61 	DEF_INPUT("extalr", CLK_EXTALR),
62 
63 	/* Internal Core Clocks */
64 	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
65 	DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
66 	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
67 	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
68 
69 	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
70 	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
71 	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  4, 1),
72 	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  6, 1),
73 	DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
74 
75 	/* Core Clock Outputs */
76 	DEF_BASE("z2",          R8A77970_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
77 	DEF_FIXED("ztr",        R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
78 	DEF_FIXED("ztrd2",      R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
79 	DEF_FIXED("zt",         R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
80 	DEF_FIXED("zx",         R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
81 	DEF_FIXED("s1d1",       R8A77970_CLK_S1D1,  CLK_S1,         1, 1),
82 	DEF_FIXED("s1d2",       R8A77970_CLK_S1D2,  CLK_S1,         2, 1),
83 	DEF_FIXED("s1d4",       R8A77970_CLK_S1D4,  CLK_S1,         4, 1),
84 	DEF_FIXED("s2d1",       R8A77970_CLK_S2D1,  CLK_S2,         1, 1),
85 	DEF_FIXED("s2d2",       R8A77970_CLK_S2D2,  CLK_S2,         2, 1),
86 	DEF_FIXED("s2d4",       R8A77970_CLK_S2D4,  CLK_S2,         4, 1),
87 
88 	DEF_GEN3_SD("sd0",      R8A77970_CLK_SD0,   CLK_PLL1_DIV4, 0x0074),
89 
90 	DEF_GEN3_RPC("rpc",     R8A77970_CLK_RPC,   CLK_RPCSRC,    0x238),
91 
92 	DEF_FIXED("cl",         R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
93 	DEF_FIXED("cp",         R8A77970_CLK_CP,    CLK_EXTAL,      2, 1),
94 
95 	/* NOTE: HDMI, CSI, CAN etc. clock are missing */
96 
97 	DEF_BASE("r",           R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
98 };
99 
100 static const struct mssr_mod_clk r8a77970_mod_clks[] = {
101 	DEF_MOD("ivcp1e",		 127,	R8A77970_CLK_S2D1),
102 	DEF_MOD("scif4",		 203,	R8A77970_CLK_S2D4),	/* @@ H3=S3D4 */
103 	DEF_MOD("scif3",		 204,	R8A77970_CLK_S2D4),	/* @@ H3=S3D4 */
104 	DEF_MOD("scif1",		 206,	R8A77970_CLK_S2D4),	/* @@ H3=S3D4 */
105 	DEF_MOD("scif0",		 207,	R8A77970_CLK_S2D4),	/* @@ H3=S3D4 */
106 	DEF_MOD("msiof3",		 208,	R8A77970_CLK_MSO),
107 	DEF_MOD("msiof2",		 209,	R8A77970_CLK_MSO),
108 	DEF_MOD("msiof1",		 210,	R8A77970_CLK_MSO),
109 	DEF_MOD("msiof0",		 211,	R8A77970_CLK_MSO),
110 	DEF_MOD("mfis",			 213,	R8A77970_CLK_S2D2),	/* @@ H3=S3D2 */
111 	DEF_MOD("sys-dmac2",	 217,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
112 	DEF_MOD("sys-dmac1",	 218,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
113 	DEF_MOD("sdif",			 314,	R8A77970_CLK_SD0),
114 	DEF_MOD("rwdt0",		 402,	R8A77970_CLK_R),
115 	DEF_MOD("intc-ex",		 407,	R8A77970_CLK_CP),
116 	DEF_MOD("intc-ap",		 408,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
117 	DEF_MOD("hscif3",		 517,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
118 	DEF_MOD("hscif2",		 518,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
119 	DEF_MOD("hscif1",		 519,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
120 	DEF_MOD("hscif0",		 520,	R8A77970_CLK_S2D1),	/* @@ H3=S3D1 */
121 	DEF_MOD("thermal",		 522,	R8A77970_CLK_CP),
122 	DEF_MOD("pwm",			 523,	R8A77970_CLK_S2D4),
123 	DEF_MOD("fcpvd0",		 603,	R8A77970_CLK_S2D1),
124 	DEF_MOD("vspd0",		 623,	R8A77970_CLK_S2D1),
125 	DEF_MOD("csi40",		 716,	R8A77970_CLK_CSI0),
126 	DEF_MOD("du0",			 724,	R8A77970_CLK_S2D1),
127 	DEF_MOD("lvds",			 727,	R8A77970_CLK_S2D1),
128 	DEF_MOD("vin3",			 808,	R8A77970_CLK_S2D1),
129 	DEF_MOD("vin2",			 809,	R8A77970_CLK_S2D1),
130 	DEF_MOD("vin1",			 810,	R8A77970_CLK_S2D1),
131 	DEF_MOD("vin0",			 811,	R8A77970_CLK_S2D1),
132 	DEF_MOD("etheravb",		 812,	R8A77970_CLK_S2D2),
133 	DEF_MOD("isp",			 817,	R8A77970_CLK_S2D1),
134 	DEF_MOD("gpio5",		 907,	R8A77970_CLK_CP),
135 	DEF_MOD("gpio4",		 908,	R8A77970_CLK_CP),
136 	DEF_MOD("gpio3",		 909,	R8A77970_CLK_CP),
137 	DEF_MOD("gpio2",		 910,	R8A77970_CLK_CP),
138 	DEF_MOD("gpio1",		 911,	R8A77970_CLK_CP),
139 	DEF_MOD("gpio0",		 912,	R8A77970_CLK_CP),
140 	DEF_MOD("can-fd",		 914,	R8A77970_CLK_S2D2),
141 	DEF_MOD("rpc",			 917,	R8A77970_CLK_RPC),
142 	DEF_MOD("i2c4",			 927,	R8A77970_CLK_S2D2),
143 	DEF_MOD("i2c3",			 928,	R8A77970_CLK_S2D2),
144 	DEF_MOD("i2c2",			 929,	R8A77970_CLK_S2D2),
145 	DEF_MOD("i2c1",			 930,	R8A77970_CLK_S2D2),
146 	DEF_MOD("i2c0",			 931,	R8A77970_CLK_S2D2),
147 };
148 
149 /*
150  * CPG Clock Data
151  */
152 
153 /*
154  *   MD		EXTAL		PLL0	PLL1	PLL3
155  * 14 13 19	(MHz)
156  *-------------------------------------------------
157  * 0  0  0	16.66 x 1	x192	x192	x96
158  * 0  0  1	16.66 x 1	x192	x192	x80
159  * 0  1  0	20    x 1	x160	x160	x80
160  * 0  1  1	20    x 1	x160	x160	x66
161  * 1  0  0	27    / 2	x236	x236	x118
162  * 1  0  1	27    / 2	x236	x236	x98
163  * 1  1  0	33.33 / 2	x192	x192	x96
164  * 1  1  1	33.33 / 2	x192	x192	x80
165  */
166 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
167 					 (((md) & BIT(13)) >> 12) | \
168 					 (((md) & BIT(19)) >> 19))
169 
170 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
171 	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
172 	{ 1,		192,	1,	96,	1,	},
173 	{ 1,		192,	1,	80,	1,	},
174 	{ 1,		160,	1,	80,	1,	},
175 	{ 1,		160,	1,	66,	1,	},
176 	{ 2,		236,	1,	118,	1,	},
177 	{ 2,		236,	1,	98,	1,	},
178 	{ 2,		192,	1,	96,	1,	},
179 	{ 2,		192,	1,	80,	1,	},
180 };
181 
182 static const struct mstp_stop_table r8a77970_mstp_table[] = {
183 	{ 0x00230000, 0x0, 0x00230000, 0 },
184 	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
185 	{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
186 	{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
187 	{ 0x80000184, 0x180, 0x80000184, 0 },
188 	{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
189 	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
190 	{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
191 	{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
192 	{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
193 	{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
194 	{ 0x000000B7, 0x0, 0x000000B7, 0 },
195 };
196 
197 static const void *r8a77970_get_pll_config(const u32 cpg_mode)
198 {
199 	return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
200 }
201 
202 static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
203 	.core_clk		= r8a77970_core_clks,
204 	.core_clk_size		= ARRAY_SIZE(r8a77970_core_clks),
205 	.mod_clk		= r8a77970_mod_clks,
206 	.mod_clk_size		= ARRAY_SIZE(r8a77970_mod_clks),
207 	.mstp_table		= r8a77970_mstp_table,
208 	.mstp_table_size	= ARRAY_SIZE(r8a77970_mstp_table),
209 	.reset_node		= "renesas,r8a77970-rst",
210 	.extalr_node		= "extalr",
211 	.mod_clk_base		= MOD_CLK_BASE,
212 	.clk_extal_id		= CLK_EXTAL,
213 	.clk_extalr_id		= CLK_EXTALR,
214 	.get_pll_config		= r8a77970_get_pll_config,
215 };
216 
217 static const struct udevice_id r8a77970_clk_ids[] = {
218 	{
219 		.compatible	= "renesas,r8a77970-cpg-mssr",
220 		.data		= (ulong)&r8a77970_cpg_mssr_info
221 	},
222 	{ }
223 };
224 
225 U_BOOT_DRIVER(clk_r8a77970) = {
226 	.name		= "clk_r8a77970",
227 	.id		= UCLASS_CLK,
228 	.of_match	= r8a77970_clk_ids,
229 	.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
230 	.ops		= &gen3_clk_ops,
231 	.probe		= gen3_clk_probe,
232 	.remove		= gen3_clk_remove,
233 };
234