1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas R8A77970 CPG MSSR driver 4 * 5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on the following driver from Linux kernel: 8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 9 * 10 * Copyright (C) 2016 Glider bvba 11 */ 12 13 #include <common.h> 14 #include <clk-uclass.h> 15 #include <dm.h> 16 17 #include <dt-bindings/clock/r8a77970-cpg-mssr.h> 18 19 #include "renesas-cpg-mssr.h" 20 #include "rcar-gen3-cpg.h" 21 22 enum clk_ids { 23 /* Core Clock Outputs exported to DT */ 24 LAST_DT_CORE_CLK = R8A77970_CLK_OSC, 25 26 /* External Input Clocks */ 27 CLK_EXTAL, 28 CLK_EXTALR, 29 30 /* Internal Core Clocks */ 31 CLK_MAIN, 32 CLK_PLL0, 33 CLK_PLL1, 34 CLK_PLL2, 35 CLK_PLL3, 36 CLK_PLL4, 37 CLK_PLL1_DIV2, 38 CLK_PLL1_DIV4, 39 CLK_PLL0D2, 40 CLK_PLL0D3, 41 CLK_PLL0D5, 42 CLK_PLL1D2, 43 CLK_PE, 44 CLK_S0, 45 CLK_S1, 46 CLK_S2, 47 CLK_S3, 48 CLK_SDSRC, 49 CLK_RPCSRC, 50 CLK_SSPSRC, 51 CLK_RINT, 52 53 /* Module Clocks */ 54 MOD_CLK_BASE 55 }; 56 57 static const struct cpg_core_clk r8a77970_core_clks[] = { 58 /* External Clock Inputs */ 59 DEF_INPUT("extal", CLK_EXTAL), 60 DEF_INPUT("extalr", CLK_EXTALR), 61 62 /* Internal Core Clocks */ 63 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 64 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 65 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 66 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 67 68 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 69 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 70 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1), 71 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1), 72 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), 73 74 /* Core Clock Outputs */ 75 DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4), 76 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 77 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 78 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 79 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), 80 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1), 81 DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1), 82 DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1), 83 DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1), 84 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1), 85 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1), 86 87 DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074), 88 89 DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238), 90 91 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), 92 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), 93 94 /* NOTE: HDMI, CSI, CAN etc. clock are missing */ 95 96 DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 97 }; 98 99 static const struct mssr_mod_clk r8a77970_mod_clks[] = { 100 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), 101 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 102 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 103 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 104 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 105 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO), 106 DEF_MOD("msiof2", 209, R8A77970_CLK_MSO), 107 DEF_MOD("msiof1", 210, R8A77970_CLK_MSO), 108 DEF_MOD("msiof0", 211, R8A77970_CLK_MSO), 109 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */ 110 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 111 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 112 DEF_MOD("sdif", 314, R8A77970_CLK_SD0), 113 DEF_MOD("rwdt0", 402, R8A77970_CLK_R), 114 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), 115 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 116 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 117 DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 118 DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 119 DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 120 DEF_MOD("thermal", 522, R8A77970_CLK_CP), 121 DEF_MOD("pwm", 523, R8A77970_CLK_S2D4), 122 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1), 123 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1), 124 DEF_MOD("csi40", 716, R8A77970_CLK_CSI0), 125 DEF_MOD("du0", 724, R8A77970_CLK_S2D1), 126 DEF_MOD("lvds", 727, R8A77970_CLK_S2D1), 127 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1), 128 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1), 129 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1), 130 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1), 131 DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2), 132 DEF_MOD("isp", 817, R8A77970_CLK_S2D1), 133 DEF_MOD("gpio5", 907, R8A77970_CLK_CP), 134 DEF_MOD("gpio4", 908, R8A77970_CLK_CP), 135 DEF_MOD("gpio3", 909, R8A77970_CLK_CP), 136 DEF_MOD("gpio2", 910, R8A77970_CLK_CP), 137 DEF_MOD("gpio1", 911, R8A77970_CLK_CP), 138 DEF_MOD("gpio0", 912, R8A77970_CLK_CP), 139 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), 140 DEF_MOD("rpc", 917, R8A77970_CLK_RPC), 141 DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), 142 DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), 143 DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), 144 DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2), 145 DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2), 146 }; 147 148 /* 149 * CPG Clock Data 150 */ 151 152 /* 153 * MD EXTAL PLL0 PLL1 PLL3 154 * 14 13 19 (MHz) 155 *------------------------------------------------- 156 * 0 0 0 16.66 x 1 x192 x192 x96 157 * 0 0 1 16.66 x 1 x192 x192 x80 158 * 0 1 0 20 x 1 x160 x160 x80 159 * 0 1 1 20 x 1 x160 x160 x66 160 * 1 0 0 27 / 2 x236 x236 x118 161 * 1 0 1 27 / 2 x236 x236 x98 162 * 1 1 0 33.33 / 2 x192 x192 x96 163 * 1 1 1 33.33 / 2 x192 x192 x80 164 */ 165 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ 166 (((md) & BIT(13)) >> 12) | \ 167 (((md) & BIT(19)) >> 19)) 168 169 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = { 170 /* EXTAL div PLL1 mult/div PLL3 mult/div */ 171 { 1, 192, 1, 96, 1, }, 172 { 1, 192, 1, 80, 1, }, 173 { 1, 160, 1, 80, 1, }, 174 { 1, 160, 1, 66, 1, }, 175 { 2, 236, 1, 118, 1, }, 176 { 2, 236, 1, 98, 1, }, 177 { 2, 192, 1, 96, 1, }, 178 { 2, 192, 1, 80, 1, }, 179 }; 180 181 static const struct mstp_stop_table r8a77970_mstp_table[] = { 182 { 0x00230000, 0x0, 0x00230000, 0 }, 183 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, 184 { 0x14062FD8, 0x2040, 0x14062FD8, 0 }, 185 { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, 186 { 0x80000184, 0x180, 0x80000184, 0 }, 187 { 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 }, 188 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, 189 { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, 190 { 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 }, 191 { 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 }, 192 { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, 193 { 0x000000B7, 0x0, 0x000000B7, 0 }, 194 }; 195 196 static const void *r8a77970_get_pll_config(const u32 cpg_mode) 197 { 198 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 199 } 200 201 static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { 202 .core_clk = r8a77970_core_clks, 203 .core_clk_size = ARRAY_SIZE(r8a77970_core_clks), 204 .mod_clk = r8a77970_mod_clks, 205 .mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks), 206 .mstp_table = r8a77970_mstp_table, 207 .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table), 208 .reset_node = "renesas,r8a77970-rst", 209 .extalr_node = "extalr", 210 .mod_clk_base = MOD_CLK_BASE, 211 .clk_extal_id = CLK_EXTAL, 212 .clk_extalr_id = CLK_EXTALR, 213 .get_pll_config = r8a77970_get_pll_config, 214 }; 215 216 static const struct udevice_id r8a77970_clk_ids[] = { 217 { 218 .compatible = "renesas,r8a77970-cpg-mssr", 219 .data = (ulong)&r8a77970_cpg_mssr_info 220 }, 221 { } 222 }; 223 224 U_BOOT_DRIVER(clk_r8a77970) = { 225 .name = "clk_r8a77970", 226 .id = UCLASS_CLK, 227 .of_match = r8a77970_clk_ids, 228 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), 229 .ops = &gen3_clk_ops, 230 .probe = gen3_clk_probe, 231 .remove = gen3_clk_remove, 232 }; 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