1 /* 2 * r8a7794 Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2017 Glider bvba 5 * 6 * Based on clk-rcar-gen2.c 7 * 8 * Copyright (C) 2013 Ideas On Board SPRL 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 */ 14 15 #include <common.h> 16 #include <clk-uclass.h> 17 #include <dm.h> 18 19 #include <dt-bindings/clock/r8a7794-cpg-mssr.h> 20 21 #include "renesas-cpg-mssr.h" 22 #include "rcar-gen2-cpg.h" 23 24 enum clk_ids { 25 /* Core Clock Outputs exported to DT */ 26 LAST_DT_CORE_CLK = R8A7794_CLK_OSC, 27 28 /* External Input Clocks */ 29 CLK_EXTAL, 30 CLK_USB_EXTAL, 31 32 /* Internal Core Clocks */ 33 CLK_MAIN, 34 CLK_PLL0, 35 CLK_PLL1, 36 CLK_PLL3, 37 CLK_PLL1_DIV2, 38 39 /* Module Clocks */ 40 MOD_CLK_BASE 41 }; 42 43 static const struct cpg_core_clk r8a7794_core_clks[] = { 44 /* External Clock Inputs */ 45 DEF_INPUT("extal", CLK_EXTAL), 46 DEF_INPUT("usb_extal", CLK_USB_EXTAL), 47 48 /* Internal Core Clocks */ 49 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 50 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 51 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 52 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), 53 54 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 55 56 /* Core Clock Outputs */ 57 DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), 58 DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 59 DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 60 DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 61 DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 62 DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), 63 64 DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1), 65 DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1), 66 DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1), 67 DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1), 68 DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1), 69 DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1), 70 DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1), 71 DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1), 72 DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1), 73 DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1), 74 DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1), 75 DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1), 76 DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1), 77 DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1), 78 DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1), 79 DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1), 80 DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1), 81 DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1), 82 83 DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078), 84 DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c), 85 DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), 86 }; 87 88 static const struct mssr_mod_clk r8a7794_mod_clks[] = { 89 DEF_MOD("msiof0", 0, R8A7794_CLK_MP), 90 DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), 91 DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), 92 DEF_MOD("jpu", 106, R8A7794_CLK_M2), 93 DEF_MOD("tmu1", 111, R8A7794_CLK_P), 94 DEF_MOD("3dg", 112, R8A7794_CLK_ZG), 95 DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS), 96 DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS), 97 DEF_MOD("tmu3", 121, R8A7794_CLK_P), 98 DEF_MOD("tmu2", 122, R8A7794_CLK_P), 99 DEF_MOD("cmt0", 124, R8A7794_CLK_R), 100 DEF_MOD("tmu0", 125, R8A7794_CLK_CP), 101 DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS), 102 DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS), 103 DEF_MOD("scifa2", 202, R8A7794_CLK_MP), 104 DEF_MOD("scifa1", 203, R8A7794_CLK_MP), 105 DEF_MOD("scifa0", 204, R8A7794_CLK_MP), 106 DEF_MOD("msiof2", 205, R8A7794_CLK_MP), 107 DEF_MOD("scifb0", 206, R8A7794_CLK_MP), 108 DEF_MOD("scifb1", 207, R8A7794_CLK_MP), 109 DEF_MOD("msiof1", 208, R8A7794_CLK_MP), 110 DEF_MOD("scifb2", 216, R8A7794_CLK_MP), 111 DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS), 112 DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS), 113 DEF_MOD("tpu0", 304, R8A7794_CLK_CP), 114 DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3), 115 DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2), 116 DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0), 117 DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0), 118 DEF_MOD("iic0", 318, R8A7794_CLK_HP), 119 DEF_MOD("iic1", 323, R8A7794_CLK_HP), 120 DEF_MOD("cmt1", 329, R8A7794_CLK_R), 121 DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP), 122 DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP), 123 DEF_MOD("irqc", 407, R8A7794_CLK_CP), 124 DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS), 125 DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP), 126 DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP), 127 DEF_MOD("pwm", 523, R8A7794_CLK_P), 128 DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP), 129 DEF_MOD("usbhs", 704, R8A7794_CLK_HP), 130 DEF_MOD("hscif2", 713, R8A7794_CLK_ZS), 131 DEF_MOD("scif5", 714, R8A7794_CLK_P), 132 DEF_MOD("scif4", 715, R8A7794_CLK_P), 133 DEF_MOD("hscif1", 716, R8A7794_CLK_ZS), 134 DEF_MOD("hscif0", 717, R8A7794_CLK_ZS), 135 DEF_MOD("scif3", 718, R8A7794_CLK_P), 136 DEF_MOD("scif2", 719, R8A7794_CLK_P), 137 DEF_MOD("scif1", 720, R8A7794_CLK_P), 138 DEF_MOD("scif0", 721, R8A7794_CLK_P), 139 DEF_MOD("du1", 723, R8A7794_CLK_ZX), 140 DEF_MOD("du0", 724, R8A7794_CLK_ZX), 141 DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX), 142 DEF_MOD("mlb", 802, R8A7794_CLK_HP), 143 DEF_MOD("vin1", 810, R8A7794_CLK_ZG), 144 DEF_MOD("vin0", 811, R8A7794_CLK_ZG), 145 DEF_MOD("etheravb", 812, R8A7794_CLK_HP), 146 DEF_MOD("ether", 813, R8A7794_CLK_P), 147 DEF_MOD("gyro-adc", 901, R8A7794_CLK_P), 148 DEF_MOD("gpio6", 905, R8A7794_CLK_CP), 149 DEF_MOD("gpio5", 907, R8A7794_CLK_CP), 150 DEF_MOD("gpio4", 908, R8A7794_CLK_CP), 151 DEF_MOD("gpio3", 909, R8A7794_CLK_CP), 152 DEF_MOD("gpio2", 910, R8A7794_CLK_CP), 153 DEF_MOD("gpio1", 911, R8A7794_CLK_CP), 154 DEF_MOD("gpio0", 912, R8A7794_CLK_CP), 155 DEF_MOD("can1", 915, R8A7794_CLK_P), 156 DEF_MOD("can0", 916, R8A7794_CLK_P), 157 DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI), 158 DEF_MOD("i2c5", 925, R8A7794_CLK_HP), 159 DEF_MOD("i2c4", 927, R8A7794_CLK_HP), 160 DEF_MOD("i2c3", 928, R8A7794_CLK_HP), 161 DEF_MOD("i2c2", 929, R8A7794_CLK_HP), 162 DEF_MOD("i2c1", 930, R8A7794_CLK_HP), 163 DEF_MOD("i2c0", 931, R8A7794_CLK_HP), 164 DEF_MOD("ssi-all", 1005, R8A7794_CLK_P), 165 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 166 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 167 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 168 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 169 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 170 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 171 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 172 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 173 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 174 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 175 DEF_MOD("scu-all", 1017, R8A7794_CLK_P), 176 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 177 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 178 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 179 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 180 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 181 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 182 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 183 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 184 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 185 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 186 DEF_MOD("scifa3", 1106, R8A7794_CLK_MP), 187 DEF_MOD("scifa4", 1107, R8A7794_CLK_MP), 188 DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), 189 }; 190 191 /* 192 * CPG Clock Data 193 */ 194 195 /* 196 * MD EXTAL PLL0 PLL1 PLL3 197 * 14 13 19 (MHz) *1 *2 198 *--------------------------------------------------- 199 * 0 0 1 15 x200/3 x208/2 x88 200 * 0 1 1 20 x150/3 x156/2 x66 201 * 1 0 1 26 / 2 x230/3 x240/2 x102 202 * 1 1 1 30 / 2 x200/3 x208/2 x88 203 * 204 * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3) 205 * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2) 206 */ 207 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 208 (((md) & BIT(13)) >> 13)) 209 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = { 210 { 1, 208, 88, 200 }, 211 { 1, 156, 66, 150 }, 212 { 2, 240, 102, 230 }, 213 { 2, 208, 88, 200 }, 214 }; 215 216 static const struct mstp_stop_table r8a7794_mstp_table[] = { 217 { 0x00440801, 0x400000, 0x00440801, 0x0 }, 218 { 0x936899DA, 0x0, 0x936899DA, 0x0 }, 219 { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 }, 220 { 0xE084D810, 0x0, 0xE084D810, 0x0 }, 221 { 0x800001C4, 0x180, 0x800001C4, 0x0 }, 222 { 0x40C00044, 0x0, 0x40C00044, 0x0 }, 223 { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ 224 { 0x013FE618, 0x80000, 0x013FE618, 0x0 }, 225 { 0x40803C05, 0x0, 0x40803C05, 0x0 }, 226 { 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 }, 227 { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, 228 { 0x000001C0, 0x0, 0x000001C0, 0x0 }, 229 }; 230 231 static const void *r8a7794_get_pll_config(const u32 cpg_mode) 232 { 233 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 234 } 235 236 static const struct cpg_mssr_info r8a7794_cpg_mssr_info = { 237 .core_clk = r8a7794_core_clks, 238 .core_clk_size = ARRAY_SIZE(r8a7794_core_clks), 239 .mod_clk = r8a7794_mod_clks, 240 .mod_clk_size = ARRAY_SIZE(r8a7794_mod_clks), 241 .mstp_table = r8a7794_mstp_table, 242 .mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table), 243 .reset_node = "renesas,r8a7794-rst", 244 .extal_usb_node = "usb_extal", 245 .mod_clk_base = MOD_CLK_BASE, 246 .clk_extal_id = CLK_EXTAL, 247 .clk_extal_usb_id = CLK_USB_EXTAL, 248 .pll0_div = 2, 249 .get_pll_config = r8a7794_get_pll_config, 250 }; 251 252 static const struct udevice_id r8a7794_clk_ids[] = { 253 { 254 .compatible = "renesas,r8a7794-cpg-mssr", 255 .data = (ulong)&r8a7794_cpg_mssr_info 256 }, 257 { 258 .compatible = "renesas,r8a7793-cpg-mssr", 259 .data = (ulong)&r8a7794_cpg_mssr_info 260 }, 261 { } 262 }; 263 264 U_BOOT_DRIVER(clk_r8a7794) = { 265 .name = "clk_r8a7794", 266 .id = UCLASS_CLK, 267 .of_match = r8a7794_clk_ids, 268 .priv_auto_alloc_size = sizeof(struct gen2_clk_priv), 269 .ops = &gen2_clk_ops, 270 .probe = gen2_clk_probe, 271 .remove = gen2_clk_remove, 272 }; 273