1*19b1a8b7SMarek Vasut /* 2*19b1a8b7SMarek Vasut * r8a7794 Clock Pulse Generator / Module Standby and Software Reset 3*19b1a8b7SMarek Vasut * 4*19b1a8b7SMarek Vasut * Copyright (C) 2017 Glider bvba 5*19b1a8b7SMarek Vasut * 6*19b1a8b7SMarek Vasut * Based on clk-rcar-gen2.c 7*19b1a8b7SMarek Vasut * 8*19b1a8b7SMarek Vasut * Copyright (C) 2013 Ideas On Board SPRL 9*19b1a8b7SMarek Vasut * 10*19b1a8b7SMarek Vasut * This program is free software; you can redistribute it and/or modify 11*19b1a8b7SMarek Vasut * it under the terms of the GNU General Public License as published by 12*19b1a8b7SMarek Vasut * the Free Software Foundation; version 2 of the License. 13*19b1a8b7SMarek Vasut */ 14*19b1a8b7SMarek Vasut 15*19b1a8b7SMarek Vasut #include <common.h> 16*19b1a8b7SMarek Vasut #include <clk-uclass.h> 17*19b1a8b7SMarek Vasut #include <dm.h> 18*19b1a8b7SMarek Vasut 19*19b1a8b7SMarek Vasut #include <dt-bindings/clock/r8a7794-cpg-mssr.h> 20*19b1a8b7SMarek Vasut 21*19b1a8b7SMarek Vasut #include "renesas-cpg-mssr.h" 22*19b1a8b7SMarek Vasut #include "rcar-gen2-cpg.h" 23*19b1a8b7SMarek Vasut 24*19b1a8b7SMarek Vasut enum clk_ids { 25*19b1a8b7SMarek Vasut /* Core Clock Outputs exported to DT */ 26*19b1a8b7SMarek Vasut LAST_DT_CORE_CLK = R8A7794_CLK_OSC, 27*19b1a8b7SMarek Vasut 28*19b1a8b7SMarek Vasut /* External Input Clocks */ 29*19b1a8b7SMarek Vasut CLK_EXTAL, 30*19b1a8b7SMarek Vasut CLK_USB_EXTAL, 31*19b1a8b7SMarek Vasut 32*19b1a8b7SMarek Vasut /* Internal Core Clocks */ 33*19b1a8b7SMarek Vasut CLK_MAIN, 34*19b1a8b7SMarek Vasut CLK_PLL0, 35*19b1a8b7SMarek Vasut CLK_PLL1, 36*19b1a8b7SMarek Vasut CLK_PLL3, 37*19b1a8b7SMarek Vasut CLK_PLL1_DIV2, 38*19b1a8b7SMarek Vasut 39*19b1a8b7SMarek Vasut /* Module Clocks */ 40*19b1a8b7SMarek Vasut MOD_CLK_BASE 41*19b1a8b7SMarek Vasut }; 42*19b1a8b7SMarek Vasut 43*19b1a8b7SMarek Vasut static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { 44*19b1a8b7SMarek Vasut /* External Clock Inputs */ 45*19b1a8b7SMarek Vasut DEF_INPUT("extal", CLK_EXTAL), 46*19b1a8b7SMarek Vasut DEF_INPUT("usb_extal", CLK_USB_EXTAL), 47*19b1a8b7SMarek Vasut 48*19b1a8b7SMarek Vasut /* Internal Core Clocks */ 49*19b1a8b7SMarek Vasut DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 50*19b1a8b7SMarek Vasut DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 51*19b1a8b7SMarek Vasut DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 52*19b1a8b7SMarek Vasut DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), 53*19b1a8b7SMarek Vasut 54*19b1a8b7SMarek Vasut DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 55*19b1a8b7SMarek Vasut 56*19b1a8b7SMarek Vasut /* Core Clock Outputs */ 57*19b1a8b7SMarek Vasut DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), 58*19b1a8b7SMarek Vasut DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 59*19b1a8b7SMarek Vasut DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 60*19b1a8b7SMarek Vasut DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 61*19b1a8b7SMarek Vasut DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 62*19b1a8b7SMarek Vasut DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), 63*19b1a8b7SMarek Vasut 64*19b1a8b7SMarek Vasut DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1), 65*19b1a8b7SMarek Vasut DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1), 66*19b1a8b7SMarek Vasut DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1), 67*19b1a8b7SMarek Vasut DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1), 68*19b1a8b7SMarek Vasut DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1), 69*19b1a8b7SMarek Vasut DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1), 70*19b1a8b7SMarek Vasut DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1), 71*19b1a8b7SMarek Vasut DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1), 72*19b1a8b7SMarek Vasut DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1), 73*19b1a8b7SMarek Vasut DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1), 74*19b1a8b7SMarek Vasut DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1), 75*19b1a8b7SMarek Vasut DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1), 76*19b1a8b7SMarek Vasut DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1), 77*19b1a8b7SMarek Vasut DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1), 78*19b1a8b7SMarek Vasut DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1), 79*19b1a8b7SMarek Vasut DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1), 80*19b1a8b7SMarek Vasut DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1), 81*19b1a8b7SMarek Vasut DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1), 82*19b1a8b7SMarek Vasut 83*19b1a8b7SMarek Vasut DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078), 84*19b1a8b7SMarek Vasut DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c), 85*19b1a8b7SMarek Vasut DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), 86*19b1a8b7SMarek Vasut }; 87*19b1a8b7SMarek Vasut 88*19b1a8b7SMarek Vasut static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { 89*19b1a8b7SMarek Vasut DEF_MOD("msiof0", 0, R8A7794_CLK_MP), 90*19b1a8b7SMarek Vasut DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), 91*19b1a8b7SMarek Vasut DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), 92*19b1a8b7SMarek Vasut DEF_MOD("jpu", 106, R8A7794_CLK_M2), 93*19b1a8b7SMarek Vasut DEF_MOD("tmu1", 111, R8A7794_CLK_P), 94*19b1a8b7SMarek Vasut DEF_MOD("3dg", 112, R8A7794_CLK_ZG), 95*19b1a8b7SMarek Vasut DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS), 96*19b1a8b7SMarek Vasut DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS), 97*19b1a8b7SMarek Vasut DEF_MOD("tmu3", 121, R8A7794_CLK_P), 98*19b1a8b7SMarek Vasut DEF_MOD("tmu2", 122, R8A7794_CLK_P), 99*19b1a8b7SMarek Vasut DEF_MOD("cmt0", 124, R8A7794_CLK_R), 100*19b1a8b7SMarek Vasut DEF_MOD("tmu0", 125, R8A7794_CLK_CP), 101*19b1a8b7SMarek Vasut DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS), 102*19b1a8b7SMarek Vasut DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS), 103*19b1a8b7SMarek Vasut DEF_MOD("scifa2", 202, R8A7794_CLK_MP), 104*19b1a8b7SMarek Vasut DEF_MOD("scifa1", 203, R8A7794_CLK_MP), 105*19b1a8b7SMarek Vasut DEF_MOD("scifa0", 204, R8A7794_CLK_MP), 106*19b1a8b7SMarek Vasut DEF_MOD("msiof2", 205, R8A7794_CLK_MP), 107*19b1a8b7SMarek Vasut DEF_MOD("scifb0", 206, R8A7794_CLK_MP), 108*19b1a8b7SMarek Vasut DEF_MOD("scifb1", 207, R8A7794_CLK_MP), 109*19b1a8b7SMarek Vasut DEF_MOD("msiof1", 208, R8A7794_CLK_MP), 110*19b1a8b7SMarek Vasut DEF_MOD("scifb2", 216, R8A7794_CLK_MP), 111*19b1a8b7SMarek Vasut DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS), 112*19b1a8b7SMarek Vasut DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS), 113*19b1a8b7SMarek Vasut DEF_MOD("tpu0", 304, R8A7794_CLK_CP), 114*19b1a8b7SMarek Vasut DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3), 115*19b1a8b7SMarek Vasut DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2), 116*19b1a8b7SMarek Vasut DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0), 117*19b1a8b7SMarek Vasut DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0), 118*19b1a8b7SMarek Vasut DEF_MOD("iic0", 318, R8A7794_CLK_HP), 119*19b1a8b7SMarek Vasut DEF_MOD("iic1", 323, R8A7794_CLK_HP), 120*19b1a8b7SMarek Vasut DEF_MOD("cmt1", 329, R8A7794_CLK_R), 121*19b1a8b7SMarek Vasut DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP), 122*19b1a8b7SMarek Vasut DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP), 123*19b1a8b7SMarek Vasut DEF_MOD("irqc", 407, R8A7794_CLK_CP), 124*19b1a8b7SMarek Vasut DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS), 125*19b1a8b7SMarek Vasut DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP), 126*19b1a8b7SMarek Vasut DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP), 127*19b1a8b7SMarek Vasut DEF_MOD("pwm", 523, R8A7794_CLK_P), 128*19b1a8b7SMarek Vasut DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP), 129*19b1a8b7SMarek Vasut DEF_MOD("usbhs", 704, R8A7794_CLK_HP), 130*19b1a8b7SMarek Vasut DEF_MOD("hscif2", 713, R8A7794_CLK_ZS), 131*19b1a8b7SMarek Vasut DEF_MOD("scif5", 714, R8A7794_CLK_P), 132*19b1a8b7SMarek Vasut DEF_MOD("scif4", 715, R8A7794_CLK_P), 133*19b1a8b7SMarek Vasut DEF_MOD("hscif1", 716, R8A7794_CLK_ZS), 134*19b1a8b7SMarek Vasut DEF_MOD("hscif0", 717, R8A7794_CLK_ZS), 135*19b1a8b7SMarek Vasut DEF_MOD("scif3", 718, R8A7794_CLK_P), 136*19b1a8b7SMarek Vasut DEF_MOD("scif2", 719, R8A7794_CLK_P), 137*19b1a8b7SMarek Vasut DEF_MOD("scif1", 720, R8A7794_CLK_P), 138*19b1a8b7SMarek Vasut DEF_MOD("scif0", 721, R8A7794_CLK_P), 139*19b1a8b7SMarek Vasut DEF_MOD("du1", 723, R8A7794_CLK_ZX), 140*19b1a8b7SMarek Vasut DEF_MOD("du0", 724, R8A7794_CLK_ZX), 141*19b1a8b7SMarek Vasut DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX), 142*19b1a8b7SMarek Vasut DEF_MOD("mlb", 802, R8A7794_CLK_HP), 143*19b1a8b7SMarek Vasut DEF_MOD("vin1", 810, R8A7794_CLK_ZG), 144*19b1a8b7SMarek Vasut DEF_MOD("vin0", 811, R8A7794_CLK_ZG), 145*19b1a8b7SMarek Vasut DEF_MOD("etheravb", 812, R8A7794_CLK_HP), 146*19b1a8b7SMarek Vasut DEF_MOD("ether", 813, R8A7794_CLK_P), 147*19b1a8b7SMarek Vasut DEF_MOD("gyro-adc", 901, R8A7794_CLK_P), 148*19b1a8b7SMarek Vasut DEF_MOD("gpio6", 905, R8A7794_CLK_CP), 149*19b1a8b7SMarek Vasut DEF_MOD("gpio5", 907, R8A7794_CLK_CP), 150*19b1a8b7SMarek Vasut DEF_MOD("gpio4", 908, R8A7794_CLK_CP), 151*19b1a8b7SMarek Vasut DEF_MOD("gpio3", 909, R8A7794_CLK_CP), 152*19b1a8b7SMarek Vasut DEF_MOD("gpio2", 910, R8A7794_CLK_CP), 153*19b1a8b7SMarek Vasut DEF_MOD("gpio1", 911, R8A7794_CLK_CP), 154*19b1a8b7SMarek Vasut DEF_MOD("gpio0", 912, R8A7794_CLK_CP), 155*19b1a8b7SMarek Vasut DEF_MOD("can1", 915, R8A7794_CLK_P), 156*19b1a8b7SMarek Vasut DEF_MOD("can0", 916, R8A7794_CLK_P), 157*19b1a8b7SMarek Vasut DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI), 158*19b1a8b7SMarek Vasut DEF_MOD("i2c5", 925, R8A7794_CLK_HP), 159*19b1a8b7SMarek Vasut DEF_MOD("i2c4", 927, R8A7794_CLK_HP), 160*19b1a8b7SMarek Vasut DEF_MOD("i2c3", 928, R8A7794_CLK_HP), 161*19b1a8b7SMarek Vasut DEF_MOD("i2c2", 929, R8A7794_CLK_HP), 162*19b1a8b7SMarek Vasut DEF_MOD("i2c1", 930, R8A7794_CLK_HP), 163*19b1a8b7SMarek Vasut DEF_MOD("i2c0", 931, R8A7794_CLK_HP), 164*19b1a8b7SMarek Vasut DEF_MOD("ssi-all", 1005, R8A7794_CLK_P), 165*19b1a8b7SMarek Vasut DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 166*19b1a8b7SMarek Vasut DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 167*19b1a8b7SMarek Vasut DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 168*19b1a8b7SMarek Vasut DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 169*19b1a8b7SMarek Vasut DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 170*19b1a8b7SMarek Vasut DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 171*19b1a8b7SMarek Vasut DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 172*19b1a8b7SMarek Vasut DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 173*19b1a8b7SMarek Vasut DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 174*19b1a8b7SMarek Vasut DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 175*19b1a8b7SMarek Vasut DEF_MOD("scu-all", 1017, R8A7794_CLK_P), 176*19b1a8b7SMarek Vasut DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 177*19b1a8b7SMarek Vasut DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 178*19b1a8b7SMarek Vasut DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 179*19b1a8b7SMarek Vasut DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 180*19b1a8b7SMarek Vasut DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 181*19b1a8b7SMarek Vasut DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 182*19b1a8b7SMarek Vasut DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 183*19b1a8b7SMarek Vasut DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 184*19b1a8b7SMarek Vasut DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 185*19b1a8b7SMarek Vasut DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 186*19b1a8b7SMarek Vasut DEF_MOD("scifa3", 1106, R8A7794_CLK_MP), 187*19b1a8b7SMarek Vasut DEF_MOD("scifa4", 1107, R8A7794_CLK_MP), 188*19b1a8b7SMarek Vasut DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), 189*19b1a8b7SMarek Vasut }; 190*19b1a8b7SMarek Vasut 191*19b1a8b7SMarek Vasut static const unsigned int r8a7794_crit_mod_clks[] __initconst = { 192*19b1a8b7SMarek Vasut MOD_CLK_ID(408), /* INTC-SYS (GIC) */ 193*19b1a8b7SMarek Vasut }; 194*19b1a8b7SMarek Vasut 195*19b1a8b7SMarek Vasut /* 196*19b1a8b7SMarek Vasut * CPG Clock Data 197*19b1a8b7SMarek Vasut */ 198*19b1a8b7SMarek Vasut 199*19b1a8b7SMarek Vasut /* 200*19b1a8b7SMarek Vasut * MD EXTAL PLL0 PLL1 PLL3 201*19b1a8b7SMarek Vasut * 14 13 19 (MHz) *1 *2 202*19b1a8b7SMarek Vasut *--------------------------------------------------- 203*19b1a8b7SMarek Vasut * 0 0 1 15 x200/3 x208/2 x88 204*19b1a8b7SMarek Vasut * 0 1 1 20 x150/3 x156/2 x66 205*19b1a8b7SMarek Vasut * 1 0 1 26 / 2 x230/3 x240/2 x102 206*19b1a8b7SMarek Vasut * 1 1 1 30 / 2 x200/3 x208/2 x88 207*19b1a8b7SMarek Vasut * 208*19b1a8b7SMarek Vasut * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3) 209*19b1a8b7SMarek Vasut * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2) 210*19b1a8b7SMarek Vasut */ 211*19b1a8b7SMarek Vasut #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 212*19b1a8b7SMarek Vasut (((md) & BIT(13)) >> 13)) 213*19b1a8b7SMarek Vasut static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = { 214*19b1a8b7SMarek Vasut { 1, 208, 88, 200 }, 215*19b1a8b7SMarek Vasut { 1, 156, 66, 150 }, 216*19b1a8b7SMarek Vasut { 2, 240, 102, 230 }, 217*19b1a8b7SMarek Vasut { 2, 208, 88, 200 }, 218*19b1a8b7SMarek Vasut }; 219*19b1a8b7SMarek Vasut 220*19b1a8b7SMarek Vasut static const struct mstp_stop_table r8a7794_mstp_table[] = { 221*19b1a8b7SMarek Vasut { 0x00440801, 0x400000, 0x00440801, 0x0 }, 222*19b1a8b7SMarek Vasut { 0x936899DA, 0x0, 0x936899DA, 0x0 }, 223*19b1a8b7SMarek Vasut { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 }, 224*19b1a8b7SMarek Vasut { 0xE084D810, 0x0, 0xE084D810, 0x0 }, 225*19b1a8b7SMarek Vasut { 0x800001C4, 0x180, 0x800001C4, 0x0 }, 226*19b1a8b7SMarek Vasut { 0x40C00044, 0x0, 0x40C00044, 0x0 }, 227*19b1a8b7SMarek Vasut { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ 228*19b1a8b7SMarek Vasut { 0x013FE618, 0x80000, 0x013FE618, 0x0 }, 229*19b1a8b7SMarek Vasut { 0x40803C05, 0x0, 0x40803C05, 0x0 }, 230*19b1a8b7SMarek Vasut { 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 }, 231*19b1a8b7SMarek Vasut { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, 232*19b1a8b7SMarek Vasut { 0x000001C0, 0x0, 0x000001C0, 0x0 }, 233*19b1a8b7SMarek Vasut }; 234*19b1a8b7SMarek Vasut 235*19b1a8b7SMarek Vasut static const void *r8a7794_get_pll_config(const u32 cpg_mode) 236*19b1a8b7SMarek Vasut { 237*19b1a8b7SMarek Vasut return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 238*19b1a8b7SMarek Vasut } 239*19b1a8b7SMarek Vasut 240*19b1a8b7SMarek Vasut static const struct cpg_mssr_info r8a7794_cpg_mssr_info = { 241*19b1a8b7SMarek Vasut .core_clk = r8a7794_core_clks, 242*19b1a8b7SMarek Vasut .core_clk_size = ARRAY_SIZE(r8a7794_core_clks), 243*19b1a8b7SMarek Vasut .mod_clk = r8a7794_mod_clks, 244*19b1a8b7SMarek Vasut .mod_clk_size = ARRAY_SIZE(r8a7794_mod_clks), 245*19b1a8b7SMarek Vasut .mstp_table = r8a7794_mstp_table, 246*19b1a8b7SMarek Vasut .mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table), 247*19b1a8b7SMarek Vasut .reset_node = "renesas,r8a7794-rst", 248*19b1a8b7SMarek Vasut .extal_usb_node = "usb_extal", 249*19b1a8b7SMarek Vasut .mod_clk_base = MOD_CLK_BASE, 250*19b1a8b7SMarek Vasut .clk_extal_id = CLK_EXTAL, 251*19b1a8b7SMarek Vasut .clk_extal_usb_id = CLK_USB_EXTAL, 252*19b1a8b7SMarek Vasut .pll0_div = 2, 253*19b1a8b7SMarek Vasut .get_pll_config = r8a7794_get_pll_config, 254*19b1a8b7SMarek Vasut }; 255*19b1a8b7SMarek Vasut 256*19b1a8b7SMarek Vasut static const struct udevice_id r8a7794_clk_ids[] = { 257*19b1a8b7SMarek Vasut { 258*19b1a8b7SMarek Vasut .compatible = "renesas,r8a7794-cpg-mssr", 259*19b1a8b7SMarek Vasut .data = (ulong)&r8a7794_cpg_mssr_info 260*19b1a8b7SMarek Vasut }, 261*19b1a8b7SMarek Vasut { 262*19b1a8b7SMarek Vasut .compatible = "renesas,r8a7793-cpg-mssr", 263*19b1a8b7SMarek Vasut .data = (ulong)&r8a7794_cpg_mssr_info 264*19b1a8b7SMarek Vasut }, 265*19b1a8b7SMarek Vasut { } 266*19b1a8b7SMarek Vasut }; 267*19b1a8b7SMarek Vasut 268*19b1a8b7SMarek Vasut U_BOOT_DRIVER(clk_r8a7794) = { 269*19b1a8b7SMarek Vasut .name = "clk_r8a7794", 270*19b1a8b7SMarek Vasut .id = UCLASS_CLK, 271*19b1a8b7SMarek Vasut .of_match = r8a7794_clk_ids, 272*19b1a8b7SMarek Vasut .priv_auto_alloc_size = sizeof(struct gen2_clk_priv), 273*19b1a8b7SMarek Vasut .ops = &gen2_clk_ops, 274*19b1a8b7SMarek Vasut .probe = gen2_clk_probe, 275*19b1a8b7SMarek Vasut .remove = gen2_clk_remove, 276*19b1a8b7SMarek Vasut }; 277