119b1a8b7SMarek Vasut /* 219b1a8b7SMarek Vasut * r8a7794 Clock Pulse Generator / Module Standby and Software Reset 319b1a8b7SMarek Vasut * 419b1a8b7SMarek Vasut * Copyright (C) 2017 Glider bvba 519b1a8b7SMarek Vasut * 619b1a8b7SMarek Vasut * Based on clk-rcar-gen2.c 719b1a8b7SMarek Vasut * 819b1a8b7SMarek Vasut * Copyright (C) 2013 Ideas On Board SPRL 919b1a8b7SMarek Vasut * 1019b1a8b7SMarek Vasut * This program is free software; you can redistribute it and/or modify 1119b1a8b7SMarek Vasut * it under the terms of the GNU General Public License as published by 1219b1a8b7SMarek Vasut * the Free Software Foundation; version 2 of the License. 1319b1a8b7SMarek Vasut */ 1419b1a8b7SMarek Vasut 1519b1a8b7SMarek Vasut #include <common.h> 1619b1a8b7SMarek Vasut #include <clk-uclass.h> 1719b1a8b7SMarek Vasut #include <dm.h> 1819b1a8b7SMarek Vasut 1919b1a8b7SMarek Vasut #include <dt-bindings/clock/r8a7794-cpg-mssr.h> 2019b1a8b7SMarek Vasut 2119b1a8b7SMarek Vasut #include "renesas-cpg-mssr.h" 2219b1a8b7SMarek Vasut #include "rcar-gen2-cpg.h" 2319b1a8b7SMarek Vasut 2419b1a8b7SMarek Vasut enum clk_ids { 2519b1a8b7SMarek Vasut /* Core Clock Outputs exported to DT */ 2619b1a8b7SMarek Vasut LAST_DT_CORE_CLK = R8A7794_CLK_OSC, 2719b1a8b7SMarek Vasut 2819b1a8b7SMarek Vasut /* External Input Clocks */ 2919b1a8b7SMarek Vasut CLK_EXTAL, 3019b1a8b7SMarek Vasut CLK_USB_EXTAL, 3119b1a8b7SMarek Vasut 3219b1a8b7SMarek Vasut /* Internal Core Clocks */ 3319b1a8b7SMarek Vasut CLK_MAIN, 3419b1a8b7SMarek Vasut CLK_PLL0, 3519b1a8b7SMarek Vasut CLK_PLL1, 3619b1a8b7SMarek Vasut CLK_PLL3, 3719b1a8b7SMarek Vasut CLK_PLL1_DIV2, 3819b1a8b7SMarek Vasut 3919b1a8b7SMarek Vasut /* Module Clocks */ 4019b1a8b7SMarek Vasut MOD_CLK_BASE 4119b1a8b7SMarek Vasut }; 4219b1a8b7SMarek Vasut 43*010bbe73SMarek Vasut static const struct cpg_core_clk r8a7794_core_clks[] = { 4419b1a8b7SMarek Vasut /* External Clock Inputs */ 4519b1a8b7SMarek Vasut DEF_INPUT("extal", CLK_EXTAL), 4619b1a8b7SMarek Vasut DEF_INPUT("usb_extal", CLK_USB_EXTAL), 4719b1a8b7SMarek Vasut 4819b1a8b7SMarek Vasut /* Internal Core Clocks */ 4919b1a8b7SMarek Vasut DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 5019b1a8b7SMarek Vasut DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 5119b1a8b7SMarek Vasut DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 5219b1a8b7SMarek Vasut DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), 5319b1a8b7SMarek Vasut 5419b1a8b7SMarek Vasut DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 5519b1a8b7SMarek Vasut 5619b1a8b7SMarek Vasut /* Core Clock Outputs */ 5719b1a8b7SMarek Vasut DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), 5819b1a8b7SMarek Vasut DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 5919b1a8b7SMarek Vasut DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 6019b1a8b7SMarek Vasut DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 6119b1a8b7SMarek Vasut DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 6219b1a8b7SMarek Vasut DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), 6319b1a8b7SMarek Vasut 6419b1a8b7SMarek Vasut DEF_FIXED("z2", R8A7794_CLK_Z2, CLK_PLL0, 1, 1), 6519b1a8b7SMarek Vasut DEF_FIXED("zg", R8A7794_CLK_ZG, CLK_PLL1, 6, 1), 6619b1a8b7SMarek Vasut DEF_FIXED("zx", R8A7794_CLK_ZX, CLK_PLL1, 3, 1), 6719b1a8b7SMarek Vasut DEF_FIXED("zs", R8A7794_CLK_ZS, CLK_PLL1, 6, 1), 6819b1a8b7SMarek Vasut DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1), 6919b1a8b7SMarek Vasut DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1), 7019b1a8b7SMarek Vasut DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1), 7119b1a8b7SMarek Vasut DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1), 7219b1a8b7SMarek Vasut DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1), 7319b1a8b7SMarek Vasut DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1), 7419b1a8b7SMarek Vasut DEF_FIXED("m2", R8A7794_CLK_M2, CLK_PLL1, 8, 1), 7519b1a8b7SMarek Vasut DEF_FIXED("zb3", R8A7794_CLK_ZB3, CLK_PLL3, 4, 1), 7619b1a8b7SMarek Vasut DEF_FIXED("zb3d2", R8A7794_CLK_ZB3D2, CLK_PLL3, 8, 1), 7719b1a8b7SMarek Vasut DEF_FIXED("ddr", R8A7794_CLK_DDR, CLK_PLL3, 8, 1), 7819b1a8b7SMarek Vasut DEF_FIXED("mp", R8A7794_CLK_MP, CLK_PLL1_DIV2, 15, 1), 7919b1a8b7SMarek Vasut DEF_FIXED("cpex", R8A7794_CLK_CPEX, CLK_EXTAL, 2, 1), 8019b1a8b7SMarek Vasut DEF_FIXED("r", R8A7794_CLK_R, CLK_PLL1, 49152, 1), 8119b1a8b7SMarek Vasut DEF_FIXED("osc", R8A7794_CLK_OSC, CLK_PLL1, 12288, 1), 8219b1a8b7SMarek Vasut 8319b1a8b7SMarek Vasut DEF_DIV6P1("sd2", R8A7794_CLK_SD2, CLK_PLL1_DIV2, 0x078), 8419b1a8b7SMarek Vasut DEF_DIV6P1("sd3", R8A7794_CLK_SD3, CLK_PLL1_DIV2, 0x26c), 8519b1a8b7SMarek Vasut DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), 8619b1a8b7SMarek Vasut }; 8719b1a8b7SMarek Vasut 88*010bbe73SMarek Vasut static const struct mssr_mod_clk r8a7794_mod_clks[] = { 8919b1a8b7SMarek Vasut DEF_MOD("msiof0", 0, R8A7794_CLK_MP), 9019b1a8b7SMarek Vasut DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), 9119b1a8b7SMarek Vasut DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), 9219b1a8b7SMarek Vasut DEF_MOD("jpu", 106, R8A7794_CLK_M2), 9319b1a8b7SMarek Vasut DEF_MOD("tmu1", 111, R8A7794_CLK_P), 9419b1a8b7SMarek Vasut DEF_MOD("3dg", 112, R8A7794_CLK_ZG), 9519b1a8b7SMarek Vasut DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS), 9619b1a8b7SMarek Vasut DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS), 9719b1a8b7SMarek Vasut DEF_MOD("tmu3", 121, R8A7794_CLK_P), 9819b1a8b7SMarek Vasut DEF_MOD("tmu2", 122, R8A7794_CLK_P), 9919b1a8b7SMarek Vasut DEF_MOD("cmt0", 124, R8A7794_CLK_R), 10019b1a8b7SMarek Vasut DEF_MOD("tmu0", 125, R8A7794_CLK_CP), 10119b1a8b7SMarek Vasut DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS), 10219b1a8b7SMarek Vasut DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS), 10319b1a8b7SMarek Vasut DEF_MOD("scifa2", 202, R8A7794_CLK_MP), 10419b1a8b7SMarek Vasut DEF_MOD("scifa1", 203, R8A7794_CLK_MP), 10519b1a8b7SMarek Vasut DEF_MOD("scifa0", 204, R8A7794_CLK_MP), 10619b1a8b7SMarek Vasut DEF_MOD("msiof2", 205, R8A7794_CLK_MP), 10719b1a8b7SMarek Vasut DEF_MOD("scifb0", 206, R8A7794_CLK_MP), 10819b1a8b7SMarek Vasut DEF_MOD("scifb1", 207, R8A7794_CLK_MP), 10919b1a8b7SMarek Vasut DEF_MOD("msiof1", 208, R8A7794_CLK_MP), 11019b1a8b7SMarek Vasut DEF_MOD("scifb2", 216, R8A7794_CLK_MP), 11119b1a8b7SMarek Vasut DEF_MOD("sys-dmac1", 218, R8A7794_CLK_ZS), 11219b1a8b7SMarek Vasut DEF_MOD("sys-dmac0", 219, R8A7794_CLK_ZS), 11319b1a8b7SMarek Vasut DEF_MOD("tpu0", 304, R8A7794_CLK_CP), 11419b1a8b7SMarek Vasut DEF_MOD("sdhi3", 311, R8A7794_CLK_SD3), 11519b1a8b7SMarek Vasut DEF_MOD("sdhi2", 312, R8A7794_CLK_SD2), 11619b1a8b7SMarek Vasut DEF_MOD("sdhi0", 314, R8A7794_CLK_SD0), 11719b1a8b7SMarek Vasut DEF_MOD("mmcif0", 315, R8A7794_CLK_MMC0), 11819b1a8b7SMarek Vasut DEF_MOD("iic0", 318, R8A7794_CLK_HP), 11919b1a8b7SMarek Vasut DEF_MOD("iic1", 323, R8A7794_CLK_HP), 12019b1a8b7SMarek Vasut DEF_MOD("cmt1", 329, R8A7794_CLK_R), 12119b1a8b7SMarek Vasut DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP), 12219b1a8b7SMarek Vasut DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP), 12319b1a8b7SMarek Vasut DEF_MOD("irqc", 407, R8A7794_CLK_CP), 12419b1a8b7SMarek Vasut DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS), 12519b1a8b7SMarek Vasut DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP), 12619b1a8b7SMarek Vasut DEF_MOD("adsp_mod", 506, R8A7794_CLK_ADSP), 12719b1a8b7SMarek Vasut DEF_MOD("pwm", 523, R8A7794_CLK_P), 12819b1a8b7SMarek Vasut DEF_MOD("usb-ehci", 703, R8A7794_CLK_MP), 12919b1a8b7SMarek Vasut DEF_MOD("usbhs", 704, R8A7794_CLK_HP), 13019b1a8b7SMarek Vasut DEF_MOD("hscif2", 713, R8A7794_CLK_ZS), 13119b1a8b7SMarek Vasut DEF_MOD("scif5", 714, R8A7794_CLK_P), 13219b1a8b7SMarek Vasut DEF_MOD("scif4", 715, R8A7794_CLK_P), 13319b1a8b7SMarek Vasut DEF_MOD("hscif1", 716, R8A7794_CLK_ZS), 13419b1a8b7SMarek Vasut DEF_MOD("hscif0", 717, R8A7794_CLK_ZS), 13519b1a8b7SMarek Vasut DEF_MOD("scif3", 718, R8A7794_CLK_P), 13619b1a8b7SMarek Vasut DEF_MOD("scif2", 719, R8A7794_CLK_P), 13719b1a8b7SMarek Vasut DEF_MOD("scif1", 720, R8A7794_CLK_P), 13819b1a8b7SMarek Vasut DEF_MOD("scif0", 721, R8A7794_CLK_P), 13919b1a8b7SMarek Vasut DEF_MOD("du1", 723, R8A7794_CLK_ZX), 14019b1a8b7SMarek Vasut DEF_MOD("du0", 724, R8A7794_CLK_ZX), 14119b1a8b7SMarek Vasut DEF_MOD("ipmmu-sgx", 800, R8A7794_CLK_ZX), 14219b1a8b7SMarek Vasut DEF_MOD("mlb", 802, R8A7794_CLK_HP), 14319b1a8b7SMarek Vasut DEF_MOD("vin1", 810, R8A7794_CLK_ZG), 14419b1a8b7SMarek Vasut DEF_MOD("vin0", 811, R8A7794_CLK_ZG), 14519b1a8b7SMarek Vasut DEF_MOD("etheravb", 812, R8A7794_CLK_HP), 14619b1a8b7SMarek Vasut DEF_MOD("ether", 813, R8A7794_CLK_P), 14719b1a8b7SMarek Vasut DEF_MOD("gyro-adc", 901, R8A7794_CLK_P), 14819b1a8b7SMarek Vasut DEF_MOD("gpio6", 905, R8A7794_CLK_CP), 14919b1a8b7SMarek Vasut DEF_MOD("gpio5", 907, R8A7794_CLK_CP), 15019b1a8b7SMarek Vasut DEF_MOD("gpio4", 908, R8A7794_CLK_CP), 15119b1a8b7SMarek Vasut DEF_MOD("gpio3", 909, R8A7794_CLK_CP), 15219b1a8b7SMarek Vasut DEF_MOD("gpio2", 910, R8A7794_CLK_CP), 15319b1a8b7SMarek Vasut DEF_MOD("gpio1", 911, R8A7794_CLK_CP), 15419b1a8b7SMarek Vasut DEF_MOD("gpio0", 912, R8A7794_CLK_CP), 15519b1a8b7SMarek Vasut DEF_MOD("can1", 915, R8A7794_CLK_P), 15619b1a8b7SMarek Vasut DEF_MOD("can0", 916, R8A7794_CLK_P), 15719b1a8b7SMarek Vasut DEF_MOD("qspi_mod", 917, R8A7794_CLK_QSPI), 15819b1a8b7SMarek Vasut DEF_MOD("i2c5", 925, R8A7794_CLK_HP), 15919b1a8b7SMarek Vasut DEF_MOD("i2c4", 927, R8A7794_CLK_HP), 16019b1a8b7SMarek Vasut DEF_MOD("i2c3", 928, R8A7794_CLK_HP), 16119b1a8b7SMarek Vasut DEF_MOD("i2c2", 929, R8A7794_CLK_HP), 16219b1a8b7SMarek Vasut DEF_MOD("i2c1", 930, R8A7794_CLK_HP), 16319b1a8b7SMarek Vasut DEF_MOD("i2c0", 931, R8A7794_CLK_HP), 16419b1a8b7SMarek Vasut DEF_MOD("ssi-all", 1005, R8A7794_CLK_P), 16519b1a8b7SMarek Vasut DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 16619b1a8b7SMarek Vasut DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 16719b1a8b7SMarek Vasut DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 16819b1a8b7SMarek Vasut DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 16919b1a8b7SMarek Vasut DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 17019b1a8b7SMarek Vasut DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 17119b1a8b7SMarek Vasut DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 17219b1a8b7SMarek Vasut DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 17319b1a8b7SMarek Vasut DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 17419b1a8b7SMarek Vasut DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 17519b1a8b7SMarek Vasut DEF_MOD("scu-all", 1017, R8A7794_CLK_P), 17619b1a8b7SMarek Vasut DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 17719b1a8b7SMarek Vasut DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 17819b1a8b7SMarek Vasut DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 17919b1a8b7SMarek Vasut DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 18019b1a8b7SMarek Vasut DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 18119b1a8b7SMarek Vasut DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 18219b1a8b7SMarek Vasut DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 18319b1a8b7SMarek Vasut DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 18419b1a8b7SMarek Vasut DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 18519b1a8b7SMarek Vasut DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 18619b1a8b7SMarek Vasut DEF_MOD("scifa3", 1106, R8A7794_CLK_MP), 18719b1a8b7SMarek Vasut DEF_MOD("scifa4", 1107, R8A7794_CLK_MP), 18819b1a8b7SMarek Vasut DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), 18919b1a8b7SMarek Vasut }; 19019b1a8b7SMarek Vasut 19119b1a8b7SMarek Vasut /* 19219b1a8b7SMarek Vasut * CPG Clock Data 19319b1a8b7SMarek Vasut */ 19419b1a8b7SMarek Vasut 19519b1a8b7SMarek Vasut /* 19619b1a8b7SMarek Vasut * MD EXTAL PLL0 PLL1 PLL3 19719b1a8b7SMarek Vasut * 14 13 19 (MHz) *1 *2 19819b1a8b7SMarek Vasut *--------------------------------------------------- 19919b1a8b7SMarek Vasut * 0 0 1 15 x200/3 x208/2 x88 20019b1a8b7SMarek Vasut * 0 1 1 20 x150/3 x156/2 x66 20119b1a8b7SMarek Vasut * 1 0 1 26 / 2 x230/3 x240/2 x102 20219b1a8b7SMarek Vasut * 1 1 1 30 / 2 x200/3 x208/2 x88 20319b1a8b7SMarek Vasut * 20419b1a8b7SMarek Vasut * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3) 20519b1a8b7SMarek Vasut * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2) 20619b1a8b7SMarek Vasut */ 20719b1a8b7SMarek Vasut #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ 20819b1a8b7SMarek Vasut (((md) & BIT(13)) >> 13)) 209*010bbe73SMarek Vasut static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = { 21019b1a8b7SMarek Vasut { 1, 208, 88, 200 }, 21119b1a8b7SMarek Vasut { 1, 156, 66, 150 }, 21219b1a8b7SMarek Vasut { 2, 240, 102, 230 }, 21319b1a8b7SMarek Vasut { 2, 208, 88, 200 }, 21419b1a8b7SMarek Vasut }; 21519b1a8b7SMarek Vasut 21619b1a8b7SMarek Vasut static const struct mstp_stop_table r8a7794_mstp_table[] = { 21719b1a8b7SMarek Vasut { 0x00440801, 0x400000, 0x00440801, 0x0 }, 21819b1a8b7SMarek Vasut { 0x936899DA, 0x0, 0x936899DA, 0x0 }, 21919b1a8b7SMarek Vasut { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 }, 22019b1a8b7SMarek Vasut { 0xE084D810, 0x0, 0xE084D810, 0x0 }, 22119b1a8b7SMarek Vasut { 0x800001C4, 0x180, 0x800001C4, 0x0 }, 22219b1a8b7SMarek Vasut { 0x40C00044, 0x0, 0x40C00044, 0x0 }, 22319b1a8b7SMarek Vasut { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ 22419b1a8b7SMarek Vasut { 0x013FE618, 0x80000, 0x013FE618, 0x0 }, 22519b1a8b7SMarek Vasut { 0x40803C05, 0x0, 0x40803C05, 0x0 }, 22619b1a8b7SMarek Vasut { 0xFB879FEE, 0x0, 0xFB879FEE, 0x0 }, 22719b1a8b7SMarek Vasut { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, 22819b1a8b7SMarek Vasut { 0x000001C0, 0x0, 0x000001C0, 0x0 }, 22919b1a8b7SMarek Vasut }; 23019b1a8b7SMarek Vasut 23119b1a8b7SMarek Vasut static const void *r8a7794_get_pll_config(const u32 cpg_mode) 23219b1a8b7SMarek Vasut { 23319b1a8b7SMarek Vasut return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 23419b1a8b7SMarek Vasut } 23519b1a8b7SMarek Vasut 23619b1a8b7SMarek Vasut static const struct cpg_mssr_info r8a7794_cpg_mssr_info = { 23719b1a8b7SMarek Vasut .core_clk = r8a7794_core_clks, 23819b1a8b7SMarek Vasut .core_clk_size = ARRAY_SIZE(r8a7794_core_clks), 23919b1a8b7SMarek Vasut .mod_clk = r8a7794_mod_clks, 24019b1a8b7SMarek Vasut .mod_clk_size = ARRAY_SIZE(r8a7794_mod_clks), 24119b1a8b7SMarek Vasut .mstp_table = r8a7794_mstp_table, 24219b1a8b7SMarek Vasut .mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table), 24319b1a8b7SMarek Vasut .reset_node = "renesas,r8a7794-rst", 24419b1a8b7SMarek Vasut .extal_usb_node = "usb_extal", 24519b1a8b7SMarek Vasut .mod_clk_base = MOD_CLK_BASE, 24619b1a8b7SMarek Vasut .clk_extal_id = CLK_EXTAL, 24719b1a8b7SMarek Vasut .clk_extal_usb_id = CLK_USB_EXTAL, 24819b1a8b7SMarek Vasut .pll0_div = 2, 24919b1a8b7SMarek Vasut .get_pll_config = r8a7794_get_pll_config, 25019b1a8b7SMarek Vasut }; 25119b1a8b7SMarek Vasut 25219b1a8b7SMarek Vasut static const struct udevice_id r8a7794_clk_ids[] = { 25319b1a8b7SMarek Vasut { 25419b1a8b7SMarek Vasut .compatible = "renesas,r8a7794-cpg-mssr", 25519b1a8b7SMarek Vasut .data = (ulong)&r8a7794_cpg_mssr_info 25619b1a8b7SMarek Vasut }, 25719b1a8b7SMarek Vasut { 25819b1a8b7SMarek Vasut .compatible = "renesas,r8a7793-cpg-mssr", 25919b1a8b7SMarek Vasut .data = (ulong)&r8a7794_cpg_mssr_info 26019b1a8b7SMarek Vasut }, 26119b1a8b7SMarek Vasut { } 26219b1a8b7SMarek Vasut }; 26319b1a8b7SMarek Vasut 26419b1a8b7SMarek Vasut U_BOOT_DRIVER(clk_r8a7794) = { 26519b1a8b7SMarek Vasut .name = "clk_r8a7794", 26619b1a8b7SMarek Vasut .id = UCLASS_CLK, 26719b1a8b7SMarek Vasut .of_match = r8a7794_clk_ids, 26819b1a8b7SMarek Vasut .priv_auto_alloc_size = sizeof(struct gen2_clk_priv), 26919b1a8b7SMarek Vasut .ops = &gen2_clk_ops, 27019b1a8b7SMarek Vasut .probe = gen2_clk_probe, 27119b1a8b7SMarek Vasut .remove = gen2_clk_remove, 27219b1a8b7SMarek Vasut }; 273