1*67dbebe2SMarek Vasut /* 2*67dbebe2SMarek Vasut * Renesas R8A7791 CPG MSSR driver 3*67dbebe2SMarek Vasut * 4*67dbebe2SMarek Vasut * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 5*67dbebe2SMarek Vasut * 6*67dbebe2SMarek Vasut * Based on the following driver from Linux kernel: 7*67dbebe2SMarek Vasut * r8a7791 Clock Pulse Generator / Module Standby and Software Reset 8*67dbebe2SMarek Vasut * Copyright (C) 2015-2017 Glider bvba 9*67dbebe2SMarek Vasut * Based on clk-rcar-gen2.c 10*67dbebe2SMarek Vasut * Copyright (C) 2013 Ideas On Board SPRL 11*67dbebe2SMarek Vasut * 12*67dbebe2SMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 13*67dbebe2SMarek Vasut */ 14*67dbebe2SMarek Vasut 15*67dbebe2SMarek Vasut #include <common.h> 16*67dbebe2SMarek Vasut #include <clk-uclass.h> 17*67dbebe2SMarek Vasut #include <dm.h> 18*67dbebe2SMarek Vasut 19*67dbebe2SMarek Vasut #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 20*67dbebe2SMarek Vasut 21*67dbebe2SMarek Vasut #include "renesas-cpg-mssr.h" 22*67dbebe2SMarek Vasut #include "rcar-gen2-cpg.h" 23*67dbebe2SMarek Vasut 24*67dbebe2SMarek Vasut enum clk_ids { 25*67dbebe2SMarek Vasut /* Core Clock Outputs exported to DT */ 26*67dbebe2SMarek Vasut LAST_DT_CORE_CLK = R8A7791_CLK_OSC, 27*67dbebe2SMarek Vasut 28*67dbebe2SMarek Vasut /* External Input Clocks */ 29*67dbebe2SMarek Vasut CLK_EXTAL, 30*67dbebe2SMarek Vasut CLK_USB_EXTAL, 31*67dbebe2SMarek Vasut 32*67dbebe2SMarek Vasut /* Internal Core Clocks */ 33*67dbebe2SMarek Vasut CLK_MAIN, 34*67dbebe2SMarek Vasut CLK_PLL0, 35*67dbebe2SMarek Vasut CLK_PLL1, 36*67dbebe2SMarek Vasut CLK_PLL3, 37*67dbebe2SMarek Vasut CLK_PLL1_DIV2, 38*67dbebe2SMarek Vasut 39*67dbebe2SMarek Vasut /* Module Clocks */ 40*67dbebe2SMarek Vasut MOD_CLK_BASE 41*67dbebe2SMarek Vasut }; 42*67dbebe2SMarek Vasut 43*67dbebe2SMarek Vasut static const struct cpg_core_clk r8a7791_core_clks[] = { 44*67dbebe2SMarek Vasut /* External Clock Inputs */ 45*67dbebe2SMarek Vasut DEF_INPUT("extal", CLK_EXTAL), 46*67dbebe2SMarek Vasut DEF_INPUT("usb_extal", CLK_USB_EXTAL), 47*67dbebe2SMarek Vasut 48*67dbebe2SMarek Vasut /* Internal Core Clocks */ 49*67dbebe2SMarek Vasut DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 50*67dbebe2SMarek Vasut DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 51*67dbebe2SMarek Vasut DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 52*67dbebe2SMarek Vasut DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN), 53*67dbebe2SMarek Vasut 54*67dbebe2SMarek Vasut DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 55*67dbebe2SMarek Vasut 56*67dbebe2SMarek Vasut /* Core Clock Outputs */ 57*67dbebe2SMarek Vasut DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0), 58*67dbebe2SMarek Vasut DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), 59*67dbebe2SMarek Vasut DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1), 60*67dbebe2SMarek Vasut DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), 61*67dbebe2SMarek Vasut DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), 62*67dbebe2SMarek Vasut DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), 63*67dbebe2SMarek Vasut DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), 64*67dbebe2SMarek Vasut 65*67dbebe2SMarek Vasut DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1), 66*67dbebe2SMarek Vasut DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1), 67*67dbebe2SMarek Vasut DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1), 68*67dbebe2SMarek Vasut DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1), 69*67dbebe2SMarek Vasut DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1), 70*67dbebe2SMarek Vasut DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1), 71*67dbebe2SMarek Vasut DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1), 72*67dbebe2SMarek Vasut DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1), 73*67dbebe2SMarek Vasut DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1), 74*67dbebe2SMarek Vasut DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1), 75*67dbebe2SMarek Vasut DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1), 76*67dbebe2SMarek Vasut DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1), 77*67dbebe2SMarek Vasut DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1), 78*67dbebe2SMarek Vasut DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1), 79*67dbebe2SMarek Vasut DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1), 80*67dbebe2SMarek Vasut DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1), 81*67dbebe2SMarek Vasut 82*67dbebe2SMarek Vasut DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078), 83*67dbebe2SMarek Vasut DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c), 84*67dbebe2SMarek Vasut DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240), 85*67dbebe2SMarek Vasut DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248), 86*67dbebe2SMarek Vasut DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c), 87*67dbebe2SMarek Vasut }; 88*67dbebe2SMarek Vasut 89*67dbebe2SMarek Vasut static const struct mssr_mod_clk r8a7791_mod_clks[] = { 90*67dbebe2SMarek Vasut DEF_MOD("msiof0", 0, R8A7791_CLK_MP), 91*67dbebe2SMarek Vasut DEF_MOD("vcp0", 101, R8A7791_CLK_ZS), 92*67dbebe2SMarek Vasut DEF_MOD("vpc0", 103, R8A7791_CLK_ZS), 93*67dbebe2SMarek Vasut DEF_MOD("jpu", 106, R8A7791_CLK_M2), 94*67dbebe2SMarek Vasut DEF_MOD("ssp1", 109, R8A7791_CLK_ZS), 95*67dbebe2SMarek Vasut DEF_MOD("tmu1", 111, R8A7791_CLK_P), 96*67dbebe2SMarek Vasut DEF_MOD("3dg", 112, R8A7791_CLK_ZG), 97*67dbebe2SMarek Vasut DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS), 98*67dbebe2SMarek Vasut DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS), 99*67dbebe2SMarek Vasut DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS), 100*67dbebe2SMarek Vasut DEF_MOD("tmu3", 121, R8A7791_CLK_P), 101*67dbebe2SMarek Vasut DEF_MOD("tmu2", 122, R8A7791_CLK_P), 102*67dbebe2SMarek Vasut DEF_MOD("cmt0", 124, R8A7791_CLK_R), 103*67dbebe2SMarek Vasut DEF_MOD("tmu0", 125, R8A7791_CLK_CP), 104*67dbebe2SMarek Vasut DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS), 105*67dbebe2SMarek Vasut DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS), 106*67dbebe2SMarek Vasut DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS), 107*67dbebe2SMarek Vasut DEF_MOD("scifa2", 202, R8A7791_CLK_MP), 108*67dbebe2SMarek Vasut DEF_MOD("scifa1", 203, R8A7791_CLK_MP), 109*67dbebe2SMarek Vasut DEF_MOD("scifa0", 204, R8A7791_CLK_MP), 110*67dbebe2SMarek Vasut DEF_MOD("msiof2", 205, R8A7791_CLK_MP), 111*67dbebe2SMarek Vasut DEF_MOD("scifb0", 206, R8A7791_CLK_MP), 112*67dbebe2SMarek Vasut DEF_MOD("scifb1", 207, R8A7791_CLK_MP), 113*67dbebe2SMarek Vasut DEF_MOD("msiof1", 208, R8A7791_CLK_MP), 114*67dbebe2SMarek Vasut DEF_MOD("scifb2", 216, R8A7791_CLK_MP), 115*67dbebe2SMarek Vasut DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS), 116*67dbebe2SMarek Vasut DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS), 117*67dbebe2SMarek Vasut DEF_MOD("tpu0", 304, R8A7791_CLK_CP), 118*67dbebe2SMarek Vasut DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3), 119*67dbebe2SMarek Vasut DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2), 120*67dbebe2SMarek Vasut DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0), 121*67dbebe2SMarek Vasut DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0), 122*67dbebe2SMarek Vasut DEF_MOD("iic0", 318, R8A7791_CLK_HP), 123*67dbebe2SMarek Vasut DEF_MOD("pciec", 319, R8A7791_CLK_MP), 124*67dbebe2SMarek Vasut DEF_MOD("iic1", 323, R8A7791_CLK_HP), 125*67dbebe2SMarek Vasut DEF_MOD("usb3.0", 328, R8A7791_CLK_MP), 126*67dbebe2SMarek Vasut DEF_MOD("cmt1", 329, R8A7791_CLK_R), 127*67dbebe2SMarek Vasut DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP), 128*67dbebe2SMarek Vasut DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP), 129*67dbebe2SMarek Vasut DEF_MOD("irqc", 407, R8A7791_CLK_CP), 130*67dbebe2SMarek Vasut DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS), 131*67dbebe2SMarek Vasut DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP), 132*67dbebe2SMarek Vasut DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP), 133*67dbebe2SMarek Vasut DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP), 134*67dbebe2SMarek Vasut DEF_MOD("thermal", 522, CLK_EXTAL), 135*67dbebe2SMarek Vasut DEF_MOD("pwm", 523, R8A7791_CLK_P), 136*67dbebe2SMarek Vasut DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP), 137*67dbebe2SMarek Vasut DEF_MOD("usbhs", 704, R8A7791_CLK_HP), 138*67dbebe2SMarek Vasut DEF_MOD("hscif2", 713, R8A7791_CLK_ZS), 139*67dbebe2SMarek Vasut DEF_MOD("scif5", 714, R8A7791_CLK_P), 140*67dbebe2SMarek Vasut DEF_MOD("scif4", 715, R8A7791_CLK_P), 141*67dbebe2SMarek Vasut DEF_MOD("hscif1", 716, R8A7791_CLK_ZS), 142*67dbebe2SMarek Vasut DEF_MOD("hscif0", 717, R8A7791_CLK_ZS), 143*67dbebe2SMarek Vasut DEF_MOD("scif3", 718, R8A7791_CLK_P), 144*67dbebe2SMarek Vasut DEF_MOD("scif2", 719, R8A7791_CLK_P), 145*67dbebe2SMarek Vasut DEF_MOD("scif1", 720, R8A7791_CLK_P), 146*67dbebe2SMarek Vasut DEF_MOD("scif0", 721, R8A7791_CLK_P), 147*67dbebe2SMarek Vasut DEF_MOD("du1", 723, R8A7791_CLK_ZX), 148*67dbebe2SMarek Vasut DEF_MOD("du0", 724, R8A7791_CLK_ZX), 149*67dbebe2SMarek Vasut DEF_MOD("lvds0", 726, R8A7791_CLK_ZX), 150*67dbebe2SMarek Vasut DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX), 151*67dbebe2SMarek Vasut DEF_MOD("mlb", 802, R8A7791_CLK_HP), 152*67dbebe2SMarek Vasut DEF_MOD("vin2", 809, R8A7791_CLK_ZG), 153*67dbebe2SMarek Vasut DEF_MOD("vin1", 810, R8A7791_CLK_ZG), 154*67dbebe2SMarek Vasut DEF_MOD("vin0", 811, R8A7791_CLK_ZG), 155*67dbebe2SMarek Vasut DEF_MOD("etheravb", 812, R8A7791_CLK_HP), 156*67dbebe2SMarek Vasut DEF_MOD("ether", 813, R8A7791_CLK_P), 157*67dbebe2SMarek Vasut DEF_MOD("sata1", 814, R8A7791_CLK_ZS), 158*67dbebe2SMarek Vasut DEF_MOD("sata0", 815, R8A7791_CLK_ZS), 159*67dbebe2SMarek Vasut DEF_MOD("gyro-adc", 901, R8A7791_CLK_P), 160*67dbebe2SMarek Vasut DEF_MOD("gpio7", 904, R8A7791_CLK_CP), 161*67dbebe2SMarek Vasut DEF_MOD("gpio6", 905, R8A7791_CLK_CP), 162*67dbebe2SMarek Vasut DEF_MOD("gpio5", 907, R8A7791_CLK_CP), 163*67dbebe2SMarek Vasut DEF_MOD("gpio4", 908, R8A7791_CLK_CP), 164*67dbebe2SMarek Vasut DEF_MOD("gpio3", 909, R8A7791_CLK_CP), 165*67dbebe2SMarek Vasut DEF_MOD("gpio2", 910, R8A7791_CLK_CP), 166*67dbebe2SMarek Vasut DEF_MOD("gpio1", 911, R8A7791_CLK_CP), 167*67dbebe2SMarek Vasut DEF_MOD("gpio0", 912, R8A7791_CLK_CP), 168*67dbebe2SMarek Vasut DEF_MOD("can1", 915, R8A7791_CLK_P), 169*67dbebe2SMarek Vasut DEF_MOD("can0", 916, R8A7791_CLK_P), 170*67dbebe2SMarek Vasut DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI), 171*67dbebe2SMarek Vasut DEF_MOD("i2c5", 925, R8A7791_CLK_HP), 172*67dbebe2SMarek Vasut DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP), 173*67dbebe2SMarek Vasut DEF_MOD("i2c4", 927, R8A7791_CLK_HP), 174*67dbebe2SMarek Vasut DEF_MOD("i2c3", 928, R8A7791_CLK_HP), 175*67dbebe2SMarek Vasut DEF_MOD("i2c2", 929, R8A7791_CLK_HP), 176*67dbebe2SMarek Vasut DEF_MOD("i2c1", 930, R8A7791_CLK_HP), 177*67dbebe2SMarek Vasut DEF_MOD("i2c0", 931, R8A7791_CLK_HP), 178*67dbebe2SMarek Vasut DEF_MOD("ssi-all", 1005, R8A7791_CLK_P), 179*67dbebe2SMarek Vasut DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 180*67dbebe2SMarek Vasut DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 181*67dbebe2SMarek Vasut DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 182*67dbebe2SMarek Vasut DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 183*67dbebe2SMarek Vasut DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 184*67dbebe2SMarek Vasut DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 185*67dbebe2SMarek Vasut DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 186*67dbebe2SMarek Vasut DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 187*67dbebe2SMarek Vasut DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 188*67dbebe2SMarek Vasut DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 189*67dbebe2SMarek Vasut DEF_MOD("scu-all", 1017, R8A7791_CLK_P), 190*67dbebe2SMarek Vasut DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 191*67dbebe2SMarek Vasut DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 192*67dbebe2SMarek Vasut DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 193*67dbebe2SMarek Vasut DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 194*67dbebe2SMarek Vasut DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 195*67dbebe2SMarek Vasut DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 196*67dbebe2SMarek Vasut DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 197*67dbebe2SMarek Vasut DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 198*67dbebe2SMarek Vasut DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 199*67dbebe2SMarek Vasut DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 200*67dbebe2SMarek Vasut DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 201*67dbebe2SMarek Vasut DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 202*67dbebe2SMarek Vasut DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 203*67dbebe2SMarek Vasut DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 204*67dbebe2SMarek Vasut DEF_MOD("scifa3", 1106, R8A7791_CLK_MP), 205*67dbebe2SMarek Vasut DEF_MOD("scifa4", 1107, R8A7791_CLK_MP), 206*67dbebe2SMarek Vasut DEF_MOD("scifa5", 1108, R8A7791_CLK_MP), 207*67dbebe2SMarek Vasut }; 208*67dbebe2SMarek Vasut 209*67dbebe2SMarek Vasut /* 210*67dbebe2SMarek Vasut * CPG Clock Data 211*67dbebe2SMarek Vasut */ 212*67dbebe2SMarek Vasut 213*67dbebe2SMarek Vasut /* 214*67dbebe2SMarek Vasut * MD EXTAL PLL0 PLL1 PLL3 215*67dbebe2SMarek Vasut * 14 13 19 (MHz) *1 *1 216*67dbebe2SMarek Vasut *--------------------------------------------------- 217*67dbebe2SMarek Vasut * 0 0 0 15 x172/2 x208/2 x106 218*67dbebe2SMarek Vasut * 0 0 1 15 x172/2 x208/2 x88 219*67dbebe2SMarek Vasut * 0 1 0 20 x130/2 x156/2 x80 220*67dbebe2SMarek Vasut * 0 1 1 20 x130/2 x156/2 x66 221*67dbebe2SMarek Vasut * 1 0 0 26 / 2 x200/2 x240/2 x122 222*67dbebe2SMarek Vasut * 1 0 1 26 / 2 x200/2 x240/2 x102 223*67dbebe2SMarek Vasut * 1 1 0 30 / 2 x172/2 x208/2 x106 224*67dbebe2SMarek Vasut * 1 1 1 30 / 2 x172/2 x208/2 x88 225*67dbebe2SMarek Vasut * 226*67dbebe2SMarek Vasut * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2) 227*67dbebe2SMarek Vasut */ 228*67dbebe2SMarek Vasut #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ 229*67dbebe2SMarek Vasut (((md) & BIT(13)) >> 12) | \ 230*67dbebe2SMarek Vasut (((md) & BIT(19)) >> 19)) 231*67dbebe2SMarek Vasut static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { 232*67dbebe2SMarek Vasut { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 }, 233*67dbebe2SMarek Vasut { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 }, 234*67dbebe2SMarek Vasut }; 235*67dbebe2SMarek Vasut 236*67dbebe2SMarek Vasut static const struct mstp_stop_table r8a7791_mstp_table[] = { 237*67dbebe2SMarek Vasut { 0x00640801, 0x400000, 0x00640801, 0x0 }, 238*67dbebe2SMarek Vasut { 0x9B6C9B5A, 0x0, 0x9B6C9B5A, 0x0 }, 239*67dbebe2SMarek Vasut { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 }, 240*67dbebe2SMarek Vasut { 0xF08CD810, 0x0, 0xF08CD810, 0x0 }, 241*67dbebe2SMarek Vasut { 0x800001C4, 0x180, 0x800001C4, 0x0 }, 242*67dbebe2SMarek Vasut { 0x44C00046, 0x0, 0x44C00046, 0x0 }, 243*67dbebe2SMarek Vasut { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */ 244*67dbebe2SMarek Vasut { 0x05BFE618, 0x200000, 0x05BFE618, 0x0 }, 245*67dbebe2SMarek Vasut { 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 }, 246*67dbebe2SMarek Vasut { 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 }, 247*67dbebe2SMarek Vasut { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 }, 248*67dbebe2SMarek Vasut { 0x000001C0, 0x0, 0x000001C0, 0x0 }, 249*67dbebe2SMarek Vasut }; 250*67dbebe2SMarek Vasut 251*67dbebe2SMarek Vasut static const void *r8a7791_get_pll_config(const u32 cpg_mode) 252*67dbebe2SMarek Vasut { 253*67dbebe2SMarek Vasut return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 254*67dbebe2SMarek Vasut } 255*67dbebe2SMarek Vasut 256*67dbebe2SMarek Vasut static const struct cpg_mssr_info r8a7791_cpg_mssr_info = { 257*67dbebe2SMarek Vasut .core_clk = r8a7791_core_clks, 258*67dbebe2SMarek Vasut .core_clk_size = ARRAY_SIZE(r8a7791_core_clks), 259*67dbebe2SMarek Vasut .mod_clk = r8a7791_mod_clks, 260*67dbebe2SMarek Vasut .mod_clk_size = ARRAY_SIZE(r8a7791_mod_clks), 261*67dbebe2SMarek Vasut .mstp_table = r8a7791_mstp_table, 262*67dbebe2SMarek Vasut .mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table), 263*67dbebe2SMarek Vasut .reset_node = "renesas,r8a7791-rst", 264*67dbebe2SMarek Vasut .extal_usb_node = "usb_extal", 265*67dbebe2SMarek Vasut .mod_clk_base = MOD_CLK_BASE, 266*67dbebe2SMarek Vasut .clk_extal_id = CLK_EXTAL, 267*67dbebe2SMarek Vasut .clk_extal_usb_id = CLK_USB_EXTAL, 268*67dbebe2SMarek Vasut .pll0_div = 2, 269*67dbebe2SMarek Vasut .get_pll_config = r8a7791_get_pll_config, 270*67dbebe2SMarek Vasut }; 271*67dbebe2SMarek Vasut 272*67dbebe2SMarek Vasut static const struct udevice_id r8a7791_clk_ids[] = { 273*67dbebe2SMarek Vasut { 274*67dbebe2SMarek Vasut .compatible = "renesas,r8a7791-cpg-mssr", 275*67dbebe2SMarek Vasut .data = (ulong)&r8a7791_cpg_mssr_info 276*67dbebe2SMarek Vasut }, 277*67dbebe2SMarek Vasut { 278*67dbebe2SMarek Vasut .compatible = "renesas,r8a7793-cpg-mssr", 279*67dbebe2SMarek Vasut .data = (ulong)&r8a7791_cpg_mssr_info 280*67dbebe2SMarek Vasut }, 281*67dbebe2SMarek Vasut { } 282*67dbebe2SMarek Vasut }; 283*67dbebe2SMarek Vasut 284*67dbebe2SMarek Vasut U_BOOT_DRIVER(clk_r8a7791) = { 285*67dbebe2SMarek Vasut .name = "clk_r8a7791", 286*67dbebe2SMarek Vasut .id = UCLASS_CLK, 287*67dbebe2SMarek Vasut .of_match = r8a7791_clk_ids, 288*67dbebe2SMarek Vasut .priv_auto_alloc_size = sizeof(struct gen2_clk_priv), 289*67dbebe2SMarek Vasut .ops = &gen2_clk_ops, 290*67dbebe2SMarek Vasut .probe = gen2_clk_probe, 291*67dbebe2SMarek Vasut .remove = gen2_clk_remove, 292*67dbebe2SMarek Vasut }; 293