1 /* 2 * Renesas RCar Gen3 CPG MSSR driver 3 * 4 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * Based on the following driver from Linux kernel: 7 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 8 * 9 * Copyright (C) 2016 Glider bvba 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <clk-uclass.h> 16 #include <dm.h> 17 #include <errno.h> 18 #include <wait_bit.h> 19 #include <asm/io.h> 20 21 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 22 #include <dt-bindings/clock/r8a7796-cpg-mssr.h> 23 #include <dt-bindings/clock/r8a77970-cpg-mssr.h> 24 #include <dt-bindings/clock/r8a77995-cpg-mssr.h> 25 26 #define CPG_RST_MODEMR 0x0060 27 28 #define CPG_PLL0CR 0x00d8 29 #define CPG_PLL2CR 0x002c 30 #define CPG_PLL4CR 0x01f4 31 32 #define CPG_RPC_PREDIV_MASK 0x3 33 #define CPG_RPC_PREDIV_OFFSET 3 34 #define CPG_RPC_POSTDIV_MASK 0x7 35 #define CPG_RPC_POSTDIV_OFFSET 0 36 37 /* 38 * Module Standby and Software Reset register offets. 39 * 40 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 41 * R-Car Gen2, R-Car Gen3, and RZ/G1. 42 * These are NOT valid for R-Car Gen1 and RZ/A1! 43 */ 44 45 /* 46 * Module Stop Status Register offsets 47 */ 48 49 static const u16 mstpsr[] = { 50 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 51 0x9A0, 0x9A4, 0x9A8, 0x9AC, 52 }; 53 54 #define MSTPSR(i) mstpsr[i] 55 56 57 /* 58 * System Module Stop Control Register offsets 59 */ 60 61 static const u16 smstpcr[] = { 62 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 63 0x990, 0x994, 0x998, 0x99C, 64 }; 65 66 #define SMSTPCR(i) smstpcr[i] 67 68 69 /* Realtime Module Stop Control Register offsets */ 70 #define RMSTPCR(i) (smstpcr[i] - 0x20) 71 72 /* Modem Module Stop Control Register offsets (r8a73a4) */ 73 #define MMSTPCR(i) (smstpcr[i] + 0x20) 74 75 /* Software Reset Clearing Register offsets */ 76 #define SRSTCLR(i) (0x940 + (i) * 4) 77 78 struct gen3_clk_priv { 79 void __iomem *base; 80 struct clk clk_extal; 81 struct clk clk_extalr; 82 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 83 const struct cpg_core_clk *core_clk; 84 u32 core_clk_size; 85 const struct mssr_mod_clk *mod_clk; 86 u32 mod_clk_size; 87 }; 88 89 /* 90 * Definitions of CPG Core Clocks 91 * 92 * These include: 93 * - Clock outputs exported to DT 94 * - External input clocks 95 * - Internal CPG clocks 96 */ 97 struct cpg_core_clk { 98 /* Common */ 99 const char *name; 100 unsigned int id; 101 unsigned int type; 102 /* Depending on type */ 103 unsigned int parent; /* Core Clocks only */ 104 unsigned int div; 105 unsigned int mult; 106 unsigned int offset; 107 }; 108 109 enum clk_types { 110 /* Generic */ 111 CLK_TYPE_IN, /* External Clock Input */ 112 CLK_TYPE_FF, /* Fixed Factor Clock */ 113 114 /* Custom definitions start here */ 115 CLK_TYPE_CUSTOM, 116 }; 117 118 #define DEF_TYPE(_name, _id, _type...) \ 119 { .name = _name, .id = _id, .type = _type } 120 #define DEF_BASE(_name, _id, _type, _parent...) \ 121 DEF_TYPE(_name, _id, _type, .parent = _parent) 122 123 #define DEF_INPUT(_name, _id) \ 124 DEF_TYPE(_name, _id, CLK_TYPE_IN) 125 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ 126 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 127 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 128 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 129 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ 130 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset) 131 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 132 _div_clean) \ 133 DEF_BASE(_name, _id, CLK_TYPE_FF, \ 134 (_parent_clean), .div = (_div_clean), 1) 135 136 /* 137 * Definitions of Module Clocks 138 */ 139 struct mssr_mod_clk { 140 const char *name; 141 unsigned int id; 142 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */ 143 }; 144 145 /* Convert from sparse base-100 to packed index space */ 146 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) 147 148 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x)) 149 150 #define DEF_MOD(_name, _mod, _parent...) \ 151 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } 152 153 enum rcar_gen3_clk_types { 154 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 155 CLK_TYPE_GEN3_PLL0, 156 CLK_TYPE_GEN3_PLL1, 157 CLK_TYPE_GEN3_PLL2, 158 CLK_TYPE_GEN3_PLL3, 159 CLK_TYPE_GEN3_PLL4, 160 CLK_TYPE_GEN3_SD, 161 CLK_TYPE_GEN3_RPC, 162 CLK_TYPE_GEN3_R, 163 CLK_TYPE_GEN3_PE, 164 CLK_TYPE_GEN3_Z2, 165 }; 166 167 struct rcar_gen3_cpg_pll_config { 168 unsigned int extal_div; 169 unsigned int pll1_mult; 170 unsigned int pll3_mult; 171 }; 172 173 enum clk_ids { 174 /* Core Clock Outputs exported to DT */ 175 LAST_DT_CORE_CLK = R8A7796_CLK_OSC, 176 177 /* External Input Clocks */ 178 CLK_EXTAL, 179 CLK_EXTALR, 180 181 /* Internal Core Clocks */ 182 CLK_MAIN, 183 CLK_PLL0, 184 CLK_PLL1, 185 CLK_PLL2, 186 CLK_PLL3, 187 CLK_PLL4, 188 CLK_PLL1_DIV2, 189 CLK_PLL1_DIV4, 190 CLK_PLL0D2, 191 CLK_PLL0D3, 192 CLK_PLL0D5, 193 CLK_PLL1D2, 194 CLK_PE, 195 CLK_S0, 196 CLK_S1, 197 CLK_S2, 198 CLK_S3, 199 CLK_SDSRC, 200 CLK_RPCSRC, 201 CLK_SSPSRC, 202 CLK_RINT, 203 204 /* Module Clocks */ 205 MOD_CLK_BASE 206 }; 207 208 static const struct cpg_core_clk r8a7795_core_clks[] = { 209 /* External Clock Inputs */ 210 DEF_INPUT("extal", CLK_EXTAL), 211 DEF_INPUT("extalr", CLK_EXTALR), 212 213 /* Internal Core Clocks */ 214 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 215 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 216 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 217 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 218 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 219 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 220 221 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 222 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 223 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 224 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 225 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 226 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 227 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 228 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), 229 230 /* Core Clock Outputs */ 231 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 232 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 233 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 234 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 235 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 236 DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), 237 DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), 238 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 239 DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), 240 DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), 241 DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), 242 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 243 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 244 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 245 DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), 246 DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), 247 DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), 248 DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), 249 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 250 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 251 252 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), 253 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), 254 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), 255 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), 256 257 DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), 258 259 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 260 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 261 262 /* NOTE: HDMI, CSI, CAN etc. clock are missing */ 263 264 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 265 }; 266 267 static const struct mssr_mod_clk r8a7795_mod_clks[] = { 268 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ 269 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), 270 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), 271 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 272 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 273 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 274 DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), 275 DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), 276 DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), 277 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 278 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 279 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 280 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), 281 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), 282 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), 283 DEF_MOD("cmt3", 300, R8A7795_CLK_R), 284 DEF_MOD("cmt2", 301, R8A7795_CLK_R), 285 DEF_MOD("cmt1", 302, R8A7795_CLK_R), 286 DEF_MOD("cmt0", 303, R8A7795_CLK_R), 287 DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), 288 DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), 289 DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), 290 DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), 291 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 292 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 293 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 294 DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), 295 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ 296 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 297 DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), 298 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 299 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 300 DEF_MOD("rwdt", 402, R8A7795_CLK_R), 301 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 302 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 303 DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), 304 DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), 305 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), 306 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), 307 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), 308 DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), 309 DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), 310 DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), 311 DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), 312 DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), 313 DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 314 DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 315 DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 316 DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 317 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 318 DEF_MOD("thermal", 522, R8A7795_CLK_CP), 319 DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), 320 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ 321 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), 322 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), 323 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), 324 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), 325 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), 326 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ 327 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), 328 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), 329 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ 330 DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), 331 DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), 332 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ 333 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ 334 DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), 335 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ 336 DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), 337 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), 338 DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), 339 DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), 340 DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), 341 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ 342 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), 343 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), 344 DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), 345 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), 346 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), 347 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), 348 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), 349 DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), 350 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ 351 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 352 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 353 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), 354 DEF_MOD("du3", 721, R8A7795_CLK_S2D1), 355 DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 356 DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 357 DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 358 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), 359 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 360 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 361 DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), 362 DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), 363 DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), 364 DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), 365 DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), 366 DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), 367 DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), 368 DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), 369 DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), 370 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 371 DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), 372 DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), 373 DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), 374 DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), 375 DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), 376 DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), 377 DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), 378 DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), 379 DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), 380 DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), 381 DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), 382 DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), 383 DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), 384 DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), 385 DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), 386 DEF_MOD("rpc", 917, R8A7795_CLK_RPC), 387 DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), 388 DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), 389 DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), 390 DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), 391 DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), 392 DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), 393 DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), 394 DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), 395 DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), 396 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 397 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 398 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 399 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 400 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 401 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 402 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 403 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 404 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 405 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 406 DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), 407 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 408 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 409 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 410 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 411 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 412 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 413 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 414 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 415 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 416 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 417 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 418 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 419 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 420 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 421 }; 422 423 static const struct cpg_core_clk r8a7796_core_clks[] = { 424 /* External Clock Inputs */ 425 DEF_INPUT("extal", CLK_EXTAL), 426 DEF_INPUT("extalr", CLK_EXTALR), 427 428 /* Internal Core Clocks */ 429 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 430 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 431 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 432 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 433 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 434 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 435 436 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 437 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 438 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 439 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 440 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 441 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 442 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 443 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), 444 445 /* Core Clock Outputs */ 446 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 447 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 448 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 449 DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 450 DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1), 451 DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1), 452 DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1), 453 DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1), 454 DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1), 455 DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1), 456 DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1), 457 DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1), 458 DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1), 459 DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1), 460 DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1), 461 DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1), 462 DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1), 463 DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1), 464 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), 465 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), 466 467 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), 468 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), 469 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), 470 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), 471 472 DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238), 473 474 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), 475 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), 476 477 /* NOTE: HDMI, CSI, CAN etc. clock are missing */ 478 479 DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 480 }; 481 482 static const struct mssr_mod_clk r8a7796_mod_clks[] = { 483 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), 484 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), 485 DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), 486 DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), 487 DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), 488 DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), 489 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), 490 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), 491 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), 492 DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), 493 DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), 494 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), 495 DEF_MOD("cmt3", 300, R8A7796_CLK_R), 496 DEF_MOD("cmt2", 301, R8A7796_CLK_R), 497 DEF_MOD("cmt1", 302, R8A7796_CLK_R), 498 DEF_MOD("cmt0", 303, R8A7796_CLK_R), 499 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), 500 DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), 501 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), 502 DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), 503 DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), 504 DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), 505 DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), 506 DEF_MOD("usb3-if0", 328, R8A7796_CLK_S3D1), 507 DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), 508 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), 509 DEF_MOD("rwdt", 402, R8A7796_CLK_R), 510 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), 511 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), 512 DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), 513 DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), 514 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), 515 DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), 516 DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), 517 DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), 518 DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), 519 DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), 520 DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), 521 DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), 522 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), 523 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), 524 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), 525 DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), 526 DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), 527 DEF_MOD("thermal", 522, R8A7796_CLK_CP), 528 DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), 529 DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), 530 DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), 531 DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2), 532 DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1), 533 DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1), 534 DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1), 535 DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2), 536 DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2), 537 DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2), 538 DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2), 539 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), 540 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), 541 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), 542 DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), 543 DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), 544 DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), 545 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), 546 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), 547 DEF_MOD("du2", 722, R8A7796_CLK_S2D1), 548 DEF_MOD("du1", 723, R8A7796_CLK_S2D1), 549 DEF_MOD("du0", 724, R8A7796_CLK_S2D1), 550 DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), 551 DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), 552 DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), 553 DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), 554 DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), 555 DEF_MOD("vin4", 807, R8A7796_CLK_S0D2), 556 DEF_MOD("vin3", 808, R8A7796_CLK_S0D2), 557 DEF_MOD("vin2", 809, R8A7796_CLK_S0D2), 558 DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), 559 DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), 560 DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), 561 DEF_MOD("imr1", 822, R8A7796_CLK_S0D2), 562 DEF_MOD("imr0", 823, R8A7796_CLK_S0D2), 563 DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), 564 DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), 565 DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), 566 DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4), 567 DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4), 568 DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), 569 DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), 570 DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), 571 DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), 572 DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), 573 DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), 574 DEF_MOD("rpc", 917, R8A7796_CLK_RPC), 575 DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), 576 DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), 577 DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), 578 DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), 579 DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), 580 DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2), 581 DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2), 582 DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2), 583 DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4), 584 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 585 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 586 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 587 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 588 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 589 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 590 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 591 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 592 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 593 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 594 DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4), 595 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 596 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 597 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 598 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 599 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 600 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 601 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 602 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 603 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 604 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 605 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 606 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 607 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 608 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 609 }; 610 611 static const struct cpg_core_clk r8a77970_core_clks[] = { 612 /* External Clock Inputs */ 613 DEF_INPUT("extal", CLK_EXTAL), 614 DEF_INPUT("extalr", CLK_EXTALR), 615 616 /* Internal Core Clocks */ 617 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 618 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 619 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 620 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 621 622 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 623 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 624 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1), 625 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1), 626 DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), 627 628 /* Core Clock Outputs */ 629 DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4), 630 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 631 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 632 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 633 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), 634 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1), 635 DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1), 636 DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1), 637 DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1), 638 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1), 639 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1), 640 641 DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074), 642 643 DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238), 644 645 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), 646 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), 647 648 /* NOTE: HDMI, CSI, CAN etc. clock are missing */ 649 650 DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 651 }; 652 653 static const struct mssr_mod_clk r8a77970_mod_clks[] = { 654 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), 655 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 656 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 657 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 658 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ 659 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO), 660 DEF_MOD("msiof2", 209, R8A77970_CLK_MSO), 661 DEF_MOD("msiof1", 210, R8A77970_CLK_MSO), 662 DEF_MOD("msiof0", 211, R8A77970_CLK_MSO), 663 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */ 664 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 665 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 666 DEF_MOD("sdif", 314, R8A77970_CLK_SD0), 667 DEF_MOD("rwdt0", 402, R8A77970_CLK_R), 668 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), 669 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 670 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 671 DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 672 DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 673 DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ 674 DEF_MOD("thermal", 522, R8A77970_CLK_CP), 675 DEF_MOD("pwm", 523, R8A77970_CLK_S2D4), 676 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1), 677 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1), 678 DEF_MOD("csi40", 716, R8A77970_CLK_CSI0), 679 DEF_MOD("du0", 724, R8A77970_CLK_S2D1), 680 DEF_MOD("lvds", 727, R8A77970_CLK_S2D1), 681 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1), 682 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1), 683 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1), 684 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1), 685 DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2), 686 DEF_MOD("isp", 817, R8A77970_CLK_S2D1), 687 DEF_MOD("gpio5", 907, R8A77970_CLK_CP), 688 DEF_MOD("gpio4", 908, R8A77970_CLK_CP), 689 DEF_MOD("gpio3", 909, R8A77970_CLK_CP), 690 DEF_MOD("gpio2", 910, R8A77970_CLK_CP), 691 DEF_MOD("gpio1", 911, R8A77970_CLK_CP), 692 DEF_MOD("gpio0", 912, R8A77970_CLK_CP), 693 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), 694 DEF_MOD("rpc", 917, R8A77970_CLK_RPC), 695 DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), 696 DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), 697 DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), 698 DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2), 699 DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2), 700 }; 701 702 static const struct cpg_core_clk r8a77995_core_clks[] = { 703 /* External Clock Inputs */ 704 DEF_INPUT("extal", CLK_EXTAL), 705 706 /* Internal Core Clocks */ 707 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 708 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 709 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 710 711 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250), 712 DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1), 713 DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1), 714 DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1), 715 DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), 716 DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1), 717 DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), 718 DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), 719 DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), 720 DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), 721 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), 722 723 /* Core Clock Outputs */ 724 DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), 725 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), 726 DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), 727 DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1), 728 DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1), 729 DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1), 730 DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1), 731 DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1), 732 DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1), 733 DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1), 734 DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1), 735 DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1), 736 DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1), 737 DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1), 738 739 DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), 740 DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), 741 DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), 742 DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), 743 744 DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), 745 DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), 746 DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), 747 DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), 748 749 DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), 750 }; 751 752 static const struct mssr_mod_clk r8a77995_mod_clks[] = { 753 DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C), 754 DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C), 755 DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C), 756 DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C), 757 DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C), 758 DEF_MOD("msiof3", 208, R8A77995_CLK_MSO), 759 DEF_MOD("msiof2", 209, R8A77995_CLK_MSO), 760 DEF_MOD("msiof1", 210, R8A77995_CLK_MSO), 761 DEF_MOD("msiof0", 211, R8A77995_CLK_MSO), 762 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1), 763 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1), 764 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1), 765 DEF_MOD("cmt3", 300, R8A77995_CLK_R), 766 DEF_MOD("cmt2", 301, R8A77995_CLK_R), 767 DEF_MOD("cmt1", 302, R8A77995_CLK_R), 768 DEF_MOD("cmt0", 303, R8A77995_CLK_R), 769 DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C), 770 DEF_MOD("emmc0", 312, R8A77995_CLK_SD0), 771 DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1), 772 DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1), 773 DEF_MOD("rwdt", 402, R8A77995_CLK_R), 774 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), 775 DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1), 776 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), 777 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), 778 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), 779 DEF_MOD("thermal", 522, R8A77995_CLK_CP), 780 DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C), 781 DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2), 782 DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2), 783 DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1), 784 DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2), 785 DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2), 786 DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1), 787 DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2), 788 DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2), 789 DEF_MOD("du1", 723, R8A77995_CLK_S2D1), 790 DEF_MOD("du0", 724, R8A77995_CLK_S2D1), 791 DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), 792 DEF_MOD("vin7", 804, R8A77995_CLK_S1D2), 793 DEF_MOD("vin6", 805, R8A77995_CLK_S1D2), 794 DEF_MOD("vin5", 806, R8A77995_CLK_S1D2), 795 DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), 796 DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), 797 DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), 798 DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4), 799 DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4), 800 DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4), 801 DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4), 802 DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4), 803 DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4), 804 DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4), 805 DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), 806 DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), 807 DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), 808 DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), 809 DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), 810 DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), 811 DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2), 812 DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4), 813 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 814 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 815 DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4), 816 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 817 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 818 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 819 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 820 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 821 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 822 }; 823 824 /* 825 * CPG Clock Data 826 */ 827 828 /* 829 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 830 * 14 13 19 17 (MHz) 831 *------------------------------------------------------------------- 832 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 833 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 834 * 0 0 1 0 Prohibited setting 835 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 836 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 837 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 838 * 0 1 1 0 Prohibited setting 839 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 840 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 841 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 842 * 1 0 1 0 Prohibited setting 843 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 844 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 845 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 846 * 1 1 1 0 Prohibited setting 847 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 848 */ 849 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 850 (((md) & BIT(13)) >> 11) | \ 851 (((md) & BIT(19)) >> 18) | \ 852 (((md) & BIT(17)) >> 17)) 853 854 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { 855 /* EXTAL div PLL1 mult PLL3 mult */ 856 { 1, 192, 192, }, 857 { 1, 192, 128, }, 858 { 0, /* Prohibited setting */ }, 859 { 1, 192, 192, }, 860 { 1, 160, 160, }, 861 { 1, 160, 106, }, 862 { 0, /* Prohibited setting */ }, 863 { 1, 160, 160, }, 864 { 1, 128, 128, }, 865 { 1, 128, 84, }, 866 { 0, /* Prohibited setting */ }, 867 { 1, 128, 128, }, 868 { 2, 192, 192, }, 869 { 2, 192, 128, }, 870 { 0, /* Prohibited setting */ }, 871 { 2, 192, 192, }, 872 }; 873 874 /* 875 * SDn Clock 876 */ 877 #define CPG_SD_STP_HCK BIT(9) 878 #define CPG_SD_STP_CK BIT(8) 879 880 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) 881 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) 882 883 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ 884 { \ 885 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ 886 ((stp_ck) ? CPG_SD_STP_CK : 0) | \ 887 ((sd_srcfc) << 2) | \ 888 ((sd_fc) << 0), \ 889 .div = (sd_div), \ 890 } 891 892 struct sd_div_table { 893 u32 val; 894 unsigned int div; 895 }; 896 897 /* SDn divider 898 * sd_srcfc sd_fc div 899 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc 900 *------------------------------------------------------------------- 901 * 0 0 0 (1) 1 (4) 4 902 * 0 0 1 (2) 1 (4) 8 903 * 1 0 2 (4) 1 (4) 16 904 * 1 0 3 (8) 1 (4) 32 905 * 1 0 4 (16) 1 (4) 64 906 * 0 0 0 (1) 0 (2) 2 907 * 0 0 1 (2) 0 (2) 4 908 * 1 0 2 (4) 0 (2) 8 909 * 1 0 3 (8) 0 (2) 16 910 * 1 0 4 (16) 0 (2) 32 911 */ 912 static const struct sd_div_table cpg_sd_div_table[] = { 913 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ 914 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), 915 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), 916 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), 917 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), 918 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), 919 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), 920 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), 921 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), 922 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), 923 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), 924 }; 925 926 static bool gen3_clk_is_mod(struct clk *clk) 927 { 928 return (clk->id >> 16) == CPG_MOD; 929 } 930 931 static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr) 932 { 933 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 934 const unsigned long clkid = clk->id & 0xffff; 935 int i; 936 937 if (!gen3_clk_is_mod(clk)) 938 return -EINVAL; 939 940 for (i = 0; i < priv->mod_clk_size; i++) { 941 if (priv->mod_clk[i].id != MOD_CLK_ID(clkid)) 942 continue; 943 944 *mssr = &priv->mod_clk[i]; 945 return 0; 946 } 947 948 return -ENODEV; 949 } 950 951 static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core) 952 { 953 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 954 const unsigned long clkid = clk->id & 0xffff; 955 int i; 956 957 if (gen3_clk_is_mod(clk)) 958 return -EINVAL; 959 960 for (i = 0; i < priv->core_clk_size; i++) { 961 if (priv->core_clk[i].id != clkid) 962 continue; 963 964 *core = &priv->core_clk[i]; 965 return 0; 966 } 967 968 return -ENODEV; 969 } 970 971 static int gen3_clk_get_parent(struct clk *clk, struct clk *parent) 972 { 973 const struct cpg_core_clk *core; 974 const struct mssr_mod_clk *mssr; 975 int ret; 976 977 if (gen3_clk_is_mod(clk)) { 978 ret = gen3_clk_get_mod(clk, &mssr); 979 if (ret) 980 return ret; 981 982 parent->id = mssr->parent; 983 } else { 984 ret = gen3_clk_get_core(clk, &core); 985 if (ret) 986 return ret; 987 988 if (core->type == CLK_TYPE_IN) 989 parent->id = ~0; /* Top-level clock */ 990 else 991 parent->id = core->parent; 992 } 993 994 parent->dev = clk->dev; 995 996 return 0; 997 } 998 999 static int gen3_clk_setup_sdif_div(struct clk *clk) 1000 { 1001 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 1002 const struct cpg_core_clk *core; 1003 struct clk parent; 1004 int ret; 1005 1006 ret = gen3_clk_get_parent(clk, &parent); 1007 if (ret) { 1008 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); 1009 return ret; 1010 } 1011 1012 if (gen3_clk_is_mod(&parent)) 1013 return 0; 1014 1015 ret = gen3_clk_get_core(&parent, &core); 1016 if (ret) 1017 return ret; 1018 1019 if (core->type != CLK_TYPE_GEN3_SD) 1020 return 0; 1021 1022 debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); 1023 1024 writel(1, priv->base + core->offset); 1025 1026 return 0; 1027 } 1028 1029 static int gen3_clk_endisable(struct clk *clk, bool enable) 1030 { 1031 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 1032 const unsigned long clkid = clk->id & 0xffff; 1033 const unsigned int reg = clkid / 100; 1034 const unsigned int bit = clkid % 100; 1035 const u32 bitmask = BIT(bit); 1036 int ret; 1037 1038 if (!gen3_clk_is_mod(clk)) 1039 return -EINVAL; 1040 1041 debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__, 1042 clkid, reg, bit, enable ? "ON" : "OFF"); 1043 1044 if (enable) { 1045 ret = gen3_clk_setup_sdif_div(clk); 1046 if (ret) 1047 return ret; 1048 clrbits_le32(priv->base + SMSTPCR(reg), bitmask); 1049 return wait_for_bit("MSTP", priv->base + MSTPSR(reg), 1050 bitmask, 0, 100, 0); 1051 } else { 1052 setbits_le32(priv->base + SMSTPCR(reg), bitmask); 1053 return 0; 1054 } 1055 } 1056 1057 static int gen3_clk_enable(struct clk *clk) 1058 { 1059 return gen3_clk_endisable(clk, true); 1060 } 1061 1062 static int gen3_clk_disable(struct clk *clk) 1063 { 1064 return gen3_clk_endisable(clk, false); 1065 } 1066 1067 static ulong gen3_clk_get_rate(struct clk *clk) 1068 { 1069 struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 1070 struct clk parent; 1071 const struct cpg_core_clk *core; 1072 const struct rcar_gen3_cpg_pll_config *pll_config = 1073 priv->cpg_pll_config; 1074 u32 value, mult, prediv, postdiv, rate = 0; 1075 int i, ret; 1076 1077 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); 1078 1079 ret = gen3_clk_get_parent(clk, &parent); 1080 if (ret) { 1081 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); 1082 return ret; 1083 } 1084 1085 if (gen3_clk_is_mod(clk)) { 1086 rate = gen3_clk_get_rate(&parent); 1087 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", 1088 __func__, __LINE__, parent.id, rate); 1089 return rate; 1090 } 1091 1092 ret = gen3_clk_get_core(clk, &core); 1093 if (ret) 1094 return ret; 1095 1096 switch (core->type) { 1097 case CLK_TYPE_IN: 1098 if (core->id == CLK_EXTAL) { 1099 rate = clk_get_rate(&priv->clk_extal); 1100 debug("%s[%i] EXTAL clk: rate=%u\n", 1101 __func__, __LINE__, rate); 1102 return rate; 1103 } 1104 1105 if (core->id == CLK_EXTALR) { 1106 rate = clk_get_rate(&priv->clk_extalr); 1107 debug("%s[%i] EXTALR clk: rate=%u\n", 1108 __func__, __LINE__, rate); 1109 return rate; 1110 } 1111 1112 return -EINVAL; 1113 1114 case CLK_TYPE_GEN3_MAIN: 1115 rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; 1116 debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", 1117 __func__, __LINE__, 1118 core->parent, pll_config->extal_div, rate); 1119 return rate; 1120 1121 case CLK_TYPE_GEN3_PLL0: 1122 value = readl(priv->base + CPG_PLL0CR); 1123 mult = (((value >> 24) & 0x7f) + 1) * 2; 1124 rate = gen3_clk_get_rate(&parent) * mult; 1125 debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", 1126 __func__, __LINE__, core->parent, mult, rate); 1127 return rate; 1128 1129 case CLK_TYPE_GEN3_PLL1: 1130 rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; 1131 debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", 1132 __func__, __LINE__, 1133 core->parent, pll_config->pll1_mult, rate); 1134 return rate; 1135 1136 case CLK_TYPE_GEN3_PLL2: 1137 value = readl(priv->base + CPG_PLL2CR); 1138 mult = (((value >> 24) & 0x7f) + 1) * 2; 1139 rate = gen3_clk_get_rate(&parent) * mult; 1140 debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n", 1141 __func__, __LINE__, core->parent, mult, rate); 1142 return rate; 1143 1144 case CLK_TYPE_GEN3_PLL3: 1145 rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; 1146 debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", 1147 __func__, __LINE__, 1148 core->parent, pll_config->pll3_mult, rate); 1149 return rate; 1150 1151 case CLK_TYPE_GEN3_PLL4: 1152 value = readl(priv->base + CPG_PLL4CR); 1153 mult = (((value >> 24) & 0x7f) + 1) * 2; 1154 rate = gen3_clk_get_rate(&parent) * mult; 1155 debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n", 1156 __func__, __LINE__, core->parent, mult, rate); 1157 return rate; 1158 1159 case CLK_TYPE_FF: 1160 case CLK_TYPE_GEN3_PE: /* FIXME */ 1161 rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; 1162 debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", 1163 __func__, __LINE__, 1164 core->parent, core->mult, core->div, rate); 1165 return rate; 1166 1167 case CLK_TYPE_GEN3_SD: /* FIXME */ 1168 value = readl(priv->base + core->offset); 1169 value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; 1170 1171 for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) { 1172 if (cpg_sd_div_table[i].val != value) 1173 continue; 1174 1175 rate = gen3_clk_get_rate(&parent) / 1176 cpg_sd_div_table[i].div; 1177 debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n", 1178 __func__, __LINE__, 1179 core->parent, cpg_sd_div_table[i].div, rate); 1180 1181 return rate; 1182 } 1183 1184 return -EINVAL; 1185 1186 case CLK_TYPE_GEN3_RPC: 1187 rate = gen3_clk_get_rate(&parent); 1188 1189 value = readl(priv->base + core->offset); 1190 1191 prediv = (value >> CPG_RPC_PREDIV_OFFSET) & 1192 CPG_RPC_PREDIV_MASK; 1193 if (prediv == 2) 1194 rate /= 5; 1195 else if (prediv == 3) 1196 rate /= 6; 1197 else 1198 return -EINVAL; 1199 1200 postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & 1201 CPG_RPC_POSTDIV_MASK; 1202 rate /= postdiv + 1; 1203 1204 debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n", 1205 __func__, __LINE__, 1206 core->parent, prediv, postdiv, rate); 1207 1208 return -EINVAL; 1209 1210 } 1211 1212 printf("%s[%i] unknown fail\n", __func__, __LINE__); 1213 1214 return -ENOENT; 1215 } 1216 1217 static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) 1218 { 1219 return gen3_clk_get_rate(clk); 1220 } 1221 1222 static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) 1223 { 1224 if (args->args_count != 2) { 1225 debug("Invaild args_count: %d\n", args->args_count); 1226 return -EINVAL; 1227 } 1228 1229 clk->id = (args->args[0] << 16) | args->args[1]; 1230 1231 return 0; 1232 } 1233 1234 static const struct clk_ops gen3_clk_ops = { 1235 .enable = gen3_clk_enable, 1236 .disable = gen3_clk_disable, 1237 .get_rate = gen3_clk_get_rate, 1238 .set_rate = gen3_clk_set_rate, 1239 .of_xlate = gen3_clk_of_xlate, 1240 }; 1241 1242 enum gen3_clk_model { 1243 CLK_R8A7795, 1244 CLK_R8A7796, 1245 CLK_R8A77970, 1246 CLK_R8A77995, 1247 }; 1248 1249 static int gen3_clk_probe(struct udevice *dev) 1250 { 1251 struct gen3_clk_priv *priv = dev_get_priv(dev); 1252 enum gen3_clk_model model = dev_get_driver_data(dev); 1253 fdt_addr_t rst_base; 1254 u32 cpg_mode; 1255 int ret; 1256 1257 priv->base = (struct gen3_base *)devfdt_get_addr(dev); 1258 if (!priv->base) 1259 return -EINVAL; 1260 1261 switch (model) { 1262 case CLK_R8A7795: 1263 priv->core_clk = r8a7795_core_clks; 1264 priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks); 1265 priv->mod_clk = r8a7795_mod_clks; 1266 priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks); 1267 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1268 "renesas,r8a7795-rst"); 1269 if (ret < 0) 1270 return ret; 1271 break; 1272 case CLK_R8A7796: 1273 priv->core_clk = r8a7796_core_clks; 1274 priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks); 1275 priv->mod_clk = r8a7796_mod_clks; 1276 priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks); 1277 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1278 "renesas,r8a7796-rst"); 1279 if (ret < 0) 1280 return ret; 1281 break; 1282 case CLK_R8A77970: 1283 priv->core_clk = r8a77970_core_clks; 1284 priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks); 1285 priv->mod_clk = r8a77970_mod_clks; 1286 priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks); 1287 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1288 "renesas,r8a77970-rst"); 1289 if (ret < 0) 1290 return ret; 1291 break; 1292 case CLK_R8A77995: 1293 priv->core_clk = r8a77995_core_clks; 1294 priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks); 1295 priv->mod_clk = r8a77995_mod_clks; 1296 priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks); 1297 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 1298 "renesas,r8a77995-rst"); 1299 if (ret < 0) 1300 return ret; 1301 break; 1302 default: 1303 return -EINVAL; 1304 } 1305 1306 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); 1307 if (rst_base == FDT_ADDR_T_NONE) 1308 return -EINVAL; 1309 1310 cpg_mode = readl(rst_base + CPG_RST_MODEMR); 1311 1312 priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 1313 if (!priv->cpg_pll_config->extal_div) 1314 return -EINVAL; 1315 1316 ret = clk_get_by_name(dev, "extal", &priv->clk_extal); 1317 if (ret < 0) 1318 return ret; 1319 1320 if (model != CLK_R8A77995) { 1321 ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr); 1322 if (ret < 0) 1323 return ret; 1324 } 1325 1326 return 0; 1327 } 1328 1329 struct mstp_stop_table { 1330 u32 dis; 1331 u32 en; 1332 }; 1333 1334 static struct mstp_stop_table r8a7795_mstp_table[] = { 1335 { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 }, 1336 { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 }, 1337 { 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 }, 1338 { 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 }, 1339 { 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 }, 1340 { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 }, 1341 }; 1342 1343 static struct mstp_stop_table r8a7796_mstp_table[] = { 1344 { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, 1345 { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, 1346 { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 }, 1347 { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, 1348 { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 }, 1349 { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, 1350 }; 1351 1352 static struct mstp_stop_table r8a77970_mstp_table[] = { 1353 { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 }, 1354 { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 }, 1355 { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 }, 1356 { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, 1357 { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 }, 1358 { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, 1359 }; 1360 1361 static struct mstp_stop_table r8a77995_mstp_table[] = { 1362 { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, 1363 { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, 1364 { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 }, 1365 { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, 1366 { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 }, 1367 { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, 1368 }; 1369 1370 #define TSTR0 0x04 1371 #define TSTR0_STR0 BIT(0) 1372 1373 static int gen3_clk_remove(struct udevice *dev) 1374 { 1375 struct gen3_clk_priv *priv = dev_get_priv(dev); 1376 enum gen3_clk_model model = dev_get_driver_data(dev); 1377 struct mstp_stop_table *tbl; 1378 unsigned int i, tbl_size; 1379 1380 switch (model) { 1381 case CLK_R8A7795: 1382 tbl = r8a7795_mstp_table; 1383 tbl_size = ARRAY_SIZE(r8a7795_mstp_table); 1384 break; 1385 case CLK_R8A7796: 1386 tbl = r8a7796_mstp_table; 1387 tbl_size = ARRAY_SIZE(r8a7796_mstp_table); 1388 break; 1389 case CLK_R8A77970: 1390 tbl = r8a77970_mstp_table; 1391 tbl_size = ARRAY_SIZE(r8a77970_mstp_table); 1392 break; 1393 case CLK_R8A77995: 1394 tbl = r8a77995_mstp_table; 1395 tbl_size = ARRAY_SIZE(r8a77995_mstp_table); 1396 break; 1397 default: 1398 return -EINVAL; 1399 } 1400 1401 /* Stop TMU0 */ 1402 clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0); 1403 1404 /* Stop module clock */ 1405 for (i = 0; i < tbl_size; i++) { 1406 clrsetbits_le32(priv->base + SMSTPCR(i), tbl[i].dis, tbl[i].en); 1407 clrsetbits_le32(priv->base + RMSTPCR(i), tbl[i].dis, 0x0); 1408 } 1409 1410 return 0; 1411 } 1412 1413 static const struct udevice_id gen3_clk_ids[] = { 1414 { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, 1415 { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, 1416 { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 }, 1417 { .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 }, 1418 { } 1419 }; 1420 1421 U_BOOT_DRIVER(clk_gen3) = { 1422 .name = "clk_gen3", 1423 .id = UCLASS_CLK, 1424 .of_match = gen3_clk_ids, 1425 .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), 1426 .ops = &gen3_clk_ops, 1427 .probe = gen3_clk_probe, 1428 .remove = gen3_clk_remove, 1429 }; 1430