136c2ee4cSMarek Vasut /* 236c2ee4cSMarek Vasut * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver 336c2ee4cSMarek Vasut * 436c2ee4cSMarek Vasut * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 536c2ee4cSMarek Vasut * 636c2ee4cSMarek Vasut * Based on the following driver from Linux kernel: 736c2ee4cSMarek Vasut * r8a7796 Clock Pulse Generator / Module Standby and Software Reset 836c2ee4cSMarek Vasut * 936c2ee4cSMarek Vasut * Copyright (C) 2016 Glider bvba 1036c2ee4cSMarek Vasut * 1136c2ee4cSMarek Vasut * SPDX-License-Identifier: GPL-2.0+ 1236c2ee4cSMarek Vasut */ 1336c2ee4cSMarek Vasut 1436c2ee4cSMarek Vasut #include <common.h> 1536c2ee4cSMarek Vasut #include <clk-uclass.h> 1636c2ee4cSMarek Vasut #include <dm.h> 1736c2ee4cSMarek Vasut #include <errno.h> 1836c2ee4cSMarek Vasut #include <wait_bit.h> 1936c2ee4cSMarek Vasut #include <asm/io.h> 2036c2ee4cSMarek Vasut 2136c2ee4cSMarek Vasut #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 2236c2ee4cSMarek Vasut #include <dt-bindings/clock/r8a7796-cpg-mssr.h> 2336c2ee4cSMarek Vasut 2436c2ee4cSMarek Vasut #define CPG_RST_MODEMR 0x0060 2536c2ee4cSMarek Vasut 2636c2ee4cSMarek Vasut #define CPG_PLL0CR 0x00d8 2736c2ee4cSMarek Vasut #define CPG_PLL2CR 0x002c 2836c2ee4cSMarek Vasut #define CPG_PLL4CR 0x01f4 2936c2ee4cSMarek Vasut 30*849ab0a6SMarek Vasut #define CPG_RPC_PREDIV_MASK 0x3 31*849ab0a6SMarek Vasut #define CPG_RPC_PREDIV_OFFSET 3 32*849ab0a6SMarek Vasut #define CPG_RPC_POSTDIV_MASK 0x7 33*849ab0a6SMarek Vasut #define CPG_RPC_POSTDIV_OFFSET 0 34*849ab0a6SMarek Vasut 3536c2ee4cSMarek Vasut /* 3636c2ee4cSMarek Vasut * Module Standby and Software Reset register offets. 3736c2ee4cSMarek Vasut * 3836c2ee4cSMarek Vasut * If the registers exist, these are valid for SH-Mobile, R-Mobile, 3936c2ee4cSMarek Vasut * R-Car Gen2, R-Car Gen3, and RZ/G1. 4036c2ee4cSMarek Vasut * These are NOT valid for R-Car Gen1 and RZ/A1! 4136c2ee4cSMarek Vasut */ 4236c2ee4cSMarek Vasut 4336c2ee4cSMarek Vasut /* 4436c2ee4cSMarek Vasut * Module Stop Status Register offsets 4536c2ee4cSMarek Vasut */ 4636c2ee4cSMarek Vasut 4736c2ee4cSMarek Vasut static const u16 mstpsr[] = { 4836c2ee4cSMarek Vasut 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 4936c2ee4cSMarek Vasut 0x9A0, 0x9A4, 0x9A8, 0x9AC, 5036c2ee4cSMarek Vasut }; 5136c2ee4cSMarek Vasut 5236c2ee4cSMarek Vasut #define MSTPSR(i) mstpsr[i] 5336c2ee4cSMarek Vasut 5436c2ee4cSMarek Vasut 5536c2ee4cSMarek Vasut /* 5636c2ee4cSMarek Vasut * System Module Stop Control Register offsets 5736c2ee4cSMarek Vasut */ 5836c2ee4cSMarek Vasut 5936c2ee4cSMarek Vasut static const u16 smstpcr[] = { 6036c2ee4cSMarek Vasut 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 6136c2ee4cSMarek Vasut 0x990, 0x994, 0x998, 0x99C, 6236c2ee4cSMarek Vasut }; 6336c2ee4cSMarek Vasut 6436c2ee4cSMarek Vasut #define SMSTPCR(i) smstpcr[i] 6536c2ee4cSMarek Vasut 6636c2ee4cSMarek Vasut 6736c2ee4cSMarek Vasut /* Realtime Module Stop Control Register offsets */ 6836c2ee4cSMarek Vasut #define RMSTPCR(i) (smstpcr[i] - 0x20) 6936c2ee4cSMarek Vasut 7036c2ee4cSMarek Vasut /* Modem Module Stop Control Register offsets (r8a73a4) */ 7136c2ee4cSMarek Vasut #define MMSTPCR(i) (smstpcr[i] + 0x20) 7236c2ee4cSMarek Vasut 7336c2ee4cSMarek Vasut /* Software Reset Clearing Register offsets */ 7436c2ee4cSMarek Vasut #define SRSTCLR(i) (0x940 + (i) * 4) 7536c2ee4cSMarek Vasut 7636c2ee4cSMarek Vasut struct gen3_clk_priv { 7736c2ee4cSMarek Vasut void __iomem *base; 7836c2ee4cSMarek Vasut struct clk clk_extal; 7936c2ee4cSMarek Vasut struct clk clk_extalr; 8036c2ee4cSMarek Vasut const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 81fd8692b8SMarek Vasut const struct cpg_core_clk *core_clk; 82fd8692b8SMarek Vasut u32 core_clk_size; 8336c2ee4cSMarek Vasut const struct mssr_mod_clk *mod_clk; 8436c2ee4cSMarek Vasut u32 mod_clk_size; 8536c2ee4cSMarek Vasut }; 8636c2ee4cSMarek Vasut 8736c2ee4cSMarek Vasut /* 8836c2ee4cSMarek Vasut * Definitions of CPG Core Clocks 8936c2ee4cSMarek Vasut * 9036c2ee4cSMarek Vasut * These include: 9136c2ee4cSMarek Vasut * - Clock outputs exported to DT 9236c2ee4cSMarek Vasut * - External input clocks 9336c2ee4cSMarek Vasut * - Internal CPG clocks 9436c2ee4cSMarek Vasut */ 9536c2ee4cSMarek Vasut struct cpg_core_clk { 9636c2ee4cSMarek Vasut /* Common */ 9736c2ee4cSMarek Vasut const char *name; 9836c2ee4cSMarek Vasut unsigned int id; 9936c2ee4cSMarek Vasut unsigned int type; 10036c2ee4cSMarek Vasut /* Depending on type */ 10136c2ee4cSMarek Vasut unsigned int parent; /* Core Clocks only */ 10236c2ee4cSMarek Vasut unsigned int div; 10336c2ee4cSMarek Vasut unsigned int mult; 10436c2ee4cSMarek Vasut unsigned int offset; 10536c2ee4cSMarek Vasut }; 10636c2ee4cSMarek Vasut 10736c2ee4cSMarek Vasut enum clk_types { 10836c2ee4cSMarek Vasut /* Generic */ 10936c2ee4cSMarek Vasut CLK_TYPE_IN, /* External Clock Input */ 11036c2ee4cSMarek Vasut CLK_TYPE_FF, /* Fixed Factor Clock */ 11136c2ee4cSMarek Vasut 11236c2ee4cSMarek Vasut /* Custom definitions start here */ 11336c2ee4cSMarek Vasut CLK_TYPE_CUSTOM, 11436c2ee4cSMarek Vasut }; 11536c2ee4cSMarek Vasut 11636c2ee4cSMarek Vasut #define DEF_TYPE(_name, _id, _type...) \ 11736c2ee4cSMarek Vasut { .name = _name, .id = _id, .type = _type } 11836c2ee4cSMarek Vasut #define DEF_BASE(_name, _id, _type, _parent...) \ 11936c2ee4cSMarek Vasut DEF_TYPE(_name, _id, _type, .parent = _parent) 12036c2ee4cSMarek Vasut 12136c2ee4cSMarek Vasut #define DEF_INPUT(_name, _id) \ 12236c2ee4cSMarek Vasut DEF_TYPE(_name, _id, CLK_TYPE_IN) 12336c2ee4cSMarek Vasut #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ 12436c2ee4cSMarek Vasut DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 12536c2ee4cSMarek Vasut #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 12636c2ee4cSMarek Vasut DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 127*849ab0a6SMarek Vasut #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ 128*849ab0a6SMarek Vasut DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset) 12936c2ee4cSMarek Vasut 13036c2ee4cSMarek Vasut /* 13136c2ee4cSMarek Vasut * Definitions of Module Clocks 13236c2ee4cSMarek Vasut */ 13336c2ee4cSMarek Vasut struct mssr_mod_clk { 13436c2ee4cSMarek Vasut const char *name; 13536c2ee4cSMarek Vasut unsigned int id; 13636c2ee4cSMarek Vasut unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */ 13736c2ee4cSMarek Vasut }; 13836c2ee4cSMarek Vasut 13936c2ee4cSMarek Vasut /* Convert from sparse base-100 to packed index space */ 14036c2ee4cSMarek Vasut #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32)) 14136c2ee4cSMarek Vasut 14236c2ee4cSMarek Vasut #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x)) 14336c2ee4cSMarek Vasut 14436c2ee4cSMarek Vasut #define DEF_MOD(_name, _mod, _parent...) \ 14536c2ee4cSMarek Vasut { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent } 14636c2ee4cSMarek Vasut 14736c2ee4cSMarek Vasut enum rcar_gen3_clk_types { 14836c2ee4cSMarek Vasut CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 14936c2ee4cSMarek Vasut CLK_TYPE_GEN3_PLL0, 15036c2ee4cSMarek Vasut CLK_TYPE_GEN3_PLL1, 15136c2ee4cSMarek Vasut CLK_TYPE_GEN3_PLL2, 15236c2ee4cSMarek Vasut CLK_TYPE_GEN3_PLL3, 15336c2ee4cSMarek Vasut CLK_TYPE_GEN3_PLL4, 15436c2ee4cSMarek Vasut CLK_TYPE_GEN3_SD, 155*849ab0a6SMarek Vasut CLK_TYPE_GEN3_RPC, 15636c2ee4cSMarek Vasut CLK_TYPE_GEN3_R, 15736c2ee4cSMarek Vasut }; 15836c2ee4cSMarek Vasut 15936c2ee4cSMarek Vasut struct rcar_gen3_cpg_pll_config { 16036c2ee4cSMarek Vasut unsigned int extal_div; 16136c2ee4cSMarek Vasut unsigned int pll1_mult; 16236c2ee4cSMarek Vasut unsigned int pll3_mult; 16336c2ee4cSMarek Vasut }; 16436c2ee4cSMarek Vasut 16536c2ee4cSMarek Vasut enum clk_ids { 16636c2ee4cSMarek Vasut /* Core Clock Outputs exported to DT */ 16736c2ee4cSMarek Vasut LAST_DT_CORE_CLK = R8A7796_CLK_OSC, 16836c2ee4cSMarek Vasut 16936c2ee4cSMarek Vasut /* External Input Clocks */ 17036c2ee4cSMarek Vasut CLK_EXTAL, 17136c2ee4cSMarek Vasut CLK_EXTALR, 17236c2ee4cSMarek Vasut 17336c2ee4cSMarek Vasut /* Internal Core Clocks */ 17436c2ee4cSMarek Vasut CLK_MAIN, 17536c2ee4cSMarek Vasut CLK_PLL0, 17636c2ee4cSMarek Vasut CLK_PLL1, 17736c2ee4cSMarek Vasut CLK_PLL2, 17836c2ee4cSMarek Vasut CLK_PLL3, 17936c2ee4cSMarek Vasut CLK_PLL4, 18036c2ee4cSMarek Vasut CLK_PLL1_DIV2, 18136c2ee4cSMarek Vasut CLK_PLL1_DIV4, 18236c2ee4cSMarek Vasut CLK_S0, 18336c2ee4cSMarek Vasut CLK_S1, 18436c2ee4cSMarek Vasut CLK_S2, 18536c2ee4cSMarek Vasut CLK_S3, 18636c2ee4cSMarek Vasut CLK_SDSRC, 187*849ab0a6SMarek Vasut CLK_RPCSRC, 18836c2ee4cSMarek Vasut CLK_SSPSRC, 18936c2ee4cSMarek Vasut CLK_RINT, 19036c2ee4cSMarek Vasut 19136c2ee4cSMarek Vasut /* Module Clocks */ 19236c2ee4cSMarek Vasut MOD_CLK_BASE 19336c2ee4cSMarek Vasut }; 19436c2ee4cSMarek Vasut 195fd8692b8SMarek Vasut static const struct cpg_core_clk r8a7795_core_clks[] = { 19636c2ee4cSMarek Vasut /* External Clock Inputs */ 19736c2ee4cSMarek Vasut DEF_INPUT("extal", CLK_EXTAL), 19836c2ee4cSMarek Vasut DEF_INPUT("extalr", CLK_EXTALR), 19936c2ee4cSMarek Vasut 20036c2ee4cSMarek Vasut /* Internal Core Clocks */ 20136c2ee4cSMarek Vasut DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 20236c2ee4cSMarek Vasut DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 20336c2ee4cSMarek Vasut DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 20436c2ee4cSMarek Vasut DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 20536c2ee4cSMarek Vasut DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 20636c2ee4cSMarek Vasut DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 20736c2ee4cSMarek Vasut 20836c2ee4cSMarek Vasut DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 20936c2ee4cSMarek Vasut DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 21036c2ee4cSMarek Vasut DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 21136c2ee4cSMarek Vasut DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 21236c2ee4cSMarek Vasut DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 21336c2ee4cSMarek Vasut DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 21436c2ee4cSMarek Vasut DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 215*849ab0a6SMarek Vasut DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), 21636c2ee4cSMarek Vasut 21736c2ee4cSMarek Vasut /* Core Clock Outputs */ 218fd8692b8SMarek Vasut DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 219fd8692b8SMarek Vasut DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 220fd8692b8SMarek Vasut DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 221fd8692b8SMarek Vasut DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 222fd8692b8SMarek Vasut DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 223fd8692b8SMarek Vasut DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), 224fd8692b8SMarek Vasut DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), 225fd8692b8SMarek Vasut DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 226fd8692b8SMarek Vasut DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), 227fd8692b8SMarek Vasut DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), 228fd8692b8SMarek Vasut DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), 229fd8692b8SMarek Vasut DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 230fd8692b8SMarek Vasut DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 231fd8692b8SMarek Vasut DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 232fd8692b8SMarek Vasut DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), 233fd8692b8SMarek Vasut DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), 234fd8692b8SMarek Vasut DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), 235fd8692b8SMarek Vasut DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), 236fd8692b8SMarek Vasut DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 237fd8692b8SMarek Vasut DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 23836c2ee4cSMarek Vasut 239fd8692b8SMarek Vasut DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), 240fd8692b8SMarek Vasut DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), 241fd8692b8SMarek Vasut DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), 242fd8692b8SMarek Vasut DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), 24336c2ee4cSMarek Vasut 244*849ab0a6SMarek Vasut DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238), 245*849ab0a6SMarek Vasut 246fd8692b8SMarek Vasut DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 247fd8692b8SMarek Vasut DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 24836c2ee4cSMarek Vasut 24936c2ee4cSMarek Vasut /* NOTE: HDMI, CSI, CAN etc. clock are missing */ 25036c2ee4cSMarek Vasut 251fd8692b8SMarek Vasut DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 25236c2ee4cSMarek Vasut }; 25336c2ee4cSMarek Vasut 25436c2ee4cSMarek Vasut static const struct mssr_mod_clk r8a7795_mod_clks[] = { 25536c2ee4cSMarek Vasut DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ 25636c2ee4cSMarek Vasut DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), 25736c2ee4cSMarek Vasut DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), 25836c2ee4cSMarek Vasut DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 25936c2ee4cSMarek Vasut DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 26036c2ee4cSMarek Vasut DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 26136c2ee4cSMarek Vasut DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), 26236c2ee4cSMarek Vasut DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), 26336c2ee4cSMarek Vasut DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), 26436c2ee4cSMarek Vasut DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 26536c2ee4cSMarek Vasut DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 26636c2ee4cSMarek Vasut DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 26736c2ee4cSMarek Vasut DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), 26836c2ee4cSMarek Vasut DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), 26936c2ee4cSMarek Vasut DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), 27036c2ee4cSMarek Vasut DEF_MOD("cmt3", 300, R8A7795_CLK_R), 27136c2ee4cSMarek Vasut DEF_MOD("cmt2", 301, R8A7795_CLK_R), 27236c2ee4cSMarek Vasut DEF_MOD("cmt1", 302, R8A7795_CLK_R), 27336c2ee4cSMarek Vasut DEF_MOD("cmt0", 303, R8A7795_CLK_R), 27436c2ee4cSMarek Vasut DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), 27536c2ee4cSMarek Vasut DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), 27636c2ee4cSMarek Vasut DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), 27736c2ee4cSMarek Vasut DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), 27836c2ee4cSMarek Vasut DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 27936c2ee4cSMarek Vasut DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 28036c2ee4cSMarek Vasut DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 28136c2ee4cSMarek Vasut DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), 28236c2ee4cSMarek Vasut DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ 28336c2ee4cSMarek Vasut DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 28436c2ee4cSMarek Vasut DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), 28536c2ee4cSMarek Vasut DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 28636c2ee4cSMarek Vasut DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 28736c2ee4cSMarek Vasut DEF_MOD("rwdt", 402, R8A7795_CLK_R), 28836c2ee4cSMarek Vasut DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 28936c2ee4cSMarek Vasut DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 29036c2ee4cSMarek Vasut DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), 29136c2ee4cSMarek Vasut DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), 29236c2ee4cSMarek Vasut DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), 29336c2ee4cSMarek Vasut DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), 29436c2ee4cSMarek Vasut DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), 29536c2ee4cSMarek Vasut DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), 29636c2ee4cSMarek Vasut DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), 29736c2ee4cSMarek Vasut DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), 29836c2ee4cSMarek Vasut DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), 29936c2ee4cSMarek Vasut DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), 30036c2ee4cSMarek Vasut DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), 30136c2ee4cSMarek Vasut DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), 30236c2ee4cSMarek Vasut DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), 30336c2ee4cSMarek Vasut DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), 30436c2ee4cSMarek Vasut DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 30536c2ee4cSMarek Vasut DEF_MOD("thermal", 522, R8A7795_CLK_CP), 30636c2ee4cSMarek Vasut DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), 30736c2ee4cSMarek Vasut DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ 30836c2ee4cSMarek Vasut DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), 30936c2ee4cSMarek Vasut DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), 31036c2ee4cSMarek Vasut DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), 31136c2ee4cSMarek Vasut DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), 31236c2ee4cSMarek Vasut DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), 31336c2ee4cSMarek Vasut DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ 31436c2ee4cSMarek Vasut DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), 31536c2ee4cSMarek Vasut DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), 31636c2ee4cSMarek Vasut DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ 31736c2ee4cSMarek Vasut DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), 31836c2ee4cSMarek Vasut DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), 31936c2ee4cSMarek Vasut DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ 32036c2ee4cSMarek Vasut DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ 32136c2ee4cSMarek Vasut DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), 32236c2ee4cSMarek Vasut DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ 32336c2ee4cSMarek Vasut DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), 32436c2ee4cSMarek Vasut DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), 32536c2ee4cSMarek Vasut DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), 32636c2ee4cSMarek Vasut DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), 32736c2ee4cSMarek Vasut DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), 32836c2ee4cSMarek Vasut DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ 32936c2ee4cSMarek Vasut DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), 33036c2ee4cSMarek Vasut DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), 33136c2ee4cSMarek Vasut DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), 33236c2ee4cSMarek Vasut DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), 33336c2ee4cSMarek Vasut DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), 33436c2ee4cSMarek Vasut DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), 33536c2ee4cSMarek Vasut DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), 33636c2ee4cSMarek Vasut DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), 33736c2ee4cSMarek Vasut DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ 33836c2ee4cSMarek Vasut DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 33936c2ee4cSMarek Vasut DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 34036c2ee4cSMarek Vasut DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), 34136c2ee4cSMarek Vasut DEF_MOD("du3", 721, R8A7795_CLK_S2D1), 34236c2ee4cSMarek Vasut DEF_MOD("du2", 722, R8A7795_CLK_S2D1), 34336c2ee4cSMarek Vasut DEF_MOD("du1", 723, R8A7795_CLK_S2D1), 34436c2ee4cSMarek Vasut DEF_MOD("du0", 724, R8A7795_CLK_S2D1), 34536c2ee4cSMarek Vasut DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), 34636c2ee4cSMarek Vasut DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 34736c2ee4cSMarek Vasut DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 34836c2ee4cSMarek Vasut DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), 34936c2ee4cSMarek Vasut DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), 35036c2ee4cSMarek Vasut DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), 35136c2ee4cSMarek Vasut DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), 35236c2ee4cSMarek Vasut DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), 35336c2ee4cSMarek Vasut DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), 35436c2ee4cSMarek Vasut DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), 35536c2ee4cSMarek Vasut DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), 35636c2ee4cSMarek Vasut DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), 35736c2ee4cSMarek Vasut DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 35836c2ee4cSMarek Vasut DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), 35936c2ee4cSMarek Vasut DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), 36036c2ee4cSMarek Vasut DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), 36136c2ee4cSMarek Vasut DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), 36236c2ee4cSMarek Vasut DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), 36336c2ee4cSMarek Vasut DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), 36436c2ee4cSMarek Vasut DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), 36536c2ee4cSMarek Vasut DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), 36636c2ee4cSMarek Vasut DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), 36736c2ee4cSMarek Vasut DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), 36836c2ee4cSMarek Vasut DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), 36936c2ee4cSMarek Vasut DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), 37036c2ee4cSMarek Vasut DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), 37136c2ee4cSMarek Vasut DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), 37236c2ee4cSMarek Vasut DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), 373*849ab0a6SMarek Vasut DEF_MOD("rpc", 917, R8A7795_CLK_RPC), 37436c2ee4cSMarek Vasut DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), 37536c2ee4cSMarek Vasut DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), 37636c2ee4cSMarek Vasut DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), 37736c2ee4cSMarek Vasut DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), 37836c2ee4cSMarek Vasut DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), 37936c2ee4cSMarek Vasut DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), 38036c2ee4cSMarek Vasut DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), 38136c2ee4cSMarek Vasut DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), 38236c2ee4cSMarek Vasut DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), 38336c2ee4cSMarek Vasut DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 38436c2ee4cSMarek Vasut DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 38536c2ee4cSMarek Vasut DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 38636c2ee4cSMarek Vasut DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 38736c2ee4cSMarek Vasut DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 38836c2ee4cSMarek Vasut DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 38936c2ee4cSMarek Vasut DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 39036c2ee4cSMarek Vasut DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 39136c2ee4cSMarek Vasut DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 39236c2ee4cSMarek Vasut DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 39336c2ee4cSMarek Vasut DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), 39436c2ee4cSMarek Vasut DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 39536c2ee4cSMarek Vasut DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 39636c2ee4cSMarek Vasut DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 39736c2ee4cSMarek Vasut DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 39836c2ee4cSMarek Vasut DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 39936c2ee4cSMarek Vasut DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 40036c2ee4cSMarek Vasut DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 40136c2ee4cSMarek Vasut DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 40236c2ee4cSMarek Vasut DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 40336c2ee4cSMarek Vasut DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 40436c2ee4cSMarek Vasut DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 40536c2ee4cSMarek Vasut DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 40636c2ee4cSMarek Vasut DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 40736c2ee4cSMarek Vasut DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 40836c2ee4cSMarek Vasut }; 40936c2ee4cSMarek Vasut 410fd8692b8SMarek Vasut static const struct cpg_core_clk r8a7796_core_clks[] = { 411fd8692b8SMarek Vasut /* External Clock Inputs */ 412fd8692b8SMarek Vasut DEF_INPUT("extal", CLK_EXTAL), 413fd8692b8SMarek Vasut DEF_INPUT("extalr", CLK_EXTALR), 414fd8692b8SMarek Vasut 415fd8692b8SMarek Vasut /* Internal Core Clocks */ 416fd8692b8SMarek Vasut DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 417fd8692b8SMarek Vasut DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 418fd8692b8SMarek Vasut DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 419fd8692b8SMarek Vasut DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 420fd8692b8SMarek Vasut DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 421fd8692b8SMarek Vasut DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 422fd8692b8SMarek Vasut 423fd8692b8SMarek Vasut DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 424fd8692b8SMarek Vasut DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 425fd8692b8SMarek Vasut DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 426fd8692b8SMarek Vasut DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 427fd8692b8SMarek Vasut DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 428fd8692b8SMarek Vasut DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 429fd8692b8SMarek Vasut DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 430*849ab0a6SMarek Vasut DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), 431fd8692b8SMarek Vasut 432fd8692b8SMarek Vasut /* Core Clock Outputs */ 433fd8692b8SMarek Vasut DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 434fd8692b8SMarek Vasut DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 435fd8692b8SMarek Vasut DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 436fd8692b8SMarek Vasut DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 437fd8692b8SMarek Vasut DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1), 438fd8692b8SMarek Vasut DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1), 439fd8692b8SMarek Vasut DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1), 440fd8692b8SMarek Vasut DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1), 441fd8692b8SMarek Vasut DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1), 442fd8692b8SMarek Vasut DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1), 443fd8692b8SMarek Vasut DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1), 444fd8692b8SMarek Vasut DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1), 445fd8692b8SMarek Vasut DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1), 446fd8692b8SMarek Vasut DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1), 447fd8692b8SMarek Vasut DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1), 448fd8692b8SMarek Vasut DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1), 449fd8692b8SMarek Vasut DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1), 450fd8692b8SMarek Vasut DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1), 451fd8692b8SMarek Vasut DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), 452fd8692b8SMarek Vasut DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), 453fd8692b8SMarek Vasut 454fd8692b8SMarek Vasut DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), 455fd8692b8SMarek Vasut DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), 456fd8692b8SMarek Vasut DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), 457fd8692b8SMarek Vasut DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), 458fd8692b8SMarek Vasut 459*849ab0a6SMarek Vasut DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238), 460*849ab0a6SMarek Vasut 461fd8692b8SMarek Vasut DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), 462fd8692b8SMarek Vasut DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), 463fd8692b8SMarek Vasut 464fd8692b8SMarek Vasut /* NOTE: HDMI, CSI, CAN etc. clock are missing */ 465fd8692b8SMarek Vasut 466fd8692b8SMarek Vasut DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 467fd8692b8SMarek Vasut }; 468fd8692b8SMarek Vasut 46936c2ee4cSMarek Vasut static const struct mssr_mod_clk r8a7796_mod_clks[] = { 47036c2ee4cSMarek Vasut DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), 47136c2ee4cSMarek Vasut DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), 47236c2ee4cSMarek Vasut DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), 47336c2ee4cSMarek Vasut DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), 47436c2ee4cSMarek Vasut DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), 47536c2ee4cSMarek Vasut DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), 47636c2ee4cSMarek Vasut DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), 47736c2ee4cSMarek Vasut DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), 47836c2ee4cSMarek Vasut DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), 47936c2ee4cSMarek Vasut DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), 48036c2ee4cSMarek Vasut DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), 48136c2ee4cSMarek Vasut DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), 48236c2ee4cSMarek Vasut DEF_MOD("cmt3", 300, R8A7796_CLK_R), 48336c2ee4cSMarek Vasut DEF_MOD("cmt2", 301, R8A7796_CLK_R), 48436c2ee4cSMarek Vasut DEF_MOD("cmt1", 302, R8A7796_CLK_R), 48536c2ee4cSMarek Vasut DEF_MOD("cmt0", 303, R8A7796_CLK_R), 48636c2ee4cSMarek Vasut DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), 48736c2ee4cSMarek Vasut DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), 48836c2ee4cSMarek Vasut DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), 48936c2ee4cSMarek Vasut DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), 49036c2ee4cSMarek Vasut DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), 49136c2ee4cSMarek Vasut DEF_MOD("pcie1", 318, R8A7796_CLK_S3D1), 49236c2ee4cSMarek Vasut DEF_MOD("pcie0", 319, R8A7796_CLK_S3D1), 49336c2ee4cSMarek Vasut DEF_MOD("usb-dmac0", 330, R8A7796_CLK_S3D1), 49436c2ee4cSMarek Vasut DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), 49536c2ee4cSMarek Vasut DEF_MOD("rwdt", 402, R8A7796_CLK_R), 49636c2ee4cSMarek Vasut DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), 49736c2ee4cSMarek Vasut DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), 49836c2ee4cSMarek Vasut DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), 49936c2ee4cSMarek Vasut DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), 50036c2ee4cSMarek Vasut DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), 50136c2ee4cSMarek Vasut DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), 50236c2ee4cSMarek Vasut DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), 50336c2ee4cSMarek Vasut DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), 50436c2ee4cSMarek Vasut DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), 50536c2ee4cSMarek Vasut DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), 50636c2ee4cSMarek Vasut DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), 50736c2ee4cSMarek Vasut DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), 50836c2ee4cSMarek Vasut DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), 50936c2ee4cSMarek Vasut DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), 51036c2ee4cSMarek Vasut DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), 51136c2ee4cSMarek Vasut DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), 51236c2ee4cSMarek Vasut DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), 51336c2ee4cSMarek Vasut DEF_MOD("thermal", 522, R8A7796_CLK_CP), 51436c2ee4cSMarek Vasut DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), 51536c2ee4cSMarek Vasut DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), 51636c2ee4cSMarek Vasut DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), 51736c2ee4cSMarek Vasut DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2), 51836c2ee4cSMarek Vasut DEF_MOD("fcpvb0", 607, R8A7796_CLK_S0D1), 51936c2ee4cSMarek Vasut DEF_MOD("fcpvi0", 611, R8A7796_CLK_S0D1), 52036c2ee4cSMarek Vasut DEF_MOD("fcpf0", 615, R8A7796_CLK_S0D1), 52136c2ee4cSMarek Vasut DEF_MOD("fcpci0", 617, R8A7796_CLK_S0D2), 52236c2ee4cSMarek Vasut DEF_MOD("fcpcs", 619, R8A7796_CLK_S0D2), 52336c2ee4cSMarek Vasut DEF_MOD("vspd2", 621, R8A7796_CLK_S0D2), 52436c2ee4cSMarek Vasut DEF_MOD("vspd1", 622, R8A7796_CLK_S0D2), 52536c2ee4cSMarek Vasut DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), 52636c2ee4cSMarek Vasut DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), 52736c2ee4cSMarek Vasut DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), 52836c2ee4cSMarek Vasut DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), 52936c2ee4cSMarek Vasut DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), 53036c2ee4cSMarek Vasut DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), 53136c2ee4cSMarek Vasut DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), 53236c2ee4cSMarek Vasut DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), 53336c2ee4cSMarek Vasut DEF_MOD("du2", 722, R8A7796_CLK_S2D1), 53436c2ee4cSMarek Vasut DEF_MOD("du1", 723, R8A7796_CLK_S2D1), 53536c2ee4cSMarek Vasut DEF_MOD("du0", 724, R8A7796_CLK_S2D1), 53636c2ee4cSMarek Vasut DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), 53736c2ee4cSMarek Vasut DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), 53836c2ee4cSMarek Vasut DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), 53936c2ee4cSMarek Vasut DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), 54036c2ee4cSMarek Vasut DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), 54136c2ee4cSMarek Vasut DEF_MOD("vin4", 807, R8A7796_CLK_S0D2), 54236c2ee4cSMarek Vasut DEF_MOD("vin3", 808, R8A7796_CLK_S0D2), 54336c2ee4cSMarek Vasut DEF_MOD("vin2", 809, R8A7796_CLK_S0D2), 54436c2ee4cSMarek Vasut DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), 54536c2ee4cSMarek Vasut DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), 54636c2ee4cSMarek Vasut DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), 54736c2ee4cSMarek Vasut DEF_MOD("imr1", 822, R8A7796_CLK_S0D2), 54836c2ee4cSMarek Vasut DEF_MOD("imr0", 823, R8A7796_CLK_S0D2), 54936c2ee4cSMarek Vasut DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), 55036c2ee4cSMarek Vasut DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), 55136c2ee4cSMarek Vasut DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), 55236c2ee4cSMarek Vasut DEF_MOD("gpio4", 908, R8A7796_CLK_S3D4), 55336c2ee4cSMarek Vasut DEF_MOD("gpio3", 909, R8A7796_CLK_S3D4), 55436c2ee4cSMarek Vasut DEF_MOD("gpio2", 910, R8A7796_CLK_S3D4), 55536c2ee4cSMarek Vasut DEF_MOD("gpio1", 911, R8A7796_CLK_S3D4), 55636c2ee4cSMarek Vasut DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), 55736c2ee4cSMarek Vasut DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), 55836c2ee4cSMarek Vasut DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), 55936c2ee4cSMarek Vasut DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), 560*849ab0a6SMarek Vasut DEF_MOD("rpc", 917, R8A7795_CLK_RPC), 56136c2ee4cSMarek Vasut DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), 56236c2ee4cSMarek Vasut DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), 56336c2ee4cSMarek Vasut DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), 56436c2ee4cSMarek Vasut DEF_MOD("i2c4", 927, R8A7796_CLK_S0D6), 56536c2ee4cSMarek Vasut DEF_MOD("i2c3", 928, R8A7796_CLK_S0D6), 56636c2ee4cSMarek Vasut DEF_MOD("i2c2", 929, R8A7796_CLK_S3D2), 56736c2ee4cSMarek Vasut DEF_MOD("i2c1", 930, R8A7796_CLK_S3D2), 56836c2ee4cSMarek Vasut DEF_MOD("i2c0", 931, R8A7796_CLK_S3D2), 56936c2ee4cSMarek Vasut DEF_MOD("ssi-all", 1005, R8A7796_CLK_S3D4), 57036c2ee4cSMarek Vasut DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 57136c2ee4cSMarek Vasut DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 57236c2ee4cSMarek Vasut DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 57336c2ee4cSMarek Vasut DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 57436c2ee4cSMarek Vasut DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 57536c2ee4cSMarek Vasut DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 57636c2ee4cSMarek Vasut DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 57736c2ee4cSMarek Vasut DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 57836c2ee4cSMarek Vasut DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 57936c2ee4cSMarek Vasut DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 58036c2ee4cSMarek Vasut DEF_MOD("scu-all", 1017, R8A7796_CLK_S3D4), 58136c2ee4cSMarek Vasut DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 58236c2ee4cSMarek Vasut DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 58336c2ee4cSMarek Vasut DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 58436c2ee4cSMarek Vasut DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 58536c2ee4cSMarek Vasut DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 58636c2ee4cSMarek Vasut DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 58736c2ee4cSMarek Vasut DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 58836c2ee4cSMarek Vasut DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 58936c2ee4cSMarek Vasut DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 59036c2ee4cSMarek Vasut DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 59136c2ee4cSMarek Vasut DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 59236c2ee4cSMarek Vasut DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 59336c2ee4cSMarek Vasut DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 59436c2ee4cSMarek Vasut DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 59536c2ee4cSMarek Vasut }; 59636c2ee4cSMarek Vasut 59736c2ee4cSMarek Vasut /* 59836c2ee4cSMarek Vasut * CPG Clock Data 59936c2ee4cSMarek Vasut */ 60036c2ee4cSMarek Vasut 60136c2ee4cSMarek Vasut /* 60236c2ee4cSMarek Vasut * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 60336c2ee4cSMarek Vasut * 14 13 19 17 (MHz) 60436c2ee4cSMarek Vasut *------------------------------------------------------------------- 60536c2ee4cSMarek Vasut * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 60636c2ee4cSMarek Vasut * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 60736c2ee4cSMarek Vasut * 0 0 1 0 Prohibited setting 60836c2ee4cSMarek Vasut * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 60936c2ee4cSMarek Vasut * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 61036c2ee4cSMarek Vasut * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 61136c2ee4cSMarek Vasut * 0 1 1 0 Prohibited setting 61236c2ee4cSMarek Vasut * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 61336c2ee4cSMarek Vasut * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 61436c2ee4cSMarek Vasut * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 61536c2ee4cSMarek Vasut * 1 0 1 0 Prohibited setting 61636c2ee4cSMarek Vasut * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 61736c2ee4cSMarek Vasut * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 61836c2ee4cSMarek Vasut * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 61936c2ee4cSMarek Vasut * 1 1 1 0 Prohibited setting 62036c2ee4cSMarek Vasut * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 62136c2ee4cSMarek Vasut */ 62236c2ee4cSMarek Vasut #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 62336c2ee4cSMarek Vasut (((md) & BIT(13)) >> 11) | \ 62436c2ee4cSMarek Vasut (((md) & BIT(19)) >> 18) | \ 62536c2ee4cSMarek Vasut (((md) & BIT(17)) >> 17)) 62636c2ee4cSMarek Vasut 62736c2ee4cSMarek Vasut static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { 62836c2ee4cSMarek Vasut /* EXTAL div PLL1 mult PLL3 mult */ 62936c2ee4cSMarek Vasut { 1, 192, 192, }, 63036c2ee4cSMarek Vasut { 1, 192, 128, }, 63136c2ee4cSMarek Vasut { 0, /* Prohibited setting */ }, 63236c2ee4cSMarek Vasut { 1, 192, 192, }, 63336c2ee4cSMarek Vasut { 1, 160, 160, }, 63436c2ee4cSMarek Vasut { 1, 160, 106, }, 63536c2ee4cSMarek Vasut { 0, /* Prohibited setting */ }, 63636c2ee4cSMarek Vasut { 1, 160, 160, }, 63736c2ee4cSMarek Vasut { 1, 128, 128, }, 63836c2ee4cSMarek Vasut { 1, 128, 84, }, 63936c2ee4cSMarek Vasut { 0, /* Prohibited setting */ }, 64036c2ee4cSMarek Vasut { 1, 128, 128, }, 64136c2ee4cSMarek Vasut { 2, 192, 192, }, 64236c2ee4cSMarek Vasut { 2, 192, 128, }, 64336c2ee4cSMarek Vasut { 0, /* Prohibited setting */ }, 64436c2ee4cSMarek Vasut { 2, 192, 192, }, 64536c2ee4cSMarek Vasut }; 64636c2ee4cSMarek Vasut 64736c2ee4cSMarek Vasut /* 64836c2ee4cSMarek Vasut * SDn Clock 64936c2ee4cSMarek Vasut */ 65036c2ee4cSMarek Vasut #define CPG_SD_STP_HCK BIT(9) 65136c2ee4cSMarek Vasut #define CPG_SD_STP_CK BIT(8) 65236c2ee4cSMarek Vasut 65336c2ee4cSMarek Vasut #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) 65436c2ee4cSMarek Vasut #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) 65536c2ee4cSMarek Vasut 65636c2ee4cSMarek Vasut #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ 65736c2ee4cSMarek Vasut { \ 65836c2ee4cSMarek Vasut .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ 65936c2ee4cSMarek Vasut ((stp_ck) ? CPG_SD_STP_CK : 0) | \ 66036c2ee4cSMarek Vasut ((sd_srcfc) << 2) | \ 66136c2ee4cSMarek Vasut ((sd_fc) << 0), \ 66236c2ee4cSMarek Vasut .div = (sd_div), \ 66336c2ee4cSMarek Vasut } 66436c2ee4cSMarek Vasut 66536c2ee4cSMarek Vasut struct sd_div_table { 66636c2ee4cSMarek Vasut u32 val; 66736c2ee4cSMarek Vasut unsigned int div; 66836c2ee4cSMarek Vasut }; 66936c2ee4cSMarek Vasut 67036c2ee4cSMarek Vasut /* SDn divider 67136c2ee4cSMarek Vasut * sd_srcfc sd_fc div 67236c2ee4cSMarek Vasut * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc 67336c2ee4cSMarek Vasut *------------------------------------------------------------------- 67436c2ee4cSMarek Vasut * 0 0 0 (1) 1 (4) 4 67536c2ee4cSMarek Vasut * 0 0 1 (2) 1 (4) 8 67636c2ee4cSMarek Vasut * 1 0 2 (4) 1 (4) 16 67736c2ee4cSMarek Vasut * 1 0 3 (8) 1 (4) 32 67836c2ee4cSMarek Vasut * 1 0 4 (16) 1 (4) 64 67936c2ee4cSMarek Vasut * 0 0 0 (1) 0 (2) 2 68036c2ee4cSMarek Vasut * 0 0 1 (2) 0 (2) 4 68136c2ee4cSMarek Vasut * 1 0 2 (4) 0 (2) 8 68236c2ee4cSMarek Vasut * 1 0 3 (8) 0 (2) 16 68336c2ee4cSMarek Vasut * 1 0 4 (16) 0 (2) 32 68436c2ee4cSMarek Vasut */ 68536c2ee4cSMarek Vasut static const struct sd_div_table cpg_sd_div_table[] = { 68636c2ee4cSMarek Vasut /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ 68736c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), 68836c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), 68936c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), 69036c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), 69136c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), 69236c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), 69336c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), 69436c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), 69536c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), 69636c2ee4cSMarek Vasut CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), 69736c2ee4cSMarek Vasut }; 69836c2ee4cSMarek Vasut 69936c2ee4cSMarek Vasut static bool gen3_clk_is_mod(struct clk *clk) 70036c2ee4cSMarek Vasut { 70136c2ee4cSMarek Vasut return (clk->id >> 16) == CPG_MOD; 70236c2ee4cSMarek Vasut } 70336c2ee4cSMarek Vasut 70436c2ee4cSMarek Vasut static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr) 70536c2ee4cSMarek Vasut { 70636c2ee4cSMarek Vasut struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 70736c2ee4cSMarek Vasut const unsigned long clkid = clk->id & 0xffff; 70836c2ee4cSMarek Vasut int i; 70936c2ee4cSMarek Vasut 71036c2ee4cSMarek Vasut if (!gen3_clk_is_mod(clk)) 71136c2ee4cSMarek Vasut return -EINVAL; 71236c2ee4cSMarek Vasut 71336c2ee4cSMarek Vasut for (i = 0; i < priv->mod_clk_size; i++) { 71436c2ee4cSMarek Vasut if (priv->mod_clk[i].id != MOD_CLK_ID(clkid)) 71536c2ee4cSMarek Vasut continue; 71636c2ee4cSMarek Vasut 71736c2ee4cSMarek Vasut *mssr = &priv->mod_clk[i]; 71836c2ee4cSMarek Vasut return 0; 71936c2ee4cSMarek Vasut } 72036c2ee4cSMarek Vasut 72136c2ee4cSMarek Vasut return -ENODEV; 72236c2ee4cSMarek Vasut } 72336c2ee4cSMarek Vasut 72436c2ee4cSMarek Vasut static int gen3_clk_get_core(struct clk *clk, const struct cpg_core_clk **core) 72536c2ee4cSMarek Vasut { 726fd8692b8SMarek Vasut struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 72736c2ee4cSMarek Vasut const unsigned long clkid = clk->id & 0xffff; 72836c2ee4cSMarek Vasut int i; 72936c2ee4cSMarek Vasut 73036c2ee4cSMarek Vasut if (gen3_clk_is_mod(clk)) 73136c2ee4cSMarek Vasut return -EINVAL; 73236c2ee4cSMarek Vasut 733fd8692b8SMarek Vasut for (i = 0; i < priv->core_clk_size; i++) { 734fd8692b8SMarek Vasut if (priv->core_clk[i].id != clkid) 73536c2ee4cSMarek Vasut continue; 73636c2ee4cSMarek Vasut 737fd8692b8SMarek Vasut *core = &priv->core_clk[i]; 73836c2ee4cSMarek Vasut return 0; 73936c2ee4cSMarek Vasut } 74036c2ee4cSMarek Vasut 74136c2ee4cSMarek Vasut return -ENODEV; 74236c2ee4cSMarek Vasut } 74336c2ee4cSMarek Vasut 74436c2ee4cSMarek Vasut static int gen3_clk_get_parent(struct clk *clk, struct clk *parent) 74536c2ee4cSMarek Vasut { 74636c2ee4cSMarek Vasut const struct cpg_core_clk *core; 74736c2ee4cSMarek Vasut const struct mssr_mod_clk *mssr; 74836c2ee4cSMarek Vasut int ret; 74936c2ee4cSMarek Vasut 75036c2ee4cSMarek Vasut if (gen3_clk_is_mod(clk)) { 75136c2ee4cSMarek Vasut ret = gen3_clk_get_mod(clk, &mssr); 75236c2ee4cSMarek Vasut if (ret) 75336c2ee4cSMarek Vasut return ret; 75436c2ee4cSMarek Vasut 75536c2ee4cSMarek Vasut parent->id = mssr->parent; 75636c2ee4cSMarek Vasut } else { 75736c2ee4cSMarek Vasut ret = gen3_clk_get_core(clk, &core); 75836c2ee4cSMarek Vasut if (ret) 75936c2ee4cSMarek Vasut return ret; 76036c2ee4cSMarek Vasut 76136c2ee4cSMarek Vasut if (core->type == CLK_TYPE_IN) 76236c2ee4cSMarek Vasut parent->id = ~0; /* Top-level clock */ 76336c2ee4cSMarek Vasut else 76436c2ee4cSMarek Vasut parent->id = core->parent; 76536c2ee4cSMarek Vasut } 76636c2ee4cSMarek Vasut 76736c2ee4cSMarek Vasut parent->dev = clk->dev; 76836c2ee4cSMarek Vasut 76936c2ee4cSMarek Vasut return 0; 77036c2ee4cSMarek Vasut } 77136c2ee4cSMarek Vasut 7724b20eef3SMarek Vasut static int gen3_clk_setup_sdif_div(struct clk *clk) 7734b20eef3SMarek Vasut { 7744b20eef3SMarek Vasut struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 7754b20eef3SMarek Vasut const struct cpg_core_clk *core; 7764b20eef3SMarek Vasut struct clk parent; 7774b20eef3SMarek Vasut int ret; 7784b20eef3SMarek Vasut 7794b20eef3SMarek Vasut ret = gen3_clk_get_parent(clk, &parent); 7804b20eef3SMarek Vasut if (ret) { 7814b20eef3SMarek Vasut printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); 7824b20eef3SMarek Vasut return ret; 7834b20eef3SMarek Vasut } 7844b20eef3SMarek Vasut 7854b20eef3SMarek Vasut if (gen3_clk_is_mod(&parent)) 7864b20eef3SMarek Vasut return 0; 7874b20eef3SMarek Vasut 7884b20eef3SMarek Vasut ret = gen3_clk_get_core(&parent, &core); 7894b20eef3SMarek Vasut if (ret) 7904b20eef3SMarek Vasut return ret; 7914b20eef3SMarek Vasut 7924b20eef3SMarek Vasut if (core->type != CLK_TYPE_GEN3_SD) 7934b20eef3SMarek Vasut return 0; 7944b20eef3SMarek Vasut 7954b20eef3SMarek Vasut debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); 7964b20eef3SMarek Vasut 7974b20eef3SMarek Vasut writel(1, priv->base + core->offset); 7984b20eef3SMarek Vasut 7994b20eef3SMarek Vasut return 0; 8004b20eef3SMarek Vasut } 8014b20eef3SMarek Vasut 80236c2ee4cSMarek Vasut static int gen3_clk_endisable(struct clk *clk, bool enable) 80336c2ee4cSMarek Vasut { 80436c2ee4cSMarek Vasut struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 80536c2ee4cSMarek Vasut const unsigned long clkid = clk->id & 0xffff; 80636c2ee4cSMarek Vasut const unsigned int reg = clkid / 100; 80736c2ee4cSMarek Vasut const unsigned int bit = clkid % 100; 80836c2ee4cSMarek Vasut const u32 bitmask = BIT(bit); 8094b20eef3SMarek Vasut int ret; 81036c2ee4cSMarek Vasut 81136c2ee4cSMarek Vasut if (!gen3_clk_is_mod(clk)) 81236c2ee4cSMarek Vasut return -EINVAL; 81336c2ee4cSMarek Vasut 81436c2ee4cSMarek Vasut debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__, 81536c2ee4cSMarek Vasut clkid, reg, bit, enable ? "ON" : "OFF"); 81636c2ee4cSMarek Vasut 81736c2ee4cSMarek Vasut if (enable) { 8184b20eef3SMarek Vasut ret = gen3_clk_setup_sdif_div(clk); 8194b20eef3SMarek Vasut if (ret) 8204b20eef3SMarek Vasut return ret; 82136c2ee4cSMarek Vasut clrbits_le32(priv->base + SMSTPCR(reg), bitmask); 82236c2ee4cSMarek Vasut return wait_for_bit("MSTP", priv->base + MSTPSR(reg), 82336c2ee4cSMarek Vasut bitmask, 0, 100, 0); 82436c2ee4cSMarek Vasut } else { 82536c2ee4cSMarek Vasut setbits_le32(priv->base + SMSTPCR(reg), bitmask); 82636c2ee4cSMarek Vasut return 0; 82736c2ee4cSMarek Vasut } 82836c2ee4cSMarek Vasut } 82936c2ee4cSMarek Vasut 83036c2ee4cSMarek Vasut static int gen3_clk_enable(struct clk *clk) 83136c2ee4cSMarek Vasut { 83236c2ee4cSMarek Vasut return gen3_clk_endisable(clk, true); 83336c2ee4cSMarek Vasut } 83436c2ee4cSMarek Vasut 83536c2ee4cSMarek Vasut static int gen3_clk_disable(struct clk *clk) 83636c2ee4cSMarek Vasut { 83736c2ee4cSMarek Vasut return gen3_clk_endisable(clk, false); 83836c2ee4cSMarek Vasut } 83936c2ee4cSMarek Vasut 84036c2ee4cSMarek Vasut static ulong gen3_clk_get_rate(struct clk *clk) 84136c2ee4cSMarek Vasut { 84236c2ee4cSMarek Vasut struct gen3_clk_priv *priv = dev_get_priv(clk->dev); 84336c2ee4cSMarek Vasut struct clk parent; 84436c2ee4cSMarek Vasut const struct cpg_core_clk *core; 84536c2ee4cSMarek Vasut const struct rcar_gen3_cpg_pll_config *pll_config = 84636c2ee4cSMarek Vasut priv->cpg_pll_config; 847*849ab0a6SMarek Vasut u32 value, mult, prediv, postdiv, rate = 0; 84836c2ee4cSMarek Vasut int i, ret; 84936c2ee4cSMarek Vasut 85036c2ee4cSMarek Vasut debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); 85136c2ee4cSMarek Vasut 85236c2ee4cSMarek Vasut ret = gen3_clk_get_parent(clk, &parent); 85336c2ee4cSMarek Vasut if (ret) { 85436c2ee4cSMarek Vasut printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); 85536c2ee4cSMarek Vasut return ret; 85636c2ee4cSMarek Vasut } 85736c2ee4cSMarek Vasut 85836c2ee4cSMarek Vasut if (gen3_clk_is_mod(clk)) { 85936c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent); 86036c2ee4cSMarek Vasut debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", 86136c2ee4cSMarek Vasut __func__, __LINE__, parent.id, rate); 86236c2ee4cSMarek Vasut return rate; 86336c2ee4cSMarek Vasut } 86436c2ee4cSMarek Vasut 86536c2ee4cSMarek Vasut ret = gen3_clk_get_core(clk, &core); 86636c2ee4cSMarek Vasut if (ret) 86736c2ee4cSMarek Vasut return ret; 86836c2ee4cSMarek Vasut 86936c2ee4cSMarek Vasut switch (core->type) { 87036c2ee4cSMarek Vasut case CLK_TYPE_IN: 87136c2ee4cSMarek Vasut if (core->id == CLK_EXTAL) { 87236c2ee4cSMarek Vasut rate = clk_get_rate(&priv->clk_extal); 87336c2ee4cSMarek Vasut debug("%s[%i] EXTAL clk: rate=%u\n", 87436c2ee4cSMarek Vasut __func__, __LINE__, rate); 87536c2ee4cSMarek Vasut return rate; 87636c2ee4cSMarek Vasut } 87736c2ee4cSMarek Vasut 87836c2ee4cSMarek Vasut if (core->id == CLK_EXTALR) { 87936c2ee4cSMarek Vasut rate = clk_get_rate(&priv->clk_extalr); 88036c2ee4cSMarek Vasut debug("%s[%i] EXTALR clk: rate=%u\n", 88136c2ee4cSMarek Vasut __func__, __LINE__, rate); 88236c2ee4cSMarek Vasut return rate; 88336c2ee4cSMarek Vasut } 88436c2ee4cSMarek Vasut 88536c2ee4cSMarek Vasut return -EINVAL; 88636c2ee4cSMarek Vasut 88736c2ee4cSMarek Vasut case CLK_TYPE_GEN3_MAIN: 88836c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) / pll_config->extal_div; 88936c2ee4cSMarek Vasut debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", 89036c2ee4cSMarek Vasut __func__, __LINE__, 89136c2ee4cSMarek Vasut core->parent, pll_config->extal_div, rate); 89236c2ee4cSMarek Vasut return rate; 89336c2ee4cSMarek Vasut 89436c2ee4cSMarek Vasut case CLK_TYPE_GEN3_PLL0: 89536c2ee4cSMarek Vasut value = readl(priv->base + CPG_PLL0CR); 89636c2ee4cSMarek Vasut mult = (((value >> 24) & 0x7f) + 1) * 2; 89736c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) * mult; 89836c2ee4cSMarek Vasut debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", 89936c2ee4cSMarek Vasut __func__, __LINE__, core->parent, mult, rate); 90036c2ee4cSMarek Vasut return rate; 90136c2ee4cSMarek Vasut 90236c2ee4cSMarek Vasut case CLK_TYPE_GEN3_PLL1: 90336c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) * pll_config->pll1_mult; 90436c2ee4cSMarek Vasut debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", 90536c2ee4cSMarek Vasut __func__, __LINE__, 90636c2ee4cSMarek Vasut core->parent, pll_config->pll1_mult, rate); 90736c2ee4cSMarek Vasut return rate; 90836c2ee4cSMarek Vasut 90936c2ee4cSMarek Vasut case CLK_TYPE_GEN3_PLL2: 91036c2ee4cSMarek Vasut value = readl(priv->base + CPG_PLL2CR); 91136c2ee4cSMarek Vasut mult = (((value >> 24) & 0x7f) + 1) * 2; 91236c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) * mult; 91336c2ee4cSMarek Vasut debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%u\n", 91436c2ee4cSMarek Vasut __func__, __LINE__, core->parent, mult, rate); 91536c2ee4cSMarek Vasut return rate; 91636c2ee4cSMarek Vasut 91736c2ee4cSMarek Vasut case CLK_TYPE_GEN3_PLL3: 91836c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) * pll_config->pll3_mult; 91936c2ee4cSMarek Vasut debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", 92036c2ee4cSMarek Vasut __func__, __LINE__, 92136c2ee4cSMarek Vasut core->parent, pll_config->pll3_mult, rate); 92236c2ee4cSMarek Vasut return rate; 92336c2ee4cSMarek Vasut 92436c2ee4cSMarek Vasut case CLK_TYPE_GEN3_PLL4: 92536c2ee4cSMarek Vasut value = readl(priv->base + CPG_PLL4CR); 92636c2ee4cSMarek Vasut mult = (((value >> 24) & 0x7f) + 1) * 2; 92736c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) * mult; 92836c2ee4cSMarek Vasut debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%u\n", 92936c2ee4cSMarek Vasut __func__, __LINE__, core->parent, mult, rate); 93036c2ee4cSMarek Vasut return rate; 93136c2ee4cSMarek Vasut 93236c2ee4cSMarek Vasut case CLK_TYPE_FF: 93336c2ee4cSMarek Vasut rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div; 93436c2ee4cSMarek Vasut debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", 93536c2ee4cSMarek Vasut __func__, __LINE__, 93636c2ee4cSMarek Vasut core->parent, core->mult, core->div, rate); 93736c2ee4cSMarek Vasut return rate; 93836c2ee4cSMarek Vasut 93936c2ee4cSMarek Vasut case CLK_TYPE_GEN3_SD: /* FIXME */ 94036c2ee4cSMarek Vasut value = readl(priv->base + core->offset); 94136c2ee4cSMarek Vasut value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; 94236c2ee4cSMarek Vasut 94336c2ee4cSMarek Vasut for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) { 94436c2ee4cSMarek Vasut if (cpg_sd_div_table[i].val != value) 94536c2ee4cSMarek Vasut continue; 94636c2ee4cSMarek Vasut 94736c2ee4cSMarek Vasut rate = gen3_clk_get_rate(&parent) / 94836c2ee4cSMarek Vasut cpg_sd_div_table[i].div; 94936c2ee4cSMarek Vasut debug("%s[%i] SD clk: parent=%i div=%i => rate=%u\n", 95036c2ee4cSMarek Vasut __func__, __LINE__, 95136c2ee4cSMarek Vasut core->parent, cpg_sd_div_table[i].div, rate); 95236c2ee4cSMarek Vasut 95336c2ee4cSMarek Vasut return rate; 95436c2ee4cSMarek Vasut } 95536c2ee4cSMarek Vasut 95636c2ee4cSMarek Vasut return -EINVAL; 957*849ab0a6SMarek Vasut 958*849ab0a6SMarek Vasut case CLK_TYPE_GEN3_RPC: 959*849ab0a6SMarek Vasut rate = gen3_clk_get_rate(&parent); 960*849ab0a6SMarek Vasut 961*849ab0a6SMarek Vasut value = readl(priv->base + core->offset); 962*849ab0a6SMarek Vasut 963*849ab0a6SMarek Vasut prediv = (value >> CPG_RPC_PREDIV_OFFSET) & 964*849ab0a6SMarek Vasut CPG_RPC_PREDIV_MASK; 965*849ab0a6SMarek Vasut if (prediv == 2) 966*849ab0a6SMarek Vasut rate /= 5; 967*849ab0a6SMarek Vasut else if (prediv == 3) 968*849ab0a6SMarek Vasut rate /= 6; 969*849ab0a6SMarek Vasut else 970*849ab0a6SMarek Vasut return -EINVAL; 971*849ab0a6SMarek Vasut 972*849ab0a6SMarek Vasut postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & 973*849ab0a6SMarek Vasut CPG_RPC_POSTDIV_MASK; 974*849ab0a6SMarek Vasut rate /= postdiv + 1; 975*849ab0a6SMarek Vasut 976*849ab0a6SMarek Vasut debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%u\n", 977*849ab0a6SMarek Vasut __func__, __LINE__, 978*849ab0a6SMarek Vasut core->parent, prediv, postdiv, rate); 979*849ab0a6SMarek Vasut 980*849ab0a6SMarek Vasut return -EINVAL; 981*849ab0a6SMarek Vasut 98236c2ee4cSMarek Vasut } 98336c2ee4cSMarek Vasut 98436c2ee4cSMarek Vasut printf("%s[%i] unknown fail\n", __func__, __LINE__); 98536c2ee4cSMarek Vasut 98636c2ee4cSMarek Vasut return -ENOENT; 98736c2ee4cSMarek Vasut } 98836c2ee4cSMarek Vasut 98936c2ee4cSMarek Vasut static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) 99036c2ee4cSMarek Vasut { 99136c2ee4cSMarek Vasut return gen3_clk_get_rate(clk); 99236c2ee4cSMarek Vasut } 99336c2ee4cSMarek Vasut 99436c2ee4cSMarek Vasut static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) 99536c2ee4cSMarek Vasut { 99636c2ee4cSMarek Vasut if (args->args_count != 2) { 99736c2ee4cSMarek Vasut debug("Invaild args_count: %d\n", args->args_count); 99836c2ee4cSMarek Vasut return -EINVAL; 99936c2ee4cSMarek Vasut } 100036c2ee4cSMarek Vasut 100136c2ee4cSMarek Vasut clk->id = (args->args[0] << 16) | args->args[1]; 100236c2ee4cSMarek Vasut 100336c2ee4cSMarek Vasut return 0; 100436c2ee4cSMarek Vasut } 100536c2ee4cSMarek Vasut 100636c2ee4cSMarek Vasut static const struct clk_ops gen3_clk_ops = { 100736c2ee4cSMarek Vasut .enable = gen3_clk_enable, 100836c2ee4cSMarek Vasut .disable = gen3_clk_disable, 100936c2ee4cSMarek Vasut .get_rate = gen3_clk_get_rate, 101036c2ee4cSMarek Vasut .set_rate = gen3_clk_set_rate, 101136c2ee4cSMarek Vasut .of_xlate = gen3_clk_of_xlate, 101236c2ee4cSMarek Vasut }; 101336c2ee4cSMarek Vasut 101436c2ee4cSMarek Vasut enum gen3_clk_model { 101536c2ee4cSMarek Vasut CLK_R8A7795, 101636c2ee4cSMarek Vasut CLK_R8A7796, 101736c2ee4cSMarek Vasut }; 101836c2ee4cSMarek Vasut 101936c2ee4cSMarek Vasut static int gen3_clk_probe(struct udevice *dev) 102036c2ee4cSMarek Vasut { 102136c2ee4cSMarek Vasut struct gen3_clk_priv *priv = dev_get_priv(dev); 102236c2ee4cSMarek Vasut enum gen3_clk_model model = dev_get_driver_data(dev); 102336c2ee4cSMarek Vasut fdt_addr_t rst_base; 102436c2ee4cSMarek Vasut u32 cpg_mode; 102536c2ee4cSMarek Vasut int ret; 102636c2ee4cSMarek Vasut 102736c2ee4cSMarek Vasut priv->base = (struct gen3_base *)devfdt_get_addr(dev); 102836c2ee4cSMarek Vasut if (!priv->base) 102936c2ee4cSMarek Vasut return -EINVAL; 103036c2ee4cSMarek Vasut 103136c2ee4cSMarek Vasut switch (model) { 103236c2ee4cSMarek Vasut case CLK_R8A7795: 1033fd8692b8SMarek Vasut priv->core_clk = r8a7795_core_clks; 1034fd8692b8SMarek Vasut priv->core_clk_size = ARRAY_SIZE(r8a7795_core_clks); 103536c2ee4cSMarek Vasut priv->mod_clk = r8a7795_mod_clks; 103636c2ee4cSMarek Vasut priv->mod_clk_size = ARRAY_SIZE(r8a7795_mod_clks); 103736c2ee4cSMarek Vasut ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 103836c2ee4cSMarek Vasut "renesas,r8a7795-rst"); 103936c2ee4cSMarek Vasut if (ret < 0) 104036c2ee4cSMarek Vasut return ret; 104136c2ee4cSMarek Vasut break; 104236c2ee4cSMarek Vasut case CLK_R8A7796: 1043fd8692b8SMarek Vasut priv->core_clk = r8a7796_core_clks; 1044fd8692b8SMarek Vasut priv->core_clk_size = ARRAY_SIZE(r8a7796_core_clks); 104536c2ee4cSMarek Vasut priv->mod_clk = r8a7796_mod_clks; 104636c2ee4cSMarek Vasut priv->mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks); 104736c2ee4cSMarek Vasut ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 104836c2ee4cSMarek Vasut "renesas,r8a7796-rst"); 104936c2ee4cSMarek Vasut if (ret < 0) 105036c2ee4cSMarek Vasut return ret; 105136c2ee4cSMarek Vasut break; 105236c2ee4cSMarek Vasut default: 105336c2ee4cSMarek Vasut return -EINVAL; 105436c2ee4cSMarek Vasut } 105536c2ee4cSMarek Vasut 105636c2ee4cSMarek Vasut rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); 105736c2ee4cSMarek Vasut if (rst_base == FDT_ADDR_T_NONE) 105836c2ee4cSMarek Vasut return -EINVAL; 105936c2ee4cSMarek Vasut 106036c2ee4cSMarek Vasut cpg_mode = readl(rst_base + CPG_RST_MODEMR); 106136c2ee4cSMarek Vasut 106236c2ee4cSMarek Vasut priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 106336c2ee4cSMarek Vasut if (!priv->cpg_pll_config->extal_div) 106436c2ee4cSMarek Vasut return -EINVAL; 106536c2ee4cSMarek Vasut 106636c2ee4cSMarek Vasut ret = clk_get_by_name(dev, "extal", &priv->clk_extal); 106736c2ee4cSMarek Vasut if (ret < 0) 106836c2ee4cSMarek Vasut return ret; 106936c2ee4cSMarek Vasut 107036c2ee4cSMarek Vasut ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr); 107136c2ee4cSMarek Vasut if (ret < 0) 107236c2ee4cSMarek Vasut return ret; 107336c2ee4cSMarek Vasut 107436c2ee4cSMarek Vasut return 0; 107536c2ee4cSMarek Vasut } 107636c2ee4cSMarek Vasut 107736c2ee4cSMarek Vasut static const struct udevice_id gen3_clk_ids[] = { 107836c2ee4cSMarek Vasut { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, 107936c2ee4cSMarek Vasut { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, 108036c2ee4cSMarek Vasut { } 108136c2ee4cSMarek Vasut }; 108236c2ee4cSMarek Vasut 108336c2ee4cSMarek Vasut U_BOOT_DRIVER(clk_gen3) = { 108436c2ee4cSMarek Vasut .name = "clk_gen3", 108536c2ee4cSMarek Vasut .id = UCLASS_CLK, 108636c2ee4cSMarek Vasut .of_match = gen3_clk_ids, 108736c2ee4cSMarek Vasut .priv_auto_alloc_size = sizeof(struct gen3_clk_priv), 108836c2ee4cSMarek Vasut .ops = &gen3_clk_ops, 108936c2ee4cSMarek Vasut .probe = gen3_clk_probe, 109036c2ee4cSMarek Vasut }; 1091