1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #define CLK_XTAL 0 11 #define MHZ (1000 * 1000) 12 13 #define HAVE_RST_BAR BIT(0) 14 #define CLK_DOMAIN_SCPSYS BIT(0) 15 16 #define CLK_GATE_SETCLR BIT(0) 17 #define CLK_GATE_SETCLR_INV BIT(1) 18 #define CLK_GATE_NO_SETCLR BIT(2) 19 #define CLK_GATE_NO_SETCLR_INV BIT(3) 20 #define CLK_GATE_MASK GENMASK(3, 0) 21 22 #define CLK_PARENT_APMIXED BIT(4) 23 #define CLK_PARENT_TOPCKGEN BIT(5) 24 #define CLK_PARENT_MASK GENMASK(5, 4) 25 26 /* struct mtk_pll_data - hardware-specific PLLs data */ 27 struct mtk_pll_data { 28 const int id; 29 u32 reg; 30 u32 pwr_reg; 31 u32 en_mask; 32 u32 pd_reg; 33 int pd_shift; 34 u32 flags; 35 u32 rst_bar_mask; 36 u64 fmax; 37 int pcwbits; 38 u32 pcw_reg; 39 int pcw_shift; 40 }; 41 42 /** 43 * struct mtk_fixed_clk - fixed clocks 44 * 45 * @id: index of clocks 46 * @parent: index of parnet clocks 47 * @rate: fixed rate 48 */ 49 struct mtk_fixed_clk { 50 const int id; 51 const int parent; 52 unsigned long rate; 53 }; 54 55 #define FIXED_CLK(_id, _parent, _rate) { \ 56 .id = _id, \ 57 .parent = _parent, \ 58 .rate = _rate, \ 59 } 60 61 /** 62 * struct mtk_fixed_factor - fixed multiplier and divider clocks 63 * 64 * @id: index of clocks 65 * @parent: index of parnet clocks 66 * @mult: multiplier 67 * @div: divider 68 * @flag: hardware-specific flags 69 */ 70 struct mtk_fixed_factor { 71 const int id; 72 const int parent; 73 u32 mult; 74 u32 div; 75 u32 flags; 76 }; 77 78 #define FACTOR(_id, _parent, _mult, _div, _flags) { \ 79 .id = _id, \ 80 .parent = _parent, \ 81 .mult = _mult, \ 82 .div = _div, \ 83 .flags = _flags, \ 84 } 85 86 /** 87 * struct mtk_composite - aggregate clock of mux, divider and gate clocks 88 * 89 * @id: index of clocks 90 * @parent: index of parnet clocks 91 * @mux_reg: hardware-specific mux register 92 * @gate_reg: hardware-specific gate register 93 * @mux_mask: mask to the mux bit field 94 * @mux_shift: shift to the mux bit field 95 * @gate_shift: shift to the gate bit field 96 * @num_parents: number of parent clocks 97 * @flags: hardware-specific flags 98 */ 99 struct mtk_composite { 100 const int id; 101 const int *parent; 102 u32 mux_reg; 103 u32 gate_reg; 104 u32 mux_mask; 105 signed char mux_shift; 106 signed char gate_shift; 107 signed char num_parents; 108 u16 flags; 109 }; 110 111 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ 112 _flags) { \ 113 .id = _id, \ 114 .mux_reg = _reg, \ 115 .mux_shift = _shift, \ 116 .mux_mask = BIT(_width) - 1, \ 117 .gate_reg = _reg, \ 118 .gate_shift = _gate, \ 119 .parent = _parents, \ 120 .num_parents = ARRAY_SIZE(_parents), \ 121 .flags = _flags, \ 122 } 123 124 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ 125 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) 126 127 #define MUX(_id, _parents, _reg, _shift, _width) { \ 128 .id = _id, \ 129 .mux_reg = _reg, \ 130 .mux_shift = _shift, \ 131 .mux_mask = BIT(_width) - 1, \ 132 .gate_shift = -1, \ 133 .parent = _parents, \ 134 .num_parents = ARRAY_SIZE(_parents), \ 135 .flags = 0, \ 136 } 137 138 struct mtk_gate_regs { 139 u32 sta_ofs; 140 u32 clr_ofs; 141 u32 set_ofs; 142 }; 143 144 /** 145 * struct mtk_gate - gate clocks 146 * 147 * @id: index of gate clocks 148 * @parent: index of parnet clocks 149 * @regs: hardware-specific mux register 150 * @shift: shift to the gate bit field 151 * @flags: hardware-specific flags 152 */ 153 struct mtk_gate { 154 const int id; 155 const int parent; 156 const struct mtk_gate_regs *regs; 157 int shift; 158 u32 flags; 159 }; 160 161 /* struct mtk_clk_tree - clock tree */ 162 struct mtk_clk_tree { 163 unsigned long xtal_rate; 164 unsigned long xtal2_rate; 165 const int fdivs_offs; 166 const int muxes_offs; 167 const struct mtk_pll_data *plls; 168 const struct mtk_fixed_clk *fclks; 169 const struct mtk_fixed_factor *fdivs; 170 const struct mtk_composite *muxes; 171 }; 172 173 struct mtk_clk_priv { 174 void __iomem *base; 175 const struct mtk_clk_tree *tree; 176 }; 177 178 struct mtk_cg_priv { 179 void __iomem *base; 180 const struct mtk_clk_tree *tree; 181 const struct mtk_gate *gates; 182 }; 183 184 extern const struct clk_ops mtk_clk_apmixedsys_ops; 185 extern const struct clk_ops mtk_clk_topckgen_ops; 186 extern const struct clk_ops mtk_clk_gate_ops; 187 188 int mtk_common_clk_init(struct udevice *dev, 189 const struct mtk_clk_tree *tree); 190 int mtk_common_clk_gate_init(struct udevice *dev, 191 const struct mtk_clk_tree *tree, 192 const struct mtk_gate *gates); 193 194 #endif /* __DRV_CLK_MTK_H */ 195