1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #define CLK_XTAL 0 11 #define MHZ (1000 * 1000) 12 13 #define HAVE_RST_BAR BIT(0) 14 #define CLK_DOMAIN_SCPSYS BIT(0) 15 16 #define CLK_GATE_SETCLR BIT(0) 17 #define CLK_GATE_SETCLR_INV BIT(1) 18 #define CLK_GATE_NO_SETCLR BIT(2) 19 #define CLK_GATE_NO_SETCLR_INV BIT(3) 20 #define CLK_GATE_MASK GENMASK(3, 0) 21 22 #define CLK_PARENT_APMIXED BIT(4) 23 #define CLK_PARENT_TOPCKGEN BIT(5) 24 #define CLK_PARENT_MASK GENMASK(5, 4) 25 26 #define ETHSYS_RST_CTRL_OFS 0x34 27 28 /* struct mtk_pll_data - hardware-specific PLLs data */ 29 struct mtk_pll_data { 30 const int id; 31 u32 reg; 32 u32 pwr_reg; 33 u32 en_mask; 34 u32 pd_reg; 35 int pd_shift; 36 u32 flags; 37 u32 rst_bar_mask; 38 u64 fmax; 39 int pcwbits; 40 u32 pcw_reg; 41 int pcw_shift; 42 }; 43 44 /** 45 * struct mtk_fixed_clk - fixed clocks 46 * 47 * @id: index of clocks 48 * @parent: index of parnet clocks 49 * @rate: fixed rate 50 */ 51 struct mtk_fixed_clk { 52 const int id; 53 const int parent; 54 unsigned long rate; 55 }; 56 57 #define FIXED_CLK(_id, _parent, _rate) { \ 58 .id = _id, \ 59 .parent = _parent, \ 60 .rate = _rate, \ 61 } 62 63 /** 64 * struct mtk_fixed_factor - fixed multiplier and divider clocks 65 * 66 * @id: index of clocks 67 * @parent: index of parnet clocks 68 * @mult: multiplier 69 * @div: divider 70 * @flag: hardware-specific flags 71 */ 72 struct mtk_fixed_factor { 73 const int id; 74 const int parent; 75 u32 mult; 76 u32 div; 77 u32 flags; 78 }; 79 80 #define FACTOR(_id, _parent, _mult, _div, _flags) { \ 81 .id = _id, \ 82 .parent = _parent, \ 83 .mult = _mult, \ 84 .div = _div, \ 85 .flags = _flags, \ 86 } 87 88 /** 89 * struct mtk_composite - aggregate clock of mux, divider and gate clocks 90 * 91 * @id: index of clocks 92 * @parent: index of parnet clocks 93 * @mux_reg: hardware-specific mux register 94 * @gate_reg: hardware-specific gate register 95 * @mux_mask: mask to the mux bit field 96 * @mux_shift: shift to the mux bit field 97 * @gate_shift: shift to the gate bit field 98 * @num_parents: number of parent clocks 99 * @flags: hardware-specific flags 100 */ 101 struct mtk_composite { 102 const int id; 103 const int *parent; 104 u32 mux_reg; 105 u32 gate_reg; 106 u32 mux_mask; 107 signed char mux_shift; 108 signed char gate_shift; 109 signed char num_parents; 110 u16 flags; 111 }; 112 113 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ 114 _flags) { \ 115 .id = _id, \ 116 .mux_reg = _reg, \ 117 .mux_shift = _shift, \ 118 .mux_mask = BIT(_width) - 1, \ 119 .gate_reg = _reg, \ 120 .gate_shift = _gate, \ 121 .parent = _parents, \ 122 .num_parents = ARRAY_SIZE(_parents), \ 123 .flags = _flags, \ 124 } 125 126 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ 127 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) 128 129 #define MUX(_id, _parents, _reg, _shift, _width) { \ 130 .id = _id, \ 131 .mux_reg = _reg, \ 132 .mux_shift = _shift, \ 133 .mux_mask = BIT(_width) - 1, \ 134 .gate_shift = -1, \ 135 .parent = _parents, \ 136 .num_parents = ARRAY_SIZE(_parents), \ 137 .flags = 0, \ 138 } 139 140 struct mtk_gate_regs { 141 u32 sta_ofs; 142 u32 clr_ofs; 143 u32 set_ofs; 144 }; 145 146 /** 147 * struct mtk_gate - gate clocks 148 * 149 * @id: index of gate clocks 150 * @parent: index of parnet clocks 151 * @regs: hardware-specific mux register 152 * @shift: shift to the gate bit field 153 * @flags: hardware-specific flags 154 */ 155 struct mtk_gate { 156 const int id; 157 const int parent; 158 const struct mtk_gate_regs *regs; 159 int shift; 160 u32 flags; 161 }; 162 163 /* struct mtk_clk_tree - clock tree */ 164 struct mtk_clk_tree { 165 unsigned long xtal_rate; 166 unsigned long xtal2_rate; 167 const int fdivs_offs; 168 const int muxes_offs; 169 const struct mtk_pll_data *plls; 170 const struct mtk_fixed_clk *fclks; 171 const struct mtk_fixed_factor *fdivs; 172 const struct mtk_composite *muxes; 173 }; 174 175 struct mtk_clk_priv { 176 void __iomem *base; 177 const struct mtk_clk_tree *tree; 178 }; 179 180 struct mtk_cg_priv { 181 void __iomem *base; 182 const struct mtk_clk_tree *tree; 183 const struct mtk_gate *gates; 184 }; 185 186 extern const struct clk_ops mtk_clk_apmixedsys_ops; 187 extern const struct clk_ops mtk_clk_topckgen_ops; 188 extern const struct clk_ops mtk_clk_gate_ops; 189 190 int mtk_common_clk_init(struct udevice *dev, 191 const struct mtk_clk_tree *tree); 192 int mtk_common_clk_gate_init(struct udevice *dev, 193 const struct mtk_clk_tree *tree, 194 const struct mtk_gate *gates); 195 196 #endif /* __DRV_CLK_MTK_H */ 197