1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek clock driver for MT7629 SoC 4 * 5 * Copyright (C) 2018 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/io.h> 12 #include <dt-bindings/clock/mt7629-clk.h> 13 14 #include "clk-mtk.h" 15 16 #define MT7629_CLKSQ_STB_CON0 0x20 17 #define MT7629_PLL_ISO_CON0 0x2c 18 #define MT7629_PLL_FMAX (2500UL * MHZ) 19 #define MT7629_CON0_RST_BAR BIT(24) 20 21 #define MCU_AXI_DIV 0x640 22 #define AXI_DIV_MSK GENMASK(4, 0) 23 #define AXI_DIV_SEL(x) (x) 24 25 #define MCU_BUS_MUX 0x7c0 26 #define MCU_BUS_MSK GENMASK(10, 9) 27 #define MCU_BUS_SEL(x) ((x) << 9) 28 29 /* apmixedsys */ 30 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 31 _pd_shift, _pcw_reg, _pcw_shift) { \ 32 .id = _id, \ 33 .reg = _reg, \ 34 .pwr_reg = _pwr_reg, \ 35 .en_mask = _en_mask, \ 36 .rst_bar_mask = MT7629_CON0_RST_BAR, \ 37 .fmax = MT7629_PLL_FMAX, \ 38 .flags = _flags, \ 39 .pcwbits = _pcwbits, \ 40 .pd_reg = _pd_reg, \ 41 .pd_shift = _pd_shift, \ 42 .pcw_reg = _pcw_reg, \ 43 .pcw_shift = _pcw_shift, \ 44 } 45 46 static const struct mtk_pll_data apmixed_plls[] = { 47 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 48 21, 0x204, 24, 0x204, 0), 49 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, 50 21, 0x214, 24, 0x214, 0), 51 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, 52 7, 0x224, 24, 0x224, 14), 53 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 54 21, 0x300, 1, 0x304, 0), 55 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, 56 21, 0x314, 1, 0x318, 0), 57 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, 58 21, 0x358, 1, 0x35c, 0), 59 }; 60 61 /* topckgen */ 62 #define FACTOR0(_id, _parent, _mult, _div) \ 63 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 64 65 #define FACTOR1(_id, _parent, _mult, _div) \ 66 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 67 68 #define FACTOR2(_id, _parent, _mult, _div) \ 69 FACTOR(_id, _parent, _mult, _div, 0) 70 71 static const struct mtk_fixed_clk top_fixed_clks[] = { 72 FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), 73 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), 74 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), 75 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), 76 FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), 77 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), 78 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), 79 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), 80 FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), 81 FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), 82 }; 83 84 static const struct mtk_fixed_factor top_fixed_divs[] = { 85 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4), 86 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), 87 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), 88 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), 89 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), 90 FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), 91 FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), 92 FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), 93 FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), 94 FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), 95 FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), 96 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), 97 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), 98 FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), 99 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), 100 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), 101 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), 102 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), 103 FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32), 104 FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6), 105 FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), 106 FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), 107 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), 108 FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10), 109 FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), 110 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), 111 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), 112 FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28), 113 FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112), 114 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2), 115 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), 116 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), 117 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), 118 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3), 119 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), 120 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), 121 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), 122 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48), 123 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), 124 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), 125 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), 126 FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80), 127 FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7), 128 FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), 129 FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), 130 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), 131 FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), 132 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), 133 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), 134 FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), 135 FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1), 136 FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1), 137 FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1), 138 FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1), 139 FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1), 140 FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1), 141 FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4), 142 FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1), 143 FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1), 144 FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1), 145 FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1), 146 FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), 147 FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), 148 }; 149 150 static const int axi_parents[] = { 151 CLK_XTAL, 152 CLK_TOP_SYSPLL1_D2, 153 CLK_TOP_SYSPLL_D5, 154 CLK_TOP_SYSPLL1_D4, 155 CLK_TOP_UNIVPLL_D5, 156 CLK_TOP_UNIVPLL2_D2, 157 CLK_TOP_UNIVPLL_D7, 158 CLK_TOP_DMPLL 159 }; 160 161 static const int mem_parents[] = { 162 CLK_XTAL, 163 CLK_TOP_DMPLL 164 }; 165 166 static const int ddrphycfg_parents[] = { 167 CLK_XTAL, 168 CLK_TOP_SYSPLL1_D8 169 }; 170 171 static const int eth_parents[] = { 172 CLK_XTAL, 173 CLK_TOP_SYSPLL1_D2, 174 CLK_TOP_UNIVPLL1_D2, 175 CLK_TOP_SYSPLL1_D4, 176 CLK_TOP_UNIVPLL_D5, 177 CLK_TOP_SGMIIPLL_D2, 178 CLK_TOP_UNIVPLL_D7, 179 CLK_TOP_DMPLL 180 }; 181 182 static const int pwm_parents[] = { 183 CLK_XTAL, 184 CLK_TOP_UNIVPLL2_D4 185 }; 186 187 static const int f10m_ref_parents[] = { 188 CLK_XTAL, 189 CLK_TOP_SGMIIPLL_D2 190 }; 191 192 static const int nfi_infra_parents[] = { 193 CLK_XTAL, 194 CLK_XTAL, 195 CLK_XTAL, 196 CLK_XTAL, 197 CLK_XTAL, 198 CLK_XTAL, 199 CLK_TOP_UNIVPLL2_D8, 200 CLK_TOP_UNIVPLL3_D4, 201 CLK_TOP_SYSPLL1_D8, 202 CLK_TOP_UNIVPLL1_D8, 203 CLK_TOP_SYSPLL4_D2, 204 CLK_TOP_SYSPLL2_D4, 205 CLK_TOP_UNIVPLL2_D4, 206 CLK_TOP_UNIVPLL3_D2, 207 CLK_TOP_SYSPLL1_D4, 208 CLK_TOP_SYSPLL_D7 209 }; 210 211 static const int flash_parents[] = { 212 CLK_XTAL, 213 CLK_TOP_UNIVPLL_D80_D4, 214 CLK_TOP_SYSPLL2_D8, 215 CLK_TOP_SYSPLL3_D4, 216 CLK_TOP_UNIVPLL3_D4, 217 CLK_TOP_UNIVPLL1_D8, 218 CLK_TOP_SYSPLL2_D4, 219 CLK_TOP_UNIVPLL2_D4 220 }; 221 222 static const int uart_parents[] = { 223 CLK_XTAL, 224 CLK_TOP_UNIVPLL2_D8 225 }; 226 227 static const int spi0_parents[] = { 228 CLK_XTAL, 229 CLK_TOP_SYSPLL3_D2, 230 CLK_XTAL, 231 CLK_TOP_SYSPLL2_D4, 232 CLK_TOP_SYSPLL4_D2, 233 CLK_TOP_UNIVPLL2_D4, 234 CLK_TOP_UNIVPLL1_D8, 235 CLK_XTAL 236 }; 237 238 static const int spi1_parents[] = { 239 CLK_XTAL, 240 CLK_TOP_SYSPLL3_D2, 241 CLK_XTAL, 242 CLK_TOP_SYSPLL4_D4, 243 CLK_TOP_SYSPLL4_D2, 244 CLK_TOP_UNIVPLL2_D4, 245 CLK_TOP_UNIVPLL1_D8, 246 CLK_XTAL 247 }; 248 249 static const int msdc30_0_parents[] = { 250 CLK_XTAL, 251 CLK_TOP_UNIVPLL2_D16, 252 CLK_TOP_UNIV48M 253 }; 254 255 static const int msdc30_1_parents[] = { 256 CLK_XTAL, 257 CLK_TOP_UNIVPLL2_D16, 258 CLK_TOP_UNIV48M, 259 CLK_TOP_SYSPLL2_D4, 260 CLK_TOP_UNIVPLL2_D4, 261 CLK_TOP_SYSPLL_D7, 262 CLK_TOP_SYSPLL2_D2, 263 CLK_TOP_UNIVPLL2_D2 264 }; 265 266 static const int ap2wbmcu_parents[] = { 267 CLK_XTAL, 268 CLK_TOP_SYSPLL1_D2, 269 CLK_TOP_UNIV48M, 270 CLK_TOP_SYSPLL1_D8, 271 CLK_TOP_UNIVPLL2_D4, 272 CLK_TOP_SYSPLL_D7, 273 CLK_TOP_SYSPLL2_D2, 274 CLK_TOP_UNIVPLL2_D2 275 }; 276 277 static const int audio_parents[] = { 278 CLK_XTAL, 279 CLK_TOP_SYSPLL3_D4, 280 CLK_TOP_SYSPLL4_D4, 281 CLK_TOP_SYSPLL1_D16 282 }; 283 284 static const int aud_intbus_parents[] = { 285 CLK_XTAL, 286 CLK_TOP_SYSPLL1_D4, 287 CLK_TOP_SYSPLL4_D2, 288 CLK_TOP_DMPLL_D4 289 }; 290 291 static const int pmicspi_parents[] = { 292 CLK_XTAL, 293 CLK_TOP_SYSPLL1_D8, 294 CLK_TOP_SYSPLL3_D4, 295 CLK_TOP_SYSPLL1_D16, 296 CLK_TOP_UNIVPLL3_D4, 297 CLK_XTAL, 298 CLK_TOP_UNIVPLL2_D4, 299 CLK_TOP_DMPLL_D8 300 }; 301 302 static const int scp_parents[] = { 303 CLK_XTAL, 304 CLK_TOP_SYSPLL1_D8, 305 CLK_TOP_UNIVPLL2_D2, 306 CLK_TOP_UNIVPLL2_D4 307 }; 308 309 static const int atb_parents[] = { 310 CLK_XTAL, 311 CLK_TOP_SYSPLL1_D2, 312 CLK_TOP_SYSPLL_D5 313 }; 314 315 static const int hif_parents[] = { 316 CLK_XTAL, 317 CLK_TOP_SYSPLL1_D2, 318 CLK_TOP_UNIVPLL1_D2, 319 CLK_TOP_SYSPLL1_D4, 320 CLK_TOP_UNIVPLL_D5, 321 -1, 322 CLK_TOP_UNIVPLL_D7 323 }; 324 325 static const int sata_parents[] = { 326 CLK_XTAL, 327 CLK_TOP_UNIVPLL2_D4 328 }; 329 330 static const int usb20_parents[] = { 331 CLK_XTAL, 332 CLK_TOP_UNIVPLL3_D4, 333 CLK_TOP_SYSPLL1_D8 334 }; 335 336 static const int aud1_parents[] = { 337 CLK_XTAL 338 }; 339 340 static const int irrx_parents[] = { 341 CLK_XTAL, 342 CLK_TOP_SYSPLL4_D16 343 }; 344 345 static const int crypto_parents[] = { 346 CLK_XTAL, 347 CLK_TOP_UNIVPLL_D3, 348 CLK_TOP_UNIVPLL1_D2, 349 CLK_TOP_SYSPLL1_D2, 350 CLK_TOP_UNIVPLL_D5, 351 CLK_TOP_SYSPLL_D5, 352 CLK_TOP_UNIVPLL2_D2, 353 CLK_TOP_SYSPLL_D2 354 }; 355 356 static const int gpt10m_parents[] = { 357 CLK_XTAL, 358 CLK_TOP_CLKXTAL_D4 359 }; 360 361 static const struct mtk_composite top_muxes[] = { 362 /* CLK_CFG_0 */ 363 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), 364 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), 365 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), 366 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), 367 368 /* CLK_CFG_1 */ 369 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), 370 MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), 371 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), 372 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), 373 374 /* CLK_CFG_2 */ 375 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), 376 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), 377 MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), 378 MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), 379 380 /* CLK_CFG_3 */ 381 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), 382 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), 383 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), 384 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), 385 386 /* CLK_CFG_4 */ 387 MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), 388 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), 389 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), 390 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), 391 392 /* CLK_CFG_5 */ 393 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), 394 MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, 395 CLK_DOMAIN_SCPSYS), 396 MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), 397 MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), 398 399 /* CLK_CFG_6 */ 400 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), 401 MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), 402 MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), 403 MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), 404 405 /* CLK_CFG_7 */ 406 MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), 407 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), 408 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), 409 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), 410 411 /* CLK_CFG_8 */ 412 MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), 413 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), 414 MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), 415 }; 416 417 /* infracfg */ 418 static const struct mtk_gate_regs infra_cg_regs = { 419 .set_ofs = 0x40, 420 .clr_ofs = 0x44, 421 .sta_ofs = 0x48, 422 }; 423 424 #define GATE_INFRA(_id, _parent, _shift) { \ 425 .id = _id, \ 426 .parent = _parent, \ 427 .regs = &infra_cg_regs, \ 428 .shift = _shift, \ 429 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 430 } 431 432 static const struct mtk_gate infra_cgs[] = { 433 GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0), 434 GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2), 435 GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4), 436 GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18), 437 GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19), 438 }; 439 440 /* pericfg */ 441 static const struct mtk_gate_regs peri0_cg_regs = { 442 .set_ofs = 0x8, 443 .clr_ofs = 0x10, 444 .sta_ofs = 0x18, 445 }; 446 447 static const struct mtk_gate_regs peri1_cg_regs = { 448 .set_ofs = 0xC, 449 .clr_ofs = 0x14, 450 .sta_ofs = 0x1C, 451 }; 452 453 #define GATE_PERI0(_id, _parent, _shift) { \ 454 .id = _id, \ 455 .parent = _parent, \ 456 .regs = &peri0_cg_regs, \ 457 .shift = _shift, \ 458 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 459 } 460 461 #define GATE_PERI1(_id, _parent, _shift) { \ 462 .id = _id, \ 463 .parent = _parent, \ 464 .regs = &peri1_cg_regs, \ 465 .shift = _shift, \ 466 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 467 } 468 469 static const struct mtk_gate peri_cgs[] = { 470 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2), 471 GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3), 472 GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4), 473 GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5), 474 GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6), 475 GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7), 476 GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8), 477 GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9), 478 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12), 479 GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14), 480 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17), 481 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18), 482 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19), 483 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20), 484 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22), 485 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23), 486 GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28), 487 GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29), 488 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30), 489 GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31), 490 GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1), 491 }; 492 493 /* ethsys */ 494 static const struct mtk_gate_regs eth_cg_regs = { 495 .sta_ofs = 0x30, 496 }; 497 498 #define GATE_ETH(_id, _parent, _shift, _flag) { \ 499 .id = _id, \ 500 .parent = _parent, \ 501 .regs = ð_cg_regs, \ 502 .shift = _shift, \ 503 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \ 504 } 505 506 #define GATE_ETH0(_id, _parent, _shift) \ 507 GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED) 508 509 #define GATE_ETH1(_id, _parent, _shift) \ 510 GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN) 511 512 static const struct mtk_gate eth_cgs[] = { 513 GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6), 514 GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 515 GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 516 GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9), 517 GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16), 518 }; 519 520 static const struct mtk_gate_regs sgmii_cg_regs = { 521 .set_ofs = 0xE4, 522 .clr_ofs = 0xE4, 523 .sta_ofs = 0xE4, 524 }; 525 526 #define GATE_SGMII(_id, _parent, _shift) { \ 527 .id = _id, \ 528 .parent = _parent, \ 529 .regs = &sgmii_cg_regs, \ 530 .shift = _shift, \ 531 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ 532 } 533 534 static const struct mtk_gate sgmii_cgs[] = { 535 GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2), 536 GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), 537 GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4), 538 GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), 539 }; 540 541 static const struct mtk_clk_tree mt7629_clk_tree = { 542 .xtal_rate = 40 * MHZ, 543 .xtal2_rate = 20 * MHZ, 544 .fdivs_offs = CLK_TOP_TO_USB3_SYS, 545 .muxes_offs = CLK_TOP_AXI_SEL, 546 .plls = apmixed_plls, 547 .fclks = top_fixed_clks, 548 .fdivs = top_fixed_divs, 549 .muxes = top_muxes, 550 }; 551 552 static int mt7629_mcucfg_probe(struct udevice *dev) 553 { 554 void __iomem *base; 555 556 base = dev_read_addr_ptr(dev); 557 if (!base) 558 return -ENOENT; 559 560 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, 561 AXI_DIV_SEL(0x12)); 562 clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK, 563 MCU_BUS_SEL(0x1)); 564 565 return 0; 566 } 567 568 static int mt7629_apmixedsys_probe(struct udevice *dev) 569 { 570 struct mtk_clk_priv *priv = dev_get_priv(dev); 571 int ret; 572 573 ret = mtk_common_clk_init(dev, &mt7629_clk_tree); 574 if (ret) 575 return ret; 576 577 /* reduce clock square disable time */ 578 writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0); 579 /* extend pwr/iso control timing to 1us */ 580 writel(0x80008, priv->base + MT7629_PLL_ISO_CON0); 581 582 return 0; 583 } 584 585 static int mt7629_topckgen_probe(struct udevice *dev) 586 { 587 return mtk_common_clk_init(dev, &mt7629_clk_tree); 588 } 589 590 static int mt7629_infracfg_probe(struct udevice *dev) 591 { 592 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs); 593 } 594 595 static int mt7629_pericfg_probe(struct udevice *dev) 596 { 597 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs); 598 } 599 600 static int mt7629_ethsys_probe(struct udevice *dev) 601 { 602 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs); 603 } 604 605 static int mt7629_sgmiisys_probe(struct udevice *dev) 606 { 607 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs); 608 } 609 610 static const struct udevice_id mt7629_apmixed_compat[] = { 611 { .compatible = "mediatek,mt7629-apmixedsys" }, 612 { } 613 }; 614 615 static const struct udevice_id mt7629_topckgen_compat[] = { 616 { .compatible = "mediatek,mt7629-topckgen" }, 617 { } 618 }; 619 620 static const struct udevice_id mt7629_infracfg_compat[] = { 621 { .compatible = "mediatek,mt7629-infracfg", }, 622 { } 623 }; 624 625 static const struct udevice_id mt7629_pericfg_compat[] = { 626 { .compatible = "mediatek,mt7629-pericfg", }, 627 { } 628 }; 629 630 static const struct udevice_id mt7629_ethsys_compat[] = { 631 { .compatible = "mediatek,mt7629-ethsys", }, 632 { } 633 }; 634 635 static const struct udevice_id mt7629_sgmiisys_compat[] = { 636 { .compatible = "mediatek,mt7629-sgmiisys", }, 637 { } 638 }; 639 640 static const struct udevice_id mt7629_mcucfg_compat[] = { 641 { .compatible = "mediatek,mt7629-mcucfg" }, 642 { } 643 }; 644 645 U_BOOT_DRIVER(mtk_mcucfg) = { 646 .name = "mt7629-mcucfg", 647 .id = UCLASS_SYSCON, 648 .of_match = mt7629_mcucfg_compat, 649 .probe = mt7629_mcucfg_probe, 650 .flags = DM_FLAG_PRE_RELOC, 651 }; 652 653 U_BOOT_DRIVER(mtk_clk_apmixedsys) = { 654 .name = "mt7629-clock-apmixedsys", 655 .id = UCLASS_CLK, 656 .of_match = mt7629_apmixed_compat, 657 .probe = mt7629_apmixedsys_probe, 658 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), 659 .ops = &mtk_clk_apmixedsys_ops, 660 .flags = DM_FLAG_PRE_RELOC, 661 }; 662 663 U_BOOT_DRIVER(mtk_clk_topckgen) = { 664 .name = "mt7629-clock-topckgen", 665 .id = UCLASS_CLK, 666 .of_match = mt7629_topckgen_compat, 667 .probe = mt7629_topckgen_probe, 668 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), 669 .ops = &mtk_clk_topckgen_ops, 670 .flags = DM_FLAG_PRE_RELOC, 671 }; 672 673 U_BOOT_DRIVER(mtk_clk_infracfg) = { 674 .name = "mt7629-clock-infracfg", 675 .id = UCLASS_CLK, 676 .of_match = mt7629_infracfg_compat, 677 .probe = mt7629_infracfg_probe, 678 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 679 .ops = &mtk_clk_gate_ops, 680 .flags = DM_FLAG_PRE_RELOC, 681 }; 682 683 U_BOOT_DRIVER(mtk_clk_pericfg) = { 684 .name = "mt7629-clock-pericfg", 685 .id = UCLASS_CLK, 686 .of_match = mt7629_pericfg_compat, 687 .probe = mt7629_pericfg_probe, 688 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 689 .ops = &mtk_clk_gate_ops, 690 .flags = DM_FLAG_PRE_RELOC, 691 }; 692 693 U_BOOT_DRIVER(mtk_clk_ethsys) = { 694 .name = "mt7629-clock-ethsys", 695 .id = UCLASS_CLK, 696 .of_match = mt7629_ethsys_compat, 697 .probe = mt7629_ethsys_probe, 698 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 699 .ops = &mtk_clk_gate_ops, 700 }; 701 702 U_BOOT_DRIVER(mtk_clk_sgmiisys) = { 703 .name = "mt7629-clock-sgmiisys", 704 .id = UCLASS_CLK, 705 .of_match = mt7629_sgmiisys_compat, 706 .probe = mt7629_sgmiisys_probe, 707 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 708 .ops = &mtk_clk_gate_ops, 709 }; 710