1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek clock driver for MT7629 SoC 4 * 5 * Copyright (C) 2018 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/arch-mediatek/reset.h> 12 #include <asm/io.h> 13 #include <dt-bindings/clock/mt7629-clk.h> 14 15 #include "clk-mtk.h" 16 17 #define MT7629_CLKSQ_STB_CON0 0x20 18 #define MT7629_PLL_ISO_CON0 0x2c 19 #define MT7629_PLL_FMAX (2500UL * MHZ) 20 #define MT7629_CON0_RST_BAR BIT(24) 21 22 #define MCU_AXI_DIV 0x640 23 #define AXI_DIV_MSK GENMASK(4, 0) 24 #define AXI_DIV_SEL(x) (x) 25 26 #define MCU_BUS_MUX 0x7c0 27 #define MCU_BUS_MSK GENMASK(10, 9) 28 #define MCU_BUS_SEL(x) ((x) << 9) 29 30 /* apmixedsys */ 31 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 32 _pd_shift, _pcw_reg, _pcw_shift) { \ 33 .id = _id, \ 34 .reg = _reg, \ 35 .pwr_reg = _pwr_reg, \ 36 .en_mask = _en_mask, \ 37 .rst_bar_mask = MT7629_CON0_RST_BAR, \ 38 .fmax = MT7629_PLL_FMAX, \ 39 .flags = _flags, \ 40 .pcwbits = _pcwbits, \ 41 .pd_reg = _pd_reg, \ 42 .pd_shift = _pd_shift, \ 43 .pcw_reg = _pcw_reg, \ 44 .pcw_shift = _pcw_shift, \ 45 } 46 47 static const struct mtk_pll_data apmixed_plls[] = { 48 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 49 21, 0x204, 24, 0x204, 0), 50 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, 51 21, 0x214, 24, 0x214, 0), 52 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, 53 7, 0x224, 24, 0x224, 14), 54 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 55 21, 0x300, 1, 0x304, 0), 56 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, 57 21, 0x314, 1, 0x318, 0), 58 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, 59 21, 0x358, 1, 0x35c, 0), 60 }; 61 62 /* topckgen */ 63 #define FACTOR0(_id, _parent, _mult, _div) \ 64 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 65 66 #define FACTOR1(_id, _parent, _mult, _div) \ 67 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 68 69 #define FACTOR2(_id, _parent, _mult, _div) \ 70 FACTOR(_id, _parent, _mult, _div, 0) 71 72 static const struct mtk_fixed_clk top_fixed_clks[] = { 73 FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), 74 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), 75 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), 76 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), 77 FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), 78 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), 79 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), 80 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), 81 FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), 82 FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), 83 }; 84 85 static const struct mtk_fixed_factor top_fixed_divs[] = { 86 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4), 87 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), 88 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), 89 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), 90 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), 91 FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), 92 FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), 93 FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1), 94 FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1), 95 FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1), 96 FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), 97 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), 98 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4), 99 FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8), 100 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), 101 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), 102 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), 103 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), 104 FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32), 105 FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6), 106 FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), 107 FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), 108 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), 109 FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10), 110 FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), 111 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), 112 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), 113 FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28), 114 FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112), 115 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2), 116 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), 117 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), 118 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), 119 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3), 120 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), 121 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), 122 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), 123 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48), 124 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), 125 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), 126 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), 127 FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80), 128 FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7), 129 FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), 130 FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), 131 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), 132 FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4), 133 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), 134 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), 135 FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1), 136 FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1), 137 FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1), 138 FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1), 139 FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1), 140 FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1), 141 FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1), 142 FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4), 143 FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1), 144 FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1), 145 FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1), 146 FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1), 147 FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), 148 FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), 149 }; 150 151 static const int axi_parents[] = { 152 CLK_XTAL, 153 CLK_TOP_SYSPLL1_D2, 154 CLK_TOP_SYSPLL_D5, 155 CLK_TOP_SYSPLL1_D4, 156 CLK_TOP_UNIVPLL_D5, 157 CLK_TOP_UNIVPLL2_D2, 158 CLK_TOP_UNIVPLL_D7, 159 CLK_TOP_DMPLL 160 }; 161 162 static const int mem_parents[] = { 163 CLK_XTAL, 164 CLK_TOP_DMPLL 165 }; 166 167 static const int ddrphycfg_parents[] = { 168 CLK_XTAL, 169 CLK_TOP_SYSPLL1_D8 170 }; 171 172 static const int eth_parents[] = { 173 CLK_XTAL, 174 CLK_TOP_SYSPLL1_D2, 175 CLK_TOP_UNIVPLL1_D2, 176 CLK_TOP_SYSPLL1_D4, 177 CLK_TOP_UNIVPLL_D5, 178 CLK_TOP_SGMIIPLL_D2, 179 CLK_TOP_UNIVPLL_D7, 180 CLK_TOP_DMPLL 181 }; 182 183 static const int pwm_parents[] = { 184 CLK_XTAL, 185 CLK_TOP_UNIVPLL2_D4 186 }; 187 188 static const int f10m_ref_parents[] = { 189 CLK_XTAL, 190 CLK_TOP_SGMIIPLL_D2 191 }; 192 193 static const int nfi_infra_parents[] = { 194 CLK_XTAL, 195 CLK_XTAL, 196 CLK_XTAL, 197 CLK_XTAL, 198 CLK_XTAL, 199 CLK_XTAL, 200 CLK_TOP_UNIVPLL2_D8, 201 CLK_TOP_UNIVPLL3_D4, 202 CLK_TOP_SYSPLL1_D8, 203 CLK_TOP_UNIVPLL1_D8, 204 CLK_TOP_SYSPLL4_D2, 205 CLK_TOP_SYSPLL2_D4, 206 CLK_TOP_UNIVPLL2_D4, 207 CLK_TOP_UNIVPLL3_D2, 208 CLK_TOP_SYSPLL1_D4, 209 CLK_TOP_SYSPLL_D7 210 }; 211 212 static const int flash_parents[] = { 213 CLK_XTAL, 214 CLK_TOP_UNIVPLL_D80_D4, 215 CLK_TOP_SYSPLL2_D8, 216 CLK_TOP_SYSPLL3_D4, 217 CLK_TOP_UNIVPLL3_D4, 218 CLK_TOP_UNIVPLL1_D8, 219 CLK_TOP_SYSPLL2_D4, 220 CLK_TOP_UNIVPLL2_D4 221 }; 222 223 static const int uart_parents[] = { 224 CLK_XTAL, 225 CLK_TOP_UNIVPLL2_D8 226 }; 227 228 static const int spi0_parents[] = { 229 CLK_XTAL, 230 CLK_TOP_SYSPLL3_D2, 231 CLK_XTAL, 232 CLK_TOP_SYSPLL2_D4, 233 CLK_TOP_SYSPLL4_D2, 234 CLK_TOP_UNIVPLL2_D4, 235 CLK_TOP_UNIVPLL1_D8, 236 CLK_XTAL 237 }; 238 239 static const int spi1_parents[] = { 240 CLK_XTAL, 241 CLK_TOP_SYSPLL3_D2, 242 CLK_XTAL, 243 CLK_TOP_SYSPLL4_D4, 244 CLK_TOP_SYSPLL4_D2, 245 CLK_TOP_UNIVPLL2_D4, 246 CLK_TOP_UNIVPLL1_D8, 247 CLK_XTAL 248 }; 249 250 static const int msdc30_0_parents[] = { 251 CLK_XTAL, 252 CLK_TOP_UNIVPLL2_D16, 253 CLK_TOP_UNIV48M 254 }; 255 256 static const int msdc30_1_parents[] = { 257 CLK_XTAL, 258 CLK_TOP_UNIVPLL2_D16, 259 CLK_TOP_UNIV48M, 260 CLK_TOP_SYSPLL2_D4, 261 CLK_TOP_UNIVPLL2_D4, 262 CLK_TOP_SYSPLL_D7, 263 CLK_TOP_SYSPLL2_D2, 264 CLK_TOP_UNIVPLL2_D2 265 }; 266 267 static const int ap2wbmcu_parents[] = { 268 CLK_XTAL, 269 CLK_TOP_SYSPLL1_D2, 270 CLK_TOP_UNIV48M, 271 CLK_TOP_SYSPLL1_D8, 272 CLK_TOP_UNIVPLL2_D4, 273 CLK_TOP_SYSPLL_D7, 274 CLK_TOP_SYSPLL2_D2, 275 CLK_TOP_UNIVPLL2_D2 276 }; 277 278 static const int audio_parents[] = { 279 CLK_XTAL, 280 CLK_TOP_SYSPLL3_D4, 281 CLK_TOP_SYSPLL4_D4, 282 CLK_TOP_SYSPLL1_D16 283 }; 284 285 static const int aud_intbus_parents[] = { 286 CLK_XTAL, 287 CLK_TOP_SYSPLL1_D4, 288 CLK_TOP_SYSPLL4_D2, 289 CLK_TOP_DMPLL_D4 290 }; 291 292 static const int pmicspi_parents[] = { 293 CLK_XTAL, 294 CLK_TOP_SYSPLL1_D8, 295 CLK_TOP_SYSPLL3_D4, 296 CLK_TOP_SYSPLL1_D16, 297 CLK_TOP_UNIVPLL3_D4, 298 CLK_XTAL, 299 CLK_TOP_UNIVPLL2_D4, 300 CLK_TOP_DMPLL_D8 301 }; 302 303 static const int scp_parents[] = { 304 CLK_XTAL, 305 CLK_TOP_SYSPLL1_D8, 306 CLK_TOP_UNIVPLL2_D2, 307 CLK_TOP_UNIVPLL2_D4 308 }; 309 310 static const int atb_parents[] = { 311 CLK_XTAL, 312 CLK_TOP_SYSPLL1_D2, 313 CLK_TOP_SYSPLL_D5 314 }; 315 316 static const int hif_parents[] = { 317 CLK_XTAL, 318 CLK_TOP_SYSPLL1_D2, 319 CLK_TOP_UNIVPLL1_D2, 320 CLK_TOP_SYSPLL1_D4, 321 CLK_TOP_UNIVPLL_D5, 322 -1, 323 CLK_TOP_UNIVPLL_D7 324 }; 325 326 static const int sata_parents[] = { 327 CLK_XTAL, 328 CLK_TOP_UNIVPLL2_D4 329 }; 330 331 static const int usb20_parents[] = { 332 CLK_XTAL, 333 CLK_TOP_UNIVPLL3_D4, 334 CLK_TOP_SYSPLL1_D8 335 }; 336 337 static const int aud1_parents[] = { 338 CLK_XTAL 339 }; 340 341 static const int irrx_parents[] = { 342 CLK_XTAL, 343 CLK_TOP_SYSPLL4_D16 344 }; 345 346 static const int crypto_parents[] = { 347 CLK_XTAL, 348 CLK_TOP_UNIVPLL_D3, 349 CLK_TOP_UNIVPLL1_D2, 350 CLK_TOP_SYSPLL1_D2, 351 CLK_TOP_UNIVPLL_D5, 352 CLK_TOP_SYSPLL_D5, 353 CLK_TOP_UNIVPLL2_D2, 354 CLK_TOP_SYSPLL_D2 355 }; 356 357 static const int gpt10m_parents[] = { 358 CLK_XTAL, 359 CLK_TOP_CLKXTAL_D4 360 }; 361 362 static const struct mtk_composite top_muxes[] = { 363 /* CLK_CFG_0 */ 364 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), 365 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), 366 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), 367 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), 368 369 /* CLK_CFG_1 */ 370 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), 371 MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), 372 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), 373 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), 374 375 /* CLK_CFG_2 */ 376 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), 377 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), 378 MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), 379 MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), 380 381 /* CLK_CFG_3 */ 382 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), 383 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15), 384 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23), 385 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31), 386 387 /* CLK_CFG_4 */ 388 MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7), 389 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), 390 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), 391 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31), 392 393 /* CLK_CFG_5 */ 394 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), 395 MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15, 396 CLK_DOMAIN_SCPSYS), 397 MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23), 398 MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), 399 400 /* CLK_CFG_6 */ 401 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), 402 MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), 403 MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23), 404 MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31), 405 406 /* CLK_CFG_7 */ 407 MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7), 408 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15), 409 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23), 410 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31), 411 412 /* CLK_CFG_8 */ 413 MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), 414 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), 415 MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), 416 }; 417 418 /* infracfg */ 419 static const struct mtk_gate_regs infra_cg_regs = { 420 .set_ofs = 0x40, 421 .clr_ofs = 0x44, 422 .sta_ofs = 0x48, 423 }; 424 425 #define GATE_INFRA(_id, _parent, _shift) { \ 426 .id = _id, \ 427 .parent = _parent, \ 428 .regs = &infra_cg_regs, \ 429 .shift = _shift, \ 430 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 431 } 432 433 static const struct mtk_gate infra_cgs[] = { 434 GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0), 435 GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2), 436 GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4), 437 GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18), 438 GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19), 439 }; 440 441 /* pericfg */ 442 static const struct mtk_gate_regs peri0_cg_regs = { 443 .set_ofs = 0x8, 444 .clr_ofs = 0x10, 445 .sta_ofs = 0x18, 446 }; 447 448 static const struct mtk_gate_regs peri1_cg_regs = { 449 .set_ofs = 0xC, 450 .clr_ofs = 0x14, 451 .sta_ofs = 0x1C, 452 }; 453 454 #define GATE_PERI0(_id, _parent, _shift) { \ 455 .id = _id, \ 456 .parent = _parent, \ 457 .regs = &peri0_cg_regs, \ 458 .shift = _shift, \ 459 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 460 } 461 462 #define GATE_PERI1(_id, _parent, _shift) { \ 463 .id = _id, \ 464 .parent = _parent, \ 465 .regs = &peri1_cg_regs, \ 466 .shift = _shift, \ 467 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 468 } 469 470 static const struct mtk_gate peri_cgs[] = { 471 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2), 472 GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3), 473 GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4), 474 GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5), 475 GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6), 476 GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7), 477 GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8), 478 GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9), 479 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12), 480 GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14), 481 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17), 482 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18), 483 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19), 484 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20), 485 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22), 486 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23), 487 GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28), 488 GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29), 489 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30), 490 GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31), 491 GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1), 492 }; 493 494 /* ethsys */ 495 static const struct mtk_gate_regs eth_cg_regs = { 496 .sta_ofs = 0x30, 497 }; 498 499 #define GATE_ETH(_id, _parent, _shift, _flag) { \ 500 .id = _id, \ 501 .parent = _parent, \ 502 .regs = ð_cg_regs, \ 503 .shift = _shift, \ 504 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \ 505 } 506 507 #define GATE_ETH0(_id, _parent, _shift) \ 508 GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED) 509 510 #define GATE_ETH1(_id, _parent, _shift) \ 511 GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN) 512 513 static const struct mtk_gate eth_cgs[] = { 514 GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6), 515 GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), 516 GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), 517 GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9), 518 GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16), 519 }; 520 521 static const struct mtk_gate_regs sgmii_cg_regs = { 522 .set_ofs = 0xE4, 523 .clr_ofs = 0xE4, 524 .sta_ofs = 0xE4, 525 }; 526 527 #define GATE_SGMII(_id, _parent, _shift) { \ 528 .id = _id, \ 529 .parent = _parent, \ 530 .regs = &sgmii_cg_regs, \ 531 .shift = _shift, \ 532 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ 533 } 534 535 static const struct mtk_gate sgmii_cgs[] = { 536 GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2), 537 GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), 538 GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4), 539 GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), 540 }; 541 542 static const struct mtk_clk_tree mt7629_clk_tree = { 543 .xtal_rate = 40 * MHZ, 544 .xtal2_rate = 20 * MHZ, 545 .fdivs_offs = CLK_TOP_TO_USB3_SYS, 546 .muxes_offs = CLK_TOP_AXI_SEL, 547 .plls = apmixed_plls, 548 .fclks = top_fixed_clks, 549 .fdivs = top_fixed_divs, 550 .muxes = top_muxes, 551 }; 552 553 static int mt7629_mcucfg_probe(struct udevice *dev) 554 { 555 void __iomem *base; 556 557 base = dev_read_addr_ptr(dev); 558 if (!base) 559 return -ENOENT; 560 561 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, 562 AXI_DIV_SEL(0x12)); 563 clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK, 564 MCU_BUS_SEL(0x1)); 565 566 return 0; 567 } 568 569 static int mt7629_apmixedsys_probe(struct udevice *dev) 570 { 571 struct mtk_clk_priv *priv = dev_get_priv(dev); 572 int ret; 573 574 ret = mtk_common_clk_init(dev, &mt7629_clk_tree); 575 if (ret) 576 return ret; 577 578 /* reduce clock square disable time */ 579 writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0); 580 /* extend pwr/iso control timing to 1us */ 581 writel(0x80008, priv->base + MT7629_PLL_ISO_CON0); 582 583 return 0; 584 } 585 586 static int mt7629_topckgen_probe(struct udevice *dev) 587 { 588 return mtk_common_clk_init(dev, &mt7629_clk_tree); 589 } 590 591 static int mt7629_infracfg_probe(struct udevice *dev) 592 { 593 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs); 594 } 595 596 static int mt7629_pericfg_probe(struct udevice *dev) 597 { 598 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs); 599 } 600 601 static int mt7629_ethsys_probe(struct udevice *dev) 602 { 603 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs); 604 } 605 606 static int mt7629_ethsys_bind(struct udevice *dev) 607 { 608 int ret = 0; 609 610 #if CONFIG_IS_ENABLED(RESET_MEDIATEK) 611 ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1); 612 if (ret) 613 debug("Warning: failed to bind ethsys reset controller\n"); 614 #endif 615 616 return ret; 617 } 618 619 static int mt7629_sgmiisys_probe(struct udevice *dev) 620 { 621 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs); 622 } 623 624 static const struct udevice_id mt7629_apmixed_compat[] = { 625 { .compatible = "mediatek,mt7629-apmixedsys" }, 626 { } 627 }; 628 629 static const struct udevice_id mt7629_topckgen_compat[] = { 630 { .compatible = "mediatek,mt7629-topckgen" }, 631 { } 632 }; 633 634 static const struct udevice_id mt7629_infracfg_compat[] = { 635 { .compatible = "mediatek,mt7629-infracfg", }, 636 { } 637 }; 638 639 static const struct udevice_id mt7629_pericfg_compat[] = { 640 { .compatible = "mediatek,mt7629-pericfg", }, 641 { } 642 }; 643 644 static const struct udevice_id mt7629_ethsys_compat[] = { 645 { .compatible = "mediatek,mt7629-ethsys", }, 646 { } 647 }; 648 649 static const struct udevice_id mt7629_sgmiisys_compat[] = { 650 { .compatible = "mediatek,mt7629-sgmiisys", }, 651 { } 652 }; 653 654 static const struct udevice_id mt7629_mcucfg_compat[] = { 655 { .compatible = "mediatek,mt7629-mcucfg" }, 656 { } 657 }; 658 659 U_BOOT_DRIVER(mtk_mcucfg) = { 660 .name = "mt7629-mcucfg", 661 .id = UCLASS_SYSCON, 662 .of_match = mt7629_mcucfg_compat, 663 .probe = mt7629_mcucfg_probe, 664 .flags = DM_FLAG_PRE_RELOC, 665 }; 666 667 U_BOOT_DRIVER(mtk_clk_apmixedsys) = { 668 .name = "mt7629-clock-apmixedsys", 669 .id = UCLASS_CLK, 670 .of_match = mt7629_apmixed_compat, 671 .probe = mt7629_apmixedsys_probe, 672 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), 673 .ops = &mtk_clk_apmixedsys_ops, 674 .flags = DM_FLAG_PRE_RELOC, 675 }; 676 677 U_BOOT_DRIVER(mtk_clk_topckgen) = { 678 .name = "mt7629-clock-topckgen", 679 .id = UCLASS_CLK, 680 .of_match = mt7629_topckgen_compat, 681 .probe = mt7629_topckgen_probe, 682 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), 683 .ops = &mtk_clk_topckgen_ops, 684 .flags = DM_FLAG_PRE_RELOC, 685 }; 686 687 U_BOOT_DRIVER(mtk_clk_infracfg) = { 688 .name = "mt7629-clock-infracfg", 689 .id = UCLASS_CLK, 690 .of_match = mt7629_infracfg_compat, 691 .probe = mt7629_infracfg_probe, 692 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 693 .ops = &mtk_clk_gate_ops, 694 .flags = DM_FLAG_PRE_RELOC, 695 }; 696 697 U_BOOT_DRIVER(mtk_clk_pericfg) = { 698 .name = "mt7629-clock-pericfg", 699 .id = UCLASS_CLK, 700 .of_match = mt7629_pericfg_compat, 701 .probe = mt7629_pericfg_probe, 702 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 703 .ops = &mtk_clk_gate_ops, 704 .flags = DM_FLAG_PRE_RELOC, 705 }; 706 707 U_BOOT_DRIVER(mtk_clk_ethsys) = { 708 .name = "mt7629-clock-ethsys", 709 .id = UCLASS_CLK, 710 .of_match = mt7629_ethsys_compat, 711 .probe = mt7629_ethsys_probe, 712 .bind = mt7629_ethsys_bind, 713 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 714 .ops = &mtk_clk_gate_ops, 715 }; 716 717 U_BOOT_DRIVER(mtk_clk_sgmiisys) = { 718 .name = "mt7629-clock-sgmiisys", 719 .id = UCLASS_CLK, 720 .of_match = mt7629_sgmiisys_compat, 721 .probe = mt7629_sgmiisys_probe, 722 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 723 .ops = &mtk_clk_gate_ops, 724 }; 725