1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek clock driver for MT7623 SoC 4 * 5 * Copyright (C) 2018 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <asm/arch-mediatek/reset.h> 12 #include <asm/io.h> 13 #include <dt-bindings/clock/mt7623-clk.h> 14 15 #include "clk-mtk.h" 16 17 #define MT7623_CLKSQ_STB_CON0 0x18 18 #define MT7623_PLL_ISO_CON0 0x24 19 #define MT7623_PLL_FMAX (2000UL * MHZ) 20 #define MT7623_CON0_RST_BAR BIT(27) 21 22 #define MCU_AXI_DIV 0x60 23 #define AXI_DIV_MSK GENMASK(4, 0) 24 #define AXI_DIV_SEL(x) (x) 25 26 /* apmixedsys */ 27 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 28 _pd_shift, _pcw_reg, _pcw_shift) { \ 29 .id = _id, \ 30 .reg = _reg, \ 31 .pwr_reg = _pwr_reg, \ 32 .en_mask = _en_mask, \ 33 .rst_bar_mask = MT7623_CON0_RST_BAR, \ 34 .fmax = MT7623_PLL_FMAX, \ 35 .flags = _flags, \ 36 .pcwbits = _pcwbits, \ 37 .pd_reg = _pd_reg, \ 38 .pd_shift = _pd_shift, \ 39 .pcw_reg = _pcw_reg, \ 40 .pcw_shift = _pcw_shift, \ 41 } 42 43 static const struct mtk_pll_data apmixed_plls[] = { 44 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0, 45 21, 0x204, 24, 0x204, 0), 46 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, 47 21, 0x210, 4, 0x214, 0), 48 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, 49 7, 0x220, 4, 0x224, 14), 50 PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0, 51 21, 0x230, 4, 0x234, 0), 52 PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0, 53 21, 0x240, 4, 0x244, 0), 54 PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0, 55 21, 0x250, 4, 0x254, 0), 56 PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0, 57 31, 0x270, 4, 0x274, 0), 58 PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0, 59 31, 0x280, 4, 0x284, 0), 60 PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0, 61 31, 0x290, 4, 0x294, 0), 62 PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0, 63 31, 0x2a0, 4, 0x2a4, 0), 64 PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0, 65 31, 0x2b0, 4, 0x2b4, 0), 66 PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0, 67 31, 0x2c0, 4, 0x2c4, 0), 68 PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0, 69 21, 0x2d0, 4, 0x2d4, 0), 70 }; 71 72 /* topckgen */ 73 #define FACTOR0(_id, _parent, _mult, _div) \ 74 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 75 76 #define FACTOR1(_id, _parent, _mult, _div) \ 77 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 78 79 #define FACTOR2(_id, _parent, _mult, _div) \ 80 FACTOR(_id, _parent, _mult, _div, 0) 81 82 static const struct mtk_fixed_clk top_fixed_clks[] = { 83 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ), 84 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ), 85 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ), 86 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ), 87 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ), 88 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ), 89 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ), 90 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ), 91 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ), 92 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ), 93 FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000), 94 FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ), 95 FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0), 96 FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0), 97 FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0), 98 }; 99 100 static const struct mtk_fixed_factor top_fixed_divs[] = { 101 FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1), 102 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), 103 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), 104 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), 105 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), 106 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2), 107 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4), 108 FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8), 109 FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16), 110 FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2), 111 FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4), 112 FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8), 113 FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2), 114 FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4), 115 FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2), 116 FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4), 117 118 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1), 119 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), 120 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), 121 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), 122 FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7), 123 FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26), 124 FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52), 125 FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108), 126 FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26), 127 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2), 128 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4), 129 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8), 130 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2), 131 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4), 132 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8), 133 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16), 134 FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32), 135 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2), 136 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4), 137 FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8), 138 139 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), 140 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), 141 FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4), 142 FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8), 143 144 FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1), 145 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2), 146 147 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2), 148 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4), 149 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1), 150 151 FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1), 152 FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2), 153 FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4), 154 155 FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1), 156 FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1), 157 FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2), 158 159 FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1), 160 FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2), 161 FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4), 162 163 FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1), 164 FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2), 165 FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3), 166 167 FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1), 168 169 FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1), 170 FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4), 171 FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8), 172 FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16), 173 FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24), 174 175 FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3), 176 FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3), 177 FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3), 178 FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1), 179 FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1), 180 FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), 181 FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793), 182 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), 183 FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1), 184 }; 185 186 static const int axi_parents[] = { 187 CLK_XTAL, 188 CLK_TOP_SYSPLL1_D2, 189 CLK_TOP_SYSPLL_D5, 190 CLK_TOP_SYSPLL1_D4, 191 CLK_TOP_UNIVPLL_D5, 192 CLK_TOP_UNIVPLL2_D2, 193 CLK_TOP_MMPLL_D2, 194 CLK_TOP_DMPLL_D2 195 }; 196 197 static const int mem_parents[] = { 198 CLK_XTAL, 199 CLK_TOP_DMPLL 200 }; 201 202 static const int ddrphycfg_parents[] = { 203 CLK_XTAL, 204 CLK_TOP_SYSPLL1_D8 205 }; 206 207 static const int mm_parents[] = { 208 CLK_XTAL, 209 CLK_TOP_VENCPLL, 210 CLK_TOP_SYSPLL1_D2, 211 CLK_TOP_SYSPLL1_D4, 212 CLK_TOP_UNIVPLL_D5, 213 CLK_TOP_UNIVPLL1_D2, 214 CLK_TOP_UNIVPLL2_D2, 215 CLK_TOP_DMPLL 216 }; 217 218 static const int pwm_parents[] = { 219 CLK_XTAL, 220 CLK_TOP_UNIVPLL2_D4, 221 CLK_TOP_UNIVPLL3_D2, 222 CLK_TOP_UNIVPLL1_D4 223 }; 224 225 static const int vdec_parents[] = { 226 CLK_XTAL, 227 CLK_TOP_VDECPLL, 228 CLK_TOP_SYSPLL_D5, 229 CLK_TOP_SYSPLL1_D4, 230 CLK_TOP_UNIVPLL_D5, 231 CLK_TOP_UNIVPLL2_D2, 232 CLK_TOP_VENCPLL, 233 CLK_TOP_MSDCPLL_D2, 234 CLK_TOP_MMPLL_D2 235 }; 236 237 static const int mfg_parents[] = { 238 CLK_XTAL, 239 CLK_TOP_MMPLL, 240 CLK_TOP_DMPLL_X2, 241 CLK_TOP_MSDCPLL, 242 CLK_XTAL, 243 CLK_TOP_SYSPLL_D3, 244 CLK_TOP_UNIVPLL_D3, 245 CLK_TOP_UNIVPLL1_D2 246 }; 247 248 static const int camtg_parents[] = { 249 CLK_XTAL, 250 CLK_TOP_UNIVPLL_D26, 251 CLK_TOP_UNIVPLL2_D2, 252 CLK_TOP_SYSPLL3_D2, 253 CLK_TOP_SYSPLL3_D4, 254 CLK_TOP_MSDCPLL_D2, 255 CLK_TOP_MMPLL_D2 256 }; 257 258 static const int uart_parents[] = { 259 CLK_XTAL, 260 CLK_TOP_UNIVPLL2_D8 261 }; 262 263 static const int spi_parents[] = { 264 CLK_XTAL, 265 CLK_TOP_SYSPLL3_D2, 266 CLK_TOP_SYSPLL4_D2, 267 CLK_TOP_UNIVPLL2_D4, 268 CLK_TOP_UNIVPLL1_D8 269 }; 270 271 static const int usb20_parents[] = { 272 CLK_XTAL, 273 CLK_TOP_UNIVPLL1_D8, 274 CLK_TOP_UNIVPLL3_D4 275 }; 276 277 static const int msdc30_parents[] = { 278 CLK_XTAL, 279 CLK_TOP_MSDCPLL_D2, 280 CLK_TOP_SYSPLL2_D2, 281 CLK_TOP_SYSPLL1_D4, 282 CLK_TOP_UNIVPLL1_D4, 283 CLK_TOP_UNIVPLL2_D4, 284 }; 285 286 static const int aud_intbus_parents[] = { 287 CLK_XTAL, 288 CLK_TOP_SYSPLL1_D4, 289 CLK_TOP_SYSPLL3_D2, 290 CLK_TOP_SYSPLL4_D2, 291 CLK_TOP_UNIVPLL3_D2, 292 CLK_TOP_UNIVPLL2_D4 293 }; 294 295 static const int pmicspi_parents[] = { 296 CLK_XTAL, 297 CLK_TOP_SYSPLL1_D8, 298 CLK_TOP_SYSPLL2_D4, 299 CLK_TOP_SYSPLL4_D2, 300 CLK_TOP_SYSPLL3_D4, 301 CLK_TOP_SYSPLL2_D8, 302 CLK_TOP_SYSPLL1_D16, 303 CLK_TOP_UNIVPLL3_D4, 304 CLK_TOP_UNIVPLL_D26, 305 CLK_TOP_DMPLL_D2, 306 CLK_TOP_DMPLL_D4 307 }; 308 309 static const int scp_parents[] = { 310 CLK_XTAL, 311 CLK_TOP_SYSPLL1_D8, 312 CLK_TOP_DMPLL_D2, 313 CLK_TOP_DMPLL_D4 314 }; 315 316 static const int dpi0_tve_parents[] = { 317 CLK_XTAL, 318 CLK_TOP_MIPIPLL, 319 CLK_TOP_MIPIPLL_D2, 320 CLK_TOP_MIPIPLL_D4, 321 CLK_XTAL, 322 CLK_TOP_TVDPLL, 323 CLK_TOP_TVDPLL_D2, 324 CLK_TOP_TVDPLL_D4 325 }; 326 327 static const int dpi1_parents[] = { 328 CLK_XTAL, 329 CLK_TOP_TVDPLL, 330 CLK_TOP_TVDPLL_D2, 331 CLK_TOP_TVDPLL_D4 332 }; 333 334 static const int hdmi_parents[] = { 335 CLK_XTAL, 336 CLK_TOP_HDMIPLL, 337 CLK_TOP_HDMIPLL_D2, 338 CLK_TOP_HDMIPLL_D3 339 }; 340 341 static const int apll_parents[] = { 342 CLK_XTAL, 343 CLK_TOP_AUDPLL, 344 CLK_TOP_AUDPLL_D4, 345 CLK_TOP_AUDPLL_D8, 346 CLK_TOP_AUDPLL_D16, 347 CLK_TOP_AUDPLL_D24, 348 CLK_XTAL, 349 CLK_XTAL 350 }; 351 352 static const int rtc_parents[] = { 353 CLK_TOP_32K_INTERNAL, 354 CLK_TOP_32K_EXTERNAL, 355 CLK_XTAL, 356 CLK_TOP_UNIVPLL3_D8 357 }; 358 359 static const int nfi2x_parents[] = { 360 CLK_XTAL, 361 CLK_TOP_SYSPLL2_D2, 362 CLK_TOP_SYSPLL_D7, 363 CLK_TOP_UNIVPLL3_D2, 364 CLK_TOP_SYSPLL2_D4, 365 CLK_TOP_UNIVPLL3_D4, 366 CLK_TOP_SYSPLL4_D4, 367 CLK_XTAL 368 }; 369 370 static const int emmc_hclk_parents[] = { 371 CLK_XTAL, 372 CLK_TOP_SYSPLL1_D2, 373 CLK_TOP_SYSPLL1_D4, 374 CLK_TOP_SYSPLL2_D2 375 }; 376 377 static const int flash_parents[] = { 378 CLK_TOP_CLK26M_D8, 379 CLK_XTAL, 380 CLK_TOP_SYSPLL2_D8, 381 CLK_TOP_SYSPLL3_D4, 382 CLK_TOP_UNIVPLL3_D4, 383 CLK_TOP_SYSPLL4_D2, 384 CLK_TOP_SYSPLL2_D4, 385 CLK_TOP_UNIVPLL2_D4 386 }; 387 388 static const int di_parents[] = { 389 CLK_XTAL, 390 CLK_TOP_TVD2PLL, 391 CLK_TOP_TVD2PLL_D2, 392 CLK_XTAL 393 }; 394 395 static const int nr_osd_parents[] = { 396 CLK_XTAL, 397 CLK_TOP_VENCPLL, 398 CLK_TOP_SYSPLL1_D2, 399 CLK_TOP_SYSPLL1_D4, 400 CLK_TOP_UNIVPLL_D5, 401 CLK_TOP_UNIVPLL1_D2, 402 CLK_TOP_UNIVPLL2_D2, 403 CLK_TOP_DMPLL 404 }; 405 406 static const int hdmirx_bist_parents[] = { 407 CLK_XTAL, 408 CLK_TOP_SYSPLL_D3, 409 CLK_XTAL, 410 CLK_TOP_SYSPLL1_D16, 411 CLK_TOP_SYSPLL4_D2, 412 CLK_TOP_SYSPLL1_D4, 413 CLK_TOP_VENCPLL, 414 CLK_XTAL 415 }; 416 417 static const int intdir_parents[] = { 418 CLK_XTAL, 419 CLK_TOP_MMPLL, 420 CLK_TOP_SYSPLL_D2, 421 CLK_TOP_UNIVPLL_D2 422 }; 423 424 static const int asm_parents[] = { 425 CLK_XTAL, 426 CLK_TOP_UNIVPLL2_D4, 427 CLK_TOP_UNIVPLL2_D2, 428 CLK_TOP_SYSPLL_D5 429 }; 430 431 static const int ms_card_parents[] = { 432 CLK_XTAL, 433 CLK_TOP_UNIVPLL3_D8, 434 CLK_TOP_SYSPLL4_D4 435 }; 436 437 static const int ethif_parents[] = { 438 CLK_XTAL, 439 CLK_TOP_SYSPLL1_D2, 440 CLK_TOP_SYSPLL_D5, 441 CLK_TOP_SYSPLL1_D4, 442 CLK_TOP_UNIVPLL_D5, 443 CLK_TOP_UNIVPLL1_D2, 444 CLK_TOP_DMPLL, 445 CLK_TOP_DMPLL_D2 446 }; 447 448 static const int hdmirx_parents[] = { 449 CLK_XTAL, 450 CLK_TOP_UNIVPLL_D52 451 }; 452 453 static const int cmsys_parents[] = { 454 CLK_XTAL, 455 CLK_TOP_SYSPLL1_D2, 456 CLK_TOP_UNIVPLL1_D2, 457 CLK_TOP_UNIVPLL_D5, 458 CLK_TOP_SYSPLL_D5, 459 CLK_TOP_SYSPLL2_D2, 460 CLK_TOP_SYSPLL1_D4, 461 CLK_TOP_SYSPLL3_D2, 462 CLK_TOP_SYSPLL2_D4, 463 CLK_TOP_SYSPLL1_D8, 464 CLK_XTAL, 465 CLK_XTAL, 466 CLK_XTAL, 467 CLK_XTAL, 468 CLK_XTAL 469 }; 470 471 static const int clk_8bdac_parents[] = { 472 CLK_TOP_32K_INTERNAL, 473 CLK_TOP_8BDAC, 474 CLK_XTAL, 475 CLK_XTAL 476 }; 477 478 static const int aud2dvd_parents[] = { 479 CLK_TOP_AUD_48K_TIMING, 480 CLK_TOP_AUD_44K_TIMING 481 }; 482 483 static const int padmclk_parents[] = { 484 CLK_XTAL, 485 CLK_TOP_UNIVPLL_D26, 486 CLK_TOP_UNIVPLL_D52, 487 CLK_TOP_UNIVPLL_D108, 488 CLK_TOP_UNIVPLL2_D8, 489 CLK_TOP_UNIVPLL2_D16, 490 CLK_TOP_UNIVPLL2_D32 491 }; 492 493 static const int aud_mux_parents[] = { 494 CLK_XTAL, 495 CLK_TOP_AUD1PLL_98M, 496 CLK_TOP_AUD2PLL_90M, 497 CLK_TOP_HADDS2PLL_98M, 498 CLK_TOP_AUD_EXTCK1_DIV, 499 CLK_TOP_AUD_EXTCK2_DIV 500 }; 501 502 static const int aud_src_parents[] = { 503 CLK_TOP_AUD_MUX1_SEL, 504 CLK_TOP_AUD_MUX2_SEL 505 }; 506 507 static const struct mtk_composite top_muxes[] = { 508 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), 509 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), 510 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), 511 MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31, 512 CLK_DOMAIN_SCPSYS), 513 514 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), 515 MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15), 516 MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23, 517 CLK_DOMAIN_SCPSYS), 518 MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31), 519 520 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), 521 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15), 522 MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23), 523 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31), 524 525 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7), 526 MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15), 527 MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23), 528 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31), 529 530 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7), 531 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15), 532 MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23), 533 MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31), 534 535 MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7), 536 MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15), 537 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23), 538 539 MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7), 540 MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15), 541 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31), 542 543 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7), 544 MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15), 545 MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23), 546 MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31), 547 548 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7), 549 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15), 550 MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23), 551 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31), 552 553 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7), 554 MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23), 555 MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, 556 CLK_DOMAIN_SCPSYS), 557 558 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7), 559 MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15), 560 MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23), 561 562 MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31), 563 MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7), 564 MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15), 565 MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23), 566 567 MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3), 568 569 MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3), 570 MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3), 571 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3), 572 573 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23), 574 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24), 575 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25), 576 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26), 577 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27), 578 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28), 579 }; 580 581 /* infracfg */ 582 static const struct mtk_gate_regs infra_cg_regs = { 583 .set_ofs = 0x40, 584 .clr_ofs = 0x44, 585 .sta_ofs = 0x48, 586 }; 587 588 #define GATE_INFRA(_id, _parent, _shift) { \ 589 .id = _id, \ 590 .parent = _parent, \ 591 .regs = &infra_cg_regs, \ 592 .shift = _shift, \ 593 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 594 } 595 596 static const struct mtk_gate infra_cgs[] = { 597 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0), 598 GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), 599 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), 600 GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), 601 GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5), 602 GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6), 603 GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), 604 GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), 605 GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), 606 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13), 607 GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14), 608 GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15), 609 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16), 610 GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18), 611 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19), 612 GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22), 613 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23), 614 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24), 615 }; 616 617 /* pericfg */ 618 static const struct mtk_gate_regs peri0_cg_regs = { 619 .set_ofs = 0x8, 620 .clr_ofs = 0x10, 621 .sta_ofs = 0x18, 622 }; 623 624 static const struct mtk_gate_regs peri1_cg_regs = { 625 .set_ofs = 0xC, 626 .clr_ofs = 0x14, 627 .sta_ofs = 0x1C, 628 }; 629 630 #define GATE_PERI0(_id, _parent, _shift) { \ 631 .id = _id, \ 632 .parent = _parent, \ 633 .regs = &peri0_cg_regs, \ 634 .shift = _shift, \ 635 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 636 } 637 638 #define GATE_PERI1(_id, _parent, _shift) { \ 639 .id = _id, \ 640 .parent = _parent, \ 641 .regs = &peri1_cg_regs, \ 642 .shift = _shift, \ 643 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 644 } 645 646 static const struct mtk_gate peri_cgs[] = { 647 GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0), 648 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1), 649 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2), 650 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3), 651 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4), 652 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5), 653 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6), 654 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7), 655 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8), 656 GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9), 657 GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10), 658 GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11), 659 GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12), 660 GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13), 661 GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14), 662 GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15), 663 GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16), 664 GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17), 665 GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18), 666 GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19), 667 GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20), 668 GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21), 669 GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22), 670 GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23), 671 GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), 672 GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), 673 GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), 674 GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27), 675 GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28), 676 GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), 677 GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30), 678 GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), 679 680 GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), 681 GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1), 682 GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2), 683 GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3), 684 GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4), 685 GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5), 686 GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6), 687 GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7), 688 GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8), 689 GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9), 690 GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10), 691 GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11), 692 }; 693 694 /* ethsys */ 695 static const struct mtk_gate_regs eth_cg_regs = { 696 .sta_ofs = 0x30, 697 }; 698 699 #define GATE_ETH(_id, _parent, _shift, _flag) { \ 700 .id = _id, \ 701 .parent = _parent, \ 702 .regs = ð_cg_regs, \ 703 .shift = _shift, \ 704 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \ 705 } 706 707 #define GATE_ETH0(_id, _parent, _shift) \ 708 GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED) 709 710 #define GATE_ETH1(_id, _parent, _shift) \ 711 GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN) 712 713 static const struct mtk_gate eth_cgs[] = { 714 GATE_ETH1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5), 715 GATE_ETH1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6), 716 GATE_ETH0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7), 717 GATE_ETH1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8), 718 GATE_ETH1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11), 719 GATE_ETH1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14), 720 GATE_ETH1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17), 721 GATE_ETH1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29), 722 }; 723 724 static const struct mtk_clk_tree mt7623_clk_tree = { 725 .xtal_rate = 26 * MHZ, 726 .xtal2_rate = 26 * MHZ, 727 .fdivs_offs = CLK_TOP_SYSPLL, 728 .muxes_offs = CLK_TOP_AXI_SEL, 729 .plls = apmixed_plls, 730 .fclks = top_fixed_clks, 731 .fdivs = top_fixed_divs, 732 .muxes = top_muxes, 733 }; 734 735 static int mt7623_mcucfg_probe(struct udevice *dev) 736 { 737 void __iomem *base; 738 739 base = dev_read_addr_ptr(dev); 740 if (!base) 741 return -ENOENT; 742 743 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, 744 AXI_DIV_SEL(0x12)); 745 746 return 0; 747 } 748 749 static int mt7623_apmixedsys_probe(struct udevice *dev) 750 { 751 struct mtk_clk_priv *priv = dev_get_priv(dev); 752 int ret; 753 754 ret = mtk_common_clk_init(dev, &mt7623_clk_tree); 755 if (ret) 756 return ret; 757 758 /* reduce clock square disable time */ 759 writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0); 760 /* extend control timing to 1us */ 761 writel(0x888, priv->base + MT7623_PLL_ISO_CON0); 762 763 return 0; 764 } 765 766 static int mt7623_topckgen_probe(struct udevice *dev) 767 { 768 return mtk_common_clk_init(dev, &mt7623_clk_tree); 769 } 770 771 static int mt7623_infracfg_probe(struct udevice *dev) 772 { 773 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs); 774 } 775 776 static int mt7623_pericfg_probe(struct udevice *dev) 777 { 778 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs); 779 } 780 781 static int mt7623_ethsys_probe(struct udevice *dev) 782 { 783 return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs); 784 } 785 786 static int mt7623_ethsys_bind(struct udevice *dev) 787 { 788 int ret = 0; 789 790 #if CONFIG_IS_ENABLED(RESET_MEDIATEK) 791 ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1); 792 if (ret) 793 debug("Warning: failed to bind ethsys reset controller\n"); 794 #endif 795 796 return ret; 797 } 798 799 static const struct udevice_id mt7623_apmixed_compat[] = { 800 { .compatible = "mediatek,mt7623-apmixedsys" }, 801 { } 802 }; 803 804 static const struct udevice_id mt7623_topckgen_compat[] = { 805 { .compatible = "mediatek,mt7623-topckgen" }, 806 { } 807 }; 808 809 static const struct udevice_id mt7623_infracfg_compat[] = { 810 { .compatible = "mediatek,mt7623-infracfg", }, 811 { } 812 }; 813 814 static const struct udevice_id mt7623_pericfg_compat[] = { 815 { .compatible = "mediatek,mt7623-pericfg", }, 816 { } 817 }; 818 819 static const struct udevice_id mt7623_ethsys_compat[] = { 820 { .compatible = "mediatek,mt7623-ethsys" }, 821 { } 822 }; 823 824 static const struct udevice_id mt7623_mcucfg_compat[] = { 825 { .compatible = "mediatek,mt7623-mcucfg" }, 826 { } 827 }; 828 829 U_BOOT_DRIVER(mtk_mcucfg) = { 830 .name = "mt7623-mcucfg", 831 .id = UCLASS_SYSCON, 832 .of_match = mt7623_mcucfg_compat, 833 .probe = mt7623_mcucfg_probe, 834 .flags = DM_FLAG_PRE_RELOC, 835 }; 836 837 U_BOOT_DRIVER(mtk_clk_apmixedsys) = { 838 .name = "mt7623-clock-apmixedsys", 839 .id = UCLASS_CLK, 840 .of_match = mt7623_apmixed_compat, 841 .probe = mt7623_apmixedsys_probe, 842 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), 843 .ops = &mtk_clk_apmixedsys_ops, 844 .flags = DM_FLAG_PRE_RELOC, 845 }; 846 847 U_BOOT_DRIVER(mtk_clk_topckgen) = { 848 .name = "mt7623-clock-topckgen", 849 .id = UCLASS_CLK, 850 .of_match = mt7623_topckgen_compat, 851 .probe = mt7623_topckgen_probe, 852 .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), 853 .ops = &mtk_clk_topckgen_ops, 854 .flags = DM_FLAG_PRE_RELOC, 855 }; 856 857 U_BOOT_DRIVER(mtk_clk_infracfg) = { 858 .name = "mt7623-infracfg", 859 .id = UCLASS_CLK, 860 .of_match = mt7623_infracfg_compat, 861 .probe = mt7623_infracfg_probe, 862 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 863 .ops = &mtk_clk_gate_ops, 864 .flags = DM_FLAG_PRE_RELOC, 865 }; 866 867 U_BOOT_DRIVER(mtk_clk_pericfg) = { 868 .name = "mt7623-pericfg", 869 .id = UCLASS_CLK, 870 .of_match = mt7623_pericfg_compat, 871 .probe = mt7623_pericfg_probe, 872 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 873 .ops = &mtk_clk_gate_ops, 874 .flags = DM_FLAG_PRE_RELOC, 875 }; 876 877 U_BOOT_DRIVER(mtk_clk_ethsys) = { 878 .name = "mt7623-clock-ethsys", 879 .id = UCLASS_CLK, 880 .of_match = mt7623_ethsys_compat, 881 .probe = mt7623_ethsys_probe, 882 .bind = mt7623_ethsys_bind, 883 .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), 884 .ops = &mtk_clk_gate_ops, 885 }; 886