1 /* 2 * Exynos PLL helper functions for clock drivers. 3 * Copyright (C) 2016 Samsung Electronics 4 * Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <div64.h> 12 13 #define PLL145X_MDIV_SHIFT 16 14 #define PLL145X_MDIV_MASK 0x3ff 15 #define PLL145X_PDIV_SHIFT 8 16 #define PLL145X_PDIV_MASK 0x3f 17 #define PLL145X_SDIV_SHIFT 0 18 #define PLL145X_SDIV_MASK 0x7 19 20 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) 21 { 22 unsigned long pll_con1 = readl(con1); 23 unsigned long mdiv, sdiv, pdiv; 24 uint64_t fvco = fin_freq; 25 26 mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; 27 pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; 28 sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; 29 30 fvco *= mdiv; 31 do_div(fvco, (pdiv << sdiv)); 32 return (unsigned long)fvco; 33 } 34