1 /* 2 * ZynqMP clock driver 3 * 4 * Copyright (C) 2016 Xilinx, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <linux/bitops.h> 11 #include <clk-uclass.h> 12 #include <clk.h> 13 #include <asm/arch/sys_proto.h> 14 #include <dm.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020; 19 static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020; 20 static const resource_size_t zynqmp_iou_clkc_base = 0xff180000; 21 22 /* Full power domain clocks */ 23 #define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00) 24 #define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c) 25 #define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18) 26 #define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24) 27 #define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28) 28 #define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c) 29 #define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30) 30 /* Peripheral clocks */ 31 #define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40) 32 #define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44) 33 #define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48) 34 #define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50) 35 #define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54) 36 #define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c) 37 #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60) 38 #define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64) 39 #define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80) 40 #define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94) 41 #define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98) 42 #define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c) 43 #define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0) 44 #define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4) 45 #define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8) 46 #define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8) 47 48 /* Low power domain clocks */ 49 #define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00) 50 #define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10) 51 #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20) 52 #define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24) 53 #define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28) 54 /* Peripheral clocks */ 55 #define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c) 56 #define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30) 57 #define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34) 58 #define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38) 59 #define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c) 60 #define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40) 61 #define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44) 62 #define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48) 63 #define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c) 64 #define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50) 65 #define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54) 66 #define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58) 67 #define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c) 68 #define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60) 69 #define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64) 70 #define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68) 71 #define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70) 72 #define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c) 73 #define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80) 74 #define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84) 75 #define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88) 76 #define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c) 77 #define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90) 78 #define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94) 79 #define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98) 80 #define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0) 81 #define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4) 82 #define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8) 83 #define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac) 84 #define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4) 85 #define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc) 86 #define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4) 87 #define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc) 88 #define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0) 89 #define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4) 90 #define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8) 91 #define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100) 92 #define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104) 93 #define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108) 94 #define IOU_SLCR_GEM_CLK_CTRL (zynqmp_iou_clkc_base + 0x308) 95 #define IOU_SLCR_CAN_MIO_CTRL (zynqmp_iou_clkc_base + 0x304) 96 #define IOU_SLCR_WDT_CLK_SEL (zynqmp_iou_clkc_base + 0x300) 97 98 #define ZYNQ_CLK_MAXDIV 0x3f 99 #define CLK_CTRL_DIV1_SHIFT 16 100 #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) 101 #define CLK_CTRL_DIV0_SHIFT 8 102 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) 103 #define CLK_CTRL_SRCSEL_SHIFT 0 104 #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) 105 #define PLLCTRL_FBDIV_MASK 0x7f00 106 #define PLLCTRL_FBDIV_SHIFT 8 107 #define PLLCTRL_RESET_MASK 1 108 #define PLLCTRL_RESET_SHIFT 0 109 #define PLLCTRL_BYPASS_MASK 0x8 110 #define PLLCTRL_BYPASS_SHFT 3 111 #define PLLCTRL_POST_SRC_SHFT 24 112 #define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT) 113 114 115 #define NUM_MIO_PINS 77 116 117 enum zynqmp_clk { 118 iopll, rpll, 119 apll, dpll, vpll, 120 iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd, 121 acpu, acpu_half, 122 dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp, 123 dp_video_ref, dp_audio_ref, 124 dp_stc_ref, gdma_ref, dpdma_ref, 125 ddr_ref, sata_ref, pcie_ref, 126 gpu_ref, gpu_pp0_ref, gpu_pp1_ref, 127 topsw_main, topsw_lsbus, 128 gtgref0_ref, 129 lpd_switch, lpd_lsbus, 130 usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1, 131 cpu_r5, cpu_r5_core, 132 csu_spb, csu_pll, pcap, 133 iou_switch, 134 gem_tsu_ref, gem_tsu, 135 gem0_ref, gem1_ref, gem2_ref, gem3_ref, 136 gem0_rx, gem1_rx, gem2_rx, gem3_rx, 137 qspi_ref, 138 sdio0_ref, sdio1_ref, 139 uart0_ref, uart1_ref, 140 spi0_ref, spi1_ref, 141 nand_ref, 142 i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1, 143 dll_ref, 144 adma_ref, 145 timestamp_ref, 146 ams_ref, 147 pl0, pl1, pl2, pl3, 148 wdt, 149 clk_max, 150 }; 151 152 static const char * const clk_names[clk_max] = { 153 "iopll", "rpll", "apll", "dpll", 154 "vpll", "iopll_to_fpd", "rpll_to_fpd", 155 "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", 156 "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", 157 "dbg_trace", "dbg_tstmp", "dp_video_ref", 158 "dp_audio_ref", "dp_stc_ref", "gdma_ref", 159 "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", 160 "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", 161 "topsw_main", "topsw_lsbus", "gtgref0_ref", 162 "lpd_switch", "lpd_lsbus", "usb0_bus_ref", 163 "usb1_bus_ref", "usb3_dual_ref", "usb0", 164 "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", 165 "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", 166 "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", 167 "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", 168 "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", 169 "uart0_ref", "uart1_ref", "spi0_ref", 170 "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", 171 "can0_ref", "can1_ref", "can0", "can1", 172 "dll_ref", "adma_ref", "timestamp_ref", 173 "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt" 174 }; 175 176 struct zynqmp_clk_priv { 177 unsigned long ps_clk_freq; 178 unsigned long video_clk; 179 unsigned long pss_alt_ref_clk; 180 unsigned long gt_crx_ref_clk; 181 unsigned long aux_ref_clk; 182 }; 183 184 static u32 zynqmp_clk_get_register(enum zynqmp_clk id) 185 { 186 switch (id) { 187 case iopll: 188 return CRL_APB_IOPLL_CTRL; 189 case rpll: 190 return CRL_APB_RPLL_CTRL; 191 case apll: 192 return CRF_APB_APLL_CTRL; 193 case dpll: 194 return CRF_APB_DPLL_CTRL; 195 case vpll: 196 return CRF_APB_VPLL_CTRL; 197 case acpu: 198 return CRF_APB_ACPU_CTRL; 199 case ddr_ref: 200 return CRF_APB_DDR_CTRL; 201 case qspi_ref: 202 return CRL_APB_QSPI_REF_CTRL; 203 case gem0_ref: 204 return CRL_APB_GEM0_REF_CTRL; 205 case gem1_ref: 206 return CRL_APB_GEM1_REF_CTRL; 207 case gem2_ref: 208 return CRL_APB_GEM2_REF_CTRL; 209 case gem3_ref: 210 return CRL_APB_GEM3_REF_CTRL; 211 case uart0_ref: 212 return CRL_APB_UART0_REF_CTRL; 213 case uart1_ref: 214 return CRL_APB_UART1_REF_CTRL; 215 case sdio0_ref: 216 return CRL_APB_SDIO0_REF_CTRL; 217 case sdio1_ref: 218 return CRL_APB_SDIO1_REF_CTRL; 219 case spi0_ref: 220 return CRL_APB_SPI0_REF_CTRL; 221 case spi1_ref: 222 return CRL_APB_SPI1_REF_CTRL; 223 case nand_ref: 224 return CRL_APB_NAND_REF_CTRL; 225 case i2c0_ref: 226 return CRL_APB_I2C0_REF_CTRL; 227 case i2c1_ref: 228 return CRL_APB_I2C1_REF_CTRL; 229 case can0_ref: 230 return CRL_APB_CAN0_REF_CTRL; 231 case can1_ref: 232 return CRL_APB_CAN1_REF_CTRL; 233 default: 234 debug("Invalid clk id%d\n", id); 235 } 236 return 0; 237 } 238 239 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl) 240 { 241 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> 242 CLK_CTRL_SRCSEL_SHIFT; 243 244 switch (srcsel) { 245 case 2: 246 return dpll; 247 case 3: 248 return vpll; 249 case 0 ... 1: 250 default: 251 return apll; 252 } 253 } 254 255 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl) 256 { 257 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> 258 CLK_CTRL_SRCSEL_SHIFT; 259 260 switch (srcsel) { 261 case 1: 262 return vpll; 263 case 0: 264 default: 265 return dpll; 266 } 267 } 268 269 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl) 270 { 271 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> 272 CLK_CTRL_SRCSEL_SHIFT; 273 274 switch (srcsel) { 275 case 2: 276 return rpll; 277 case 3: 278 return dpll; 279 case 0 ... 1: 280 default: 281 return iopll; 282 } 283 } 284 285 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, 286 struct zynqmp_clk_priv *priv, 287 bool is_pre_src) 288 { 289 u32 src_sel; 290 291 if (is_pre_src) 292 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> 293 PLLCTRL_POST_SRC_SHFT; 294 else 295 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> 296 PLLCTRL_POST_SRC_SHFT; 297 298 switch (src_sel) { 299 case 4: 300 return priv->video_clk; 301 case 5: 302 return priv->pss_alt_ref_clk; 303 case 6: 304 return priv->aux_ref_clk; 305 case 7: 306 return priv->gt_crx_ref_clk; 307 case 0 ... 3: 308 default: 309 return priv->ps_clk_freq; 310 } 311 } 312 313 static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv, 314 enum zynqmp_clk id) 315 { 316 u32 clk_ctrl, reset, mul; 317 ulong freq; 318 int ret; 319 320 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl); 321 if (ret) { 322 printf("%s mio read fail\n", __func__); 323 return -EIO; 324 } 325 326 if (clk_ctrl & PLLCTRL_BYPASS_MASK) 327 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0); 328 else 329 freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1); 330 331 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; 332 if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK)) 333 return 0; 334 335 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; 336 337 freq *= mul; 338 339 if (clk_ctrl & (1 << 16)) 340 freq /= 2; 341 342 return freq; 343 } 344 345 static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv, 346 enum zynqmp_clk id) 347 { 348 u32 clk_ctrl, div; 349 enum zynqmp_clk pll; 350 int ret; 351 unsigned long pllrate; 352 353 ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl); 354 if (ret) { 355 printf("%s mio read fail\n", __func__); 356 return -EIO; 357 } 358 359 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; 360 361 pll = zynqmp_clk_get_cpu_pll(clk_ctrl); 362 pllrate = zynqmp_clk_get_pll_rate(priv, pll); 363 if (IS_ERR_VALUE(pllrate)) 364 return pllrate; 365 366 return DIV_ROUND_CLOSEST(pllrate, div); 367 } 368 369 static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv) 370 { 371 u32 clk_ctrl, div; 372 enum zynqmp_clk pll; 373 int ret; 374 ulong pllrate; 375 376 ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl); 377 if (ret) { 378 printf("%s mio read fail\n", __func__); 379 return -EIO; 380 } 381 382 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; 383 384 pll = zynqmp_clk_get_ddr_pll(clk_ctrl); 385 pllrate = zynqmp_clk_get_pll_rate(priv, pll); 386 if (IS_ERR_VALUE(pllrate)) 387 return pllrate; 388 389 return DIV_ROUND_CLOSEST(pllrate, div); 390 } 391 392 static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv, 393 enum zynqmp_clk id, bool two_divs) 394 { 395 enum zynqmp_clk pll; 396 u32 clk_ctrl, div0; 397 u32 div1 = 1; 398 int ret; 399 ulong pllrate; 400 401 ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl); 402 if (ret) { 403 printf("%s mio read fail\n", __func__); 404 return -EIO; 405 } 406 407 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; 408 if (!div0) 409 div0 = 1; 410 411 if (two_divs) { 412 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; 413 if (!div1) 414 div1 = 1; 415 } 416 417 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); 418 pllrate = zynqmp_clk_get_pll_rate(priv, pll); 419 if (IS_ERR_VALUE(pllrate)) 420 return pllrate; 421 422 return 423 DIV_ROUND_CLOSEST( 424 DIV_ROUND_CLOSEST(pllrate, div0), div1); 425 } 426 427 static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate, 428 ulong pll_rate, 429 u32 *div0, u32 *div1) 430 { 431 long new_err, best_err = (long)(~0UL >> 1); 432 ulong new_rate, best_rate = 0; 433 u32 d0, d1; 434 435 for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { 436 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { 437 new_rate = DIV_ROUND_CLOSEST( 438 DIV_ROUND_CLOSEST(pll_rate, d0), d1); 439 new_err = abs(new_rate - rate); 440 441 if (new_err < best_err) { 442 *div0 = d0; 443 *div1 = d1; 444 best_err = new_err; 445 best_rate = new_rate; 446 } 447 } 448 } 449 450 return best_rate; 451 } 452 453 static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv, 454 enum zynqmp_clk id, ulong rate, 455 bool two_divs) 456 { 457 enum zynqmp_clk pll; 458 u32 clk_ctrl, div0 = 0, div1 = 0; 459 ulong pll_rate, new_rate; 460 u32 reg; 461 int ret; 462 u32 mask; 463 464 reg = zynqmp_clk_get_register(id); 465 ret = zynqmp_mmio_read(reg, &clk_ctrl); 466 if (ret) { 467 printf("%s mio read fail\n", __func__); 468 return -EIO; 469 } 470 471 pll = zynqmp_clk_get_peripheral_pll(clk_ctrl); 472 pll_rate = zynqmp_clk_get_pll_rate(priv, pll); 473 if (IS_ERR_VALUE(pll_rate)) 474 return pll_rate; 475 476 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; 477 if (two_divs) { 478 clk_ctrl &= ~CLK_CTRL_DIV1_MASK; 479 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, 480 &div0, &div1); 481 clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; 482 } else { 483 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); 484 if (div0 > ZYNQ_CLK_MAXDIV) 485 div0 = ZYNQ_CLK_MAXDIV; 486 new_rate = DIV_ROUND_CLOSEST(rate, div0); 487 } 488 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; 489 490 mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) | 491 (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT); 492 493 ret = zynqmp_mmio_write(reg, mask, clk_ctrl); 494 if (ret) { 495 printf("%s mio write fail\n", __func__); 496 return -EIO; 497 } 498 499 return new_rate; 500 } 501 502 static ulong zynqmp_clk_get_rate(struct clk *clk) 503 { 504 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev); 505 enum zynqmp_clk id = clk->id; 506 bool two_divs = false; 507 508 switch (id) { 509 case iopll ... vpll: 510 return zynqmp_clk_get_pll_rate(priv, id); 511 case acpu: 512 return zynqmp_clk_get_cpu_rate(priv, id); 513 case ddr_ref: 514 return zynqmp_clk_get_ddr_rate(priv); 515 case gem0_ref ... gem3_ref: 516 case qspi_ref ... can1_ref: 517 two_divs = true; 518 return zynqmp_clk_get_peripheral_rate(priv, id, two_divs); 519 default: 520 return -ENXIO; 521 } 522 } 523 524 static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) 525 { 526 struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev); 527 enum zynqmp_clk id = clk->id; 528 bool two_divs = true; 529 530 switch (id) { 531 case gem0_ref ... gem3_ref: 532 case qspi_ref ... can1_ref: 533 return zynqmp_clk_set_peripheral_rate(priv, id, 534 rate, two_divs); 535 default: 536 return -ENXIO; 537 } 538 } 539 540 int soc_clk_dump(void) 541 { 542 struct udevice *dev; 543 int i, ret; 544 545 ret = uclass_get_device_by_driver(UCLASS_CLK, 546 DM_GET_DRIVER(zynqmp_clk), &dev); 547 if (ret) 548 return ret; 549 550 printf("clk\t\tfrequency\n"); 551 for (i = 0; i < clk_max; i++) { 552 const char *name = clk_names[i]; 553 if (name) { 554 struct clk clk; 555 unsigned long rate; 556 557 clk.id = i; 558 ret = clk_request(dev, &clk); 559 if (ret < 0) 560 return ret; 561 562 rate = clk_get_rate(&clk); 563 564 clk_free(&clk); 565 566 if ((rate == (unsigned long)-ENOSYS) || 567 (rate == (unsigned long)-ENXIO) || 568 (rate == (unsigned long)-EIO)) 569 printf("%10s%20s\n", name, "unknown"); 570 else 571 printf("%10s%20lu\n", name, rate); 572 } 573 } 574 575 return 0; 576 } 577 578 static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq) 579 { 580 struct clk clk; 581 int ret; 582 583 ret = clk_get_by_name(dev, name, &clk); 584 if (ret < 0) { 585 dev_err(dev, "failed to get %s\n", name); 586 return ret; 587 } 588 589 *freq = clk_get_rate(&clk); 590 if (IS_ERR_VALUE(*freq)) { 591 dev_err(dev, "failed to get rate %s\n", name); 592 return -EINVAL; 593 } 594 595 return 0; 596 } 597 static int zynqmp_clk_probe(struct udevice *dev) 598 { 599 int ret; 600 struct zynqmp_clk_priv *priv = dev_get_priv(dev); 601 602 debug("%s\n", __func__); 603 ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq); 604 if (ret < 0) 605 return -EINVAL; 606 607 ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk); 608 if (ret < 0) 609 return -EINVAL; 610 611 ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev, 612 &priv->pss_alt_ref_clk); 613 if (ret < 0) 614 return -EINVAL; 615 616 ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk); 617 if (ret < 0) 618 return -EINVAL; 619 620 ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev, 621 &priv->gt_crx_ref_clk); 622 if (ret < 0) 623 return -EINVAL; 624 625 return 0; 626 } 627 628 static struct clk_ops zynqmp_clk_ops = { 629 .set_rate = zynqmp_clk_set_rate, 630 .get_rate = zynqmp_clk_get_rate, 631 }; 632 633 static const struct udevice_id zynqmp_clk_ids[] = { 634 { .compatible = "xlnx,zynqmp-clkc" }, 635 { } 636 }; 637 638 U_BOOT_DRIVER(zynqmp_clk) = { 639 .name = "zynqmp-clk", 640 .id = UCLASS_CLK, 641 .of_match = zynqmp_clk_ids, 642 .probe = zynqmp_clk_probe, 643 .ops = &zynqmp_clk_ops, 644 .priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv), 645 }; 646