1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <div64.h> 10 #include <dm.h> 11 #include <regmap.h> 12 #include <spl.h> 13 #include <syscon.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <dt-bindings/clock/stm32mp1-clks.h> 17 #include <dt-bindings/clock/stm32mp1-clksrc.h> 18 19 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 20 /* activate clock tree initialization in the driver */ 21 #define STM32MP1_CLOCK_TREE_INIT 22 #endif 23 24 #define MAX_HSI_HZ 64000000 25 26 /* TIMEOUT */ 27 #define TIMEOUT_200MS 200000 28 #define TIMEOUT_1S 1000000 29 30 /* RCC registers */ 31 #define RCC_OCENSETR 0x0C 32 #define RCC_OCENCLRR 0x10 33 #define RCC_HSICFGR 0x18 34 #define RCC_MPCKSELR 0x20 35 #define RCC_ASSCKSELR 0x24 36 #define RCC_RCK12SELR 0x28 37 #define RCC_MPCKDIVR 0x2C 38 #define RCC_AXIDIVR 0x30 39 #define RCC_APB4DIVR 0x3C 40 #define RCC_APB5DIVR 0x40 41 #define RCC_RTCDIVR 0x44 42 #define RCC_MSSCKSELR 0x48 43 #define RCC_PLL1CR 0x80 44 #define RCC_PLL1CFGR1 0x84 45 #define RCC_PLL1CFGR2 0x88 46 #define RCC_PLL1FRACR 0x8C 47 #define RCC_PLL1CSGR 0x90 48 #define RCC_PLL2CR 0x94 49 #define RCC_PLL2CFGR1 0x98 50 #define RCC_PLL2CFGR2 0x9C 51 #define RCC_PLL2FRACR 0xA0 52 #define RCC_PLL2CSGR 0xA4 53 #define RCC_I2C46CKSELR 0xC0 54 #define RCC_CPERCKSELR 0xD0 55 #define RCC_STGENCKSELR 0xD4 56 #define RCC_DDRITFCR 0xD8 57 #define RCC_BDCR 0x140 58 #define RCC_RDLSICR 0x144 59 #define RCC_MP_APB4ENSETR 0x200 60 #define RCC_MP_APB5ENSETR 0x208 61 #define RCC_MP_AHB5ENSETR 0x210 62 #define RCC_MP_AHB6ENSETR 0x218 63 #define RCC_OCRDYR 0x808 64 #define RCC_DBGCFGR 0x80C 65 #define RCC_RCK3SELR 0x820 66 #define RCC_RCK4SELR 0x824 67 #define RCC_MCUDIVR 0x830 68 #define RCC_APB1DIVR 0x834 69 #define RCC_APB2DIVR 0x838 70 #define RCC_APB3DIVR 0x83C 71 #define RCC_PLL3CR 0x880 72 #define RCC_PLL3CFGR1 0x884 73 #define RCC_PLL3CFGR2 0x888 74 #define RCC_PLL3FRACR 0x88C 75 #define RCC_PLL3CSGR 0x890 76 #define RCC_PLL4CR 0x894 77 #define RCC_PLL4CFGR1 0x898 78 #define RCC_PLL4CFGR2 0x89C 79 #define RCC_PLL4FRACR 0x8A0 80 #define RCC_PLL4CSGR 0x8A4 81 #define RCC_I2C12CKSELR 0x8C0 82 #define RCC_I2C35CKSELR 0x8C4 83 #define RCC_UART6CKSELR 0x8E4 84 #define RCC_UART24CKSELR 0x8E8 85 #define RCC_UART35CKSELR 0x8EC 86 #define RCC_UART78CKSELR 0x8F0 87 #define RCC_SDMMC12CKSELR 0x8F4 88 #define RCC_SDMMC3CKSELR 0x8F8 89 #define RCC_ETHCKSELR 0x8FC 90 #define RCC_QSPICKSELR 0x900 91 #define RCC_FMCCKSELR 0x904 92 #define RCC_USBCKSELR 0x91C 93 #define RCC_MP_APB1ENSETR 0xA00 94 #define RCC_MP_APB2ENSETR 0XA08 95 #define RCC_MP_AHB2ENSETR 0xA18 96 #define RCC_MP_AHB4ENSETR 0xA28 97 98 /* used for most of SELR register */ 99 #define RCC_SELR_SRC_MASK GENMASK(2, 0) 100 #define RCC_SELR_SRCRDY BIT(31) 101 102 /* Values of RCC_MPCKSELR register */ 103 #define RCC_MPCKSELR_HSI 0 104 #define RCC_MPCKSELR_HSE 1 105 #define RCC_MPCKSELR_PLL 2 106 #define RCC_MPCKSELR_PLL_MPUDIV 3 107 108 /* Values of RCC_ASSCKSELR register */ 109 #define RCC_ASSCKSELR_HSI 0 110 #define RCC_ASSCKSELR_HSE 1 111 #define RCC_ASSCKSELR_PLL 2 112 113 /* Values of RCC_MSSCKSELR register */ 114 #define RCC_MSSCKSELR_HSI 0 115 #define RCC_MSSCKSELR_HSE 1 116 #define RCC_MSSCKSELR_CSI 2 117 #define RCC_MSSCKSELR_PLL 3 118 119 /* Values of RCC_CPERCKSELR register */ 120 #define RCC_CPERCKSELR_HSI 0 121 #define RCC_CPERCKSELR_CSI 1 122 #define RCC_CPERCKSELR_HSE 2 123 124 /* used for most of DIVR register : max div for RTC */ 125 #define RCC_DIVR_DIV_MASK GENMASK(5, 0) 126 #define RCC_DIVR_DIVRDY BIT(31) 127 128 /* Masks for specific DIVR registers */ 129 #define RCC_APBXDIV_MASK GENMASK(2, 0) 130 #define RCC_MPUDIV_MASK GENMASK(2, 0) 131 #define RCC_AXIDIV_MASK GENMASK(2, 0) 132 #define RCC_MCUDIV_MASK GENMASK(3, 0) 133 134 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 135 #define RCC_MP_ENCLRR_OFFSET 4 136 137 /* Fields of RCC_BDCR register */ 138 #define RCC_BDCR_LSEON BIT(0) 139 #define RCC_BDCR_LSEBYP BIT(1) 140 #define RCC_BDCR_LSERDY BIT(2) 141 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) 142 #define RCC_BDCR_LSEDRV_SHIFT 4 143 #define RCC_BDCR_LSECSSON BIT(8) 144 #define RCC_BDCR_RTCCKEN BIT(20) 145 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) 146 #define RCC_BDCR_RTCSRC_SHIFT 16 147 148 /* Fields of RCC_RDLSICR register */ 149 #define RCC_RDLSICR_LSION BIT(0) 150 #define RCC_RDLSICR_LSIRDY BIT(1) 151 152 /* used for ALL PLLNCR registers */ 153 #define RCC_PLLNCR_PLLON BIT(0) 154 #define RCC_PLLNCR_PLLRDY BIT(1) 155 #define RCC_PLLNCR_DIVPEN BIT(4) 156 #define RCC_PLLNCR_DIVQEN BIT(5) 157 #define RCC_PLLNCR_DIVREN BIT(6) 158 #define RCC_PLLNCR_DIVEN_SHIFT 4 159 160 /* used for ALL PLLNCFGR1 registers */ 161 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 162 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) 163 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 164 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) 165 /* only for PLL3 and PLL4 */ 166 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 167 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) 168 169 /* used for ALL PLLNCFGR2 registers */ 170 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) 171 #define RCC_PLLNCFGR2_DIVP_SHIFT 0 172 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) 173 #define RCC_PLLNCFGR2_DIVQ_SHIFT 8 174 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) 175 #define RCC_PLLNCFGR2_DIVR_SHIFT 16 176 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) 177 178 /* used for ALL PLLNFRACR registers */ 179 #define RCC_PLLNFRACR_FRACV_SHIFT 3 180 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) 181 #define RCC_PLLNFRACR_FRACLE BIT(16) 182 183 /* used for ALL PLLNCSGR registers */ 184 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 185 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) 186 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 187 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) 188 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 189 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) 190 191 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */ 192 #define RCC_OCENR_HSION BIT(0) 193 #define RCC_OCENR_CSION BIT(4) 194 #define RCC_OCENR_HSEON BIT(8) 195 #define RCC_OCENR_HSEBYP BIT(10) 196 #define RCC_OCENR_HSECSSON BIT(11) 197 198 /* Fields of RCC_OCRDYR register */ 199 #define RCC_OCRDYR_HSIRDY BIT(0) 200 #define RCC_OCRDYR_HSIDIVRDY BIT(2) 201 #define RCC_OCRDYR_CSIRDY BIT(4) 202 #define RCC_OCRDYR_HSERDY BIT(8) 203 204 /* Fields of DDRITFCR register */ 205 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) 206 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 207 #define RCC_DDRITFCR_DDRCKMOD_SSR 0 208 209 /* Fields of RCC_HSICFGR register */ 210 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) 211 212 /* used for MCO related operations */ 213 #define RCC_MCOCFG_MCOON BIT(12) 214 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) 215 #define RCC_MCOCFG_MCODIV_SHIFT 4 216 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) 217 218 enum stm32mp1_parent_id { 219 /* 220 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved 221 * they are used as index in osc[] as entry point 222 */ 223 _HSI, 224 _HSE, 225 _CSI, 226 _LSI, 227 _LSE, 228 _I2S_CKIN, 229 _USB_PHY_48, 230 NB_OSC, 231 232 /* other parent source */ 233 _HSI_KER = NB_OSC, 234 _HSE_KER, 235 _HSE_KER_DIV2, 236 _CSI_KER, 237 _PLL1_P, 238 _PLL1_Q, 239 _PLL1_R, 240 _PLL2_P, 241 _PLL2_Q, 242 _PLL2_R, 243 _PLL3_P, 244 _PLL3_Q, 245 _PLL3_R, 246 _PLL4_P, 247 _PLL4_Q, 248 _PLL4_R, 249 _ACLK, 250 _PCLK1, 251 _PCLK2, 252 _PCLK3, 253 _PCLK4, 254 _PCLK5, 255 _HCLK6, 256 _HCLK2, 257 _CK_PER, 258 _CK_MPU, 259 _CK_MCU, 260 _PARENT_NB, 261 _UNKNOWN_ID = 0xff, 262 }; 263 264 enum stm32mp1_parent_sel { 265 _I2C12_SEL, 266 _I2C35_SEL, 267 _I2C46_SEL, 268 _UART6_SEL, 269 _UART24_SEL, 270 _UART35_SEL, 271 _UART78_SEL, 272 _SDMMC12_SEL, 273 _SDMMC3_SEL, 274 _ETH_SEL, 275 _QSPI_SEL, 276 _FMC_SEL, 277 _USBPHY_SEL, 278 _USBO_SEL, 279 _STGEN_SEL, 280 _PARENT_SEL_NB, 281 _UNKNOWN_SEL = 0xff, 282 }; 283 284 enum stm32mp1_pll_id { 285 _PLL1, 286 _PLL2, 287 _PLL3, 288 _PLL4, 289 _PLL_NB 290 }; 291 292 enum stm32mp1_div_id { 293 _DIV_P, 294 _DIV_Q, 295 _DIV_R, 296 _DIV_NB, 297 }; 298 299 enum stm32mp1_clksrc_id { 300 CLKSRC_MPU, 301 CLKSRC_AXI, 302 CLKSRC_MCU, 303 CLKSRC_PLL12, 304 CLKSRC_PLL3, 305 CLKSRC_PLL4, 306 CLKSRC_RTC, 307 CLKSRC_MCO1, 308 CLKSRC_MCO2, 309 CLKSRC_NB 310 }; 311 312 enum stm32mp1_clkdiv_id { 313 CLKDIV_MPU, 314 CLKDIV_AXI, 315 CLKDIV_MCU, 316 CLKDIV_APB1, 317 CLKDIV_APB2, 318 CLKDIV_APB3, 319 CLKDIV_APB4, 320 CLKDIV_APB5, 321 CLKDIV_RTC, 322 CLKDIV_MCO1, 323 CLKDIV_MCO2, 324 CLKDIV_NB 325 }; 326 327 enum stm32mp1_pllcfg { 328 PLLCFG_M, 329 PLLCFG_N, 330 PLLCFG_P, 331 PLLCFG_Q, 332 PLLCFG_R, 333 PLLCFG_O, 334 PLLCFG_NB 335 }; 336 337 enum stm32mp1_pllcsg { 338 PLLCSG_MOD_PER, 339 PLLCSG_INC_STEP, 340 PLLCSG_SSCG_MODE, 341 PLLCSG_NB 342 }; 343 344 enum stm32mp1_plltype { 345 PLL_800, 346 PLL_1600, 347 PLL_TYPE_NB 348 }; 349 350 struct stm32mp1_pll { 351 u8 refclk_min; 352 u8 refclk_max; 353 u8 divn_max; 354 }; 355 356 struct stm32mp1_clk_gate { 357 u16 offset; 358 u8 bit; 359 u8 index; 360 u8 set_clr; 361 u8 sel; 362 u8 fixed; 363 }; 364 365 struct stm32mp1_clk_sel { 366 u16 offset; 367 u8 src; 368 u8 msk; 369 u8 nb_parent; 370 const u8 *parent; 371 }; 372 373 #define REFCLK_SIZE 4 374 struct stm32mp1_clk_pll { 375 enum stm32mp1_plltype plltype; 376 u16 rckxselr; 377 u16 pllxcfgr1; 378 u16 pllxcfgr2; 379 u16 pllxfracr; 380 u16 pllxcr; 381 u16 pllxcsgr; 382 u8 refclk[REFCLK_SIZE]; 383 }; 384 385 struct stm32mp1_clk_data { 386 const struct stm32mp1_clk_gate *gate; 387 const struct stm32mp1_clk_sel *sel; 388 const struct stm32mp1_clk_pll *pll; 389 const int nb_gate; 390 }; 391 392 struct stm32mp1_clk_priv { 393 fdt_addr_t base; 394 const struct stm32mp1_clk_data *data; 395 ulong osc[NB_OSC]; 396 struct udevice *osc_dev[NB_OSC]; 397 }; 398 399 #define STM32MP1_CLK(off, b, idx, s) \ 400 { \ 401 .offset = (off), \ 402 .bit = (b), \ 403 .index = (idx), \ 404 .set_clr = 0, \ 405 .sel = (s), \ 406 .fixed = _UNKNOWN_ID, \ 407 } 408 409 #define STM32MP1_CLK_F(off, b, idx, f) \ 410 { \ 411 .offset = (off), \ 412 .bit = (b), \ 413 .index = (idx), \ 414 .set_clr = 0, \ 415 .sel = _UNKNOWN_SEL, \ 416 .fixed = (f), \ 417 } 418 419 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 420 { \ 421 .offset = (off), \ 422 .bit = (b), \ 423 .index = (idx), \ 424 .set_clr = 1, \ 425 .sel = (s), \ 426 .fixed = _UNKNOWN_ID, \ 427 } 428 429 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 430 { \ 431 .offset = (off), \ 432 .bit = (b), \ 433 .index = (idx), \ 434 .set_clr = 1, \ 435 .sel = _UNKNOWN_SEL, \ 436 .fixed = (f), \ 437 } 438 439 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 440 [(idx)] = { \ 441 .offset = (off), \ 442 .src = (s), \ 443 .msk = (m), \ 444 .parent = (p), \ 445 .nb_parent = ARRAY_SIZE((p)) \ 446 } 447 448 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ 449 p1, p2, p3, p4) \ 450 [(idx)] = { \ 451 .plltype = (type), \ 452 .rckxselr = (off1), \ 453 .pllxcfgr1 = (off2), \ 454 .pllxcfgr2 = (off3), \ 455 .pllxfracr = (off4), \ 456 .pllxcr = (off5), \ 457 .pllxcsgr = (off6), \ 458 .refclk[0] = (p1), \ 459 .refclk[1] = (p2), \ 460 .refclk[2] = (p3), \ 461 .refclk[3] = (p4), \ 462 } 463 464 static const u8 stm32mp1_clks[][2] = { 465 {CK_PER, _CK_PER}, 466 {CK_MPU, _CK_MPU}, 467 {CK_AXI, _ACLK}, 468 {CK_MCU, _CK_MCU}, 469 {CK_HSE, _HSE}, 470 {CK_CSI, _CSI}, 471 {CK_LSI, _LSI}, 472 {CK_LSE, _LSE}, 473 {CK_HSI, _HSI}, 474 {CK_HSE_DIV2, _HSE_KER_DIV2}, 475 }; 476 477 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 478 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 479 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 480 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 481 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 482 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 483 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 484 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 485 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 486 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 487 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 488 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 489 490 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 491 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 492 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 493 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 494 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 495 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 496 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 497 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 498 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 499 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 500 501 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 502 503 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 504 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 505 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 506 507 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 508 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 509 510 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 511 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 512 513 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 514 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 515 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 516 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 517 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 518 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 519 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 520 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 521 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 522 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 523 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 524 525 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 526 527 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL), 528 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), 529 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL), 530 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL), 531 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK), 532 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 533 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 534 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 536 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 537 538 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 539 }; 540 541 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 542 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 543 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 544 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 545 _HSE_KER}; 546 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 547 _HSE_KER}; 548 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 549 _HSE_KER}; 550 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 551 _HSE_KER}; 552 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 553 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 554 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; 555 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 556 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 557 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 558 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 559 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER}; 560 561 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 562 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), 563 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 564 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 565 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 566 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 567 uart24_parents), 568 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 569 uart35_parents), 570 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 571 uart78_parents), 572 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 573 sdmmc12_parents), 574 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 575 sdmmc3_parents), 576 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), 577 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 578 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 579 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 580 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 581 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 582 }; 583 584 #ifdef STM32MP1_CLOCK_TREE_INIT 585 /* define characteristic of PLL according type */ 586 #define DIVN_MIN 24 587 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 588 [PLL_800] = { 589 .refclk_min = 4, 590 .refclk_max = 16, 591 .divn_max = 99, 592 }, 593 [PLL_1600] = { 594 .refclk_min = 8, 595 .refclk_max = 16, 596 .divn_max = 199, 597 }, 598 }; 599 #endif /* STM32MP1_CLOCK_TREE_INIT */ 600 601 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 602 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 603 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 604 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 605 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 606 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 607 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 608 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 609 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 610 STM32MP1_CLK_PLL(_PLL3, PLL_800, 611 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 612 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 613 _HSI, _HSE, _CSI, _UNKNOWN_ID), 614 STM32MP1_CLK_PLL(_PLL4, PLL_800, 615 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 616 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 617 _HSI, _HSE, _CSI, _I2S_CKIN), 618 }; 619 620 /* Prescaler table lookups for clock computation */ 621 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 622 static const u8 stm32mp1_mcu_div[16] = { 623 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 624 }; 625 626 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/ 627 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 628 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 629 static const u8 stm32mp1_mpu_apbx_div[8] = { 630 0, 1, 2, 3, 4, 4, 4, 4 631 }; 632 633 /* div = /1 /2 /3 /4 */ 634 static const u8 stm32mp1_axi_div[8] = { 635 1, 2, 3, 4, 4, 4, 4, 4 636 }; 637 638 #ifdef DEBUG 639 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { 640 [_HSI] = "HSI", 641 [_HSE] = "HSE", 642 [_CSI] = "CSI", 643 [_LSI] = "LSI", 644 [_LSE] = "LSE", 645 [_I2S_CKIN] = "I2S_CKIN", 646 [_HSI_KER] = "HSI_KER", 647 [_HSE_KER] = "HSE_KER", 648 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 649 [_CSI_KER] = "CSI_KER", 650 [_PLL1_P] = "PLL1_P", 651 [_PLL1_Q] = "PLL1_Q", 652 [_PLL1_R] = "PLL1_R", 653 [_PLL2_P] = "PLL2_P", 654 [_PLL2_Q] = "PLL2_Q", 655 [_PLL2_R] = "PLL2_R", 656 [_PLL3_P] = "PLL3_P", 657 [_PLL3_Q] = "PLL3_Q", 658 [_PLL3_R] = "PLL3_R", 659 [_PLL4_P] = "PLL4_P", 660 [_PLL4_Q] = "PLL4_Q", 661 [_PLL4_R] = "PLL4_R", 662 [_ACLK] = "ACLK", 663 [_PCLK1] = "PCLK1", 664 [_PCLK2] = "PCLK2", 665 [_PCLK3] = "PCLK3", 666 [_PCLK4] = "PCLK4", 667 [_PCLK5] = "PCLK5", 668 [_HCLK6] = "KCLK6", 669 [_HCLK2] = "HCLK2", 670 [_CK_PER] = "CK_PER", 671 [_CK_MPU] = "CK_MPU", 672 [_CK_MCU] = "CK_MCU", 673 [_USB_PHY_48] = "USB_PHY_48" 674 }; 675 676 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { 677 [_I2C12_SEL] = "I2C12", 678 [_I2C35_SEL] = "I2C35", 679 [_I2C46_SEL] = "I2C46", 680 [_UART6_SEL] = "UART6", 681 [_UART24_SEL] = "UART24", 682 [_UART35_SEL] = "UART35", 683 [_UART78_SEL] = "UART78", 684 [_SDMMC12_SEL] = "SDMMC12", 685 [_SDMMC3_SEL] = "SDMMC3", 686 [_ETH_SEL] = "ETH", 687 [_QSPI_SEL] = "QSPI", 688 [_FMC_SEL] = "FMC", 689 [_USBPHY_SEL] = "USBPHY", 690 [_USBO_SEL] = "USBO", 691 [_STGEN_SEL] = "STGEN" 692 }; 693 #endif 694 695 static const struct stm32mp1_clk_data stm32mp1_data = { 696 .gate = stm32mp1_clk_gate, 697 .sel = stm32mp1_clk_sel, 698 .pll = stm32mp1_clk_pll, 699 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 700 }; 701 702 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) 703 { 704 if (idx >= NB_OSC) { 705 debug("%s: clk id %d not found\n", __func__, idx); 706 return 0; 707 } 708 709 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, 710 (u32)priv->osc[idx], priv->osc[idx] / 1000); 711 712 return priv->osc[idx]; 713 } 714 715 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 716 { 717 const struct stm32mp1_clk_gate *gate = priv->data->gate; 718 int i, nb_clks = priv->data->nb_gate; 719 720 for (i = 0; i < nb_clks; i++) { 721 if (gate[i].index == id) 722 break; 723 } 724 725 if (i == nb_clks) { 726 printf("%s: clk id %d not found\n", __func__, (u32)id); 727 return -EINVAL; 728 } 729 730 return i; 731 } 732 733 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, 734 int i) 735 { 736 const struct stm32mp1_clk_gate *gate = priv->data->gate; 737 738 if (gate[i].sel > _PARENT_SEL_NB) { 739 printf("%s: parents for clk id %d not found\n", 740 __func__, i); 741 return -EINVAL; 742 } 743 744 return gate[i].sel; 745 } 746 747 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, 748 int i) 749 { 750 const struct stm32mp1_clk_gate *gate = priv->data->gate; 751 752 if (gate[i].fixed == _UNKNOWN_ID) 753 return -ENOENT; 754 755 return gate[i].fixed; 756 } 757 758 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 759 unsigned long id) 760 { 761 const struct stm32mp1_clk_sel *sel = priv->data->sel; 762 int i; 763 int s, p; 764 765 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) 766 if (stm32mp1_clks[i][0] == id) 767 return stm32mp1_clks[i][1]; 768 769 i = stm32mp1_clk_get_id(priv, id); 770 if (i < 0) 771 return i; 772 773 p = stm32mp1_clk_get_fixed_parent(priv, i); 774 if (p >= 0 && p < _PARENT_NB) 775 return p; 776 777 s = stm32mp1_clk_get_sel(priv, i); 778 if (s < 0) 779 return s; 780 781 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; 782 783 if (p < sel[s].nb_parent) { 784 #ifdef DEBUG 785 debug("%s: %s clock is the parent %s of clk id %d\n", __func__, 786 stm32mp1_clk_parent_name[sel[s].parent[p]], 787 stm32mp1_clk_parent_sel_name[s], 788 (u32)id); 789 #endif 790 return sel[s].parent[p]; 791 } 792 793 pr_err("%s: no parents defined for clk id %d\n", 794 __func__, (u32)id); 795 796 return -EINVAL; 797 } 798 799 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 800 int pll_id, int div_id) 801 { 802 const struct stm32mp1_clk_pll *pll = priv->data->pll; 803 int divm, divn, divy, src; 804 ulong refclk, dfout; 805 u32 selr, cfgr1, cfgr2, fracr; 806 const u8 shift[_DIV_NB] = { 807 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 808 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 809 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT }; 810 811 debug("%s(%d, %d)\n", __func__, pll_id, div_id); 812 if (div_id > _DIV_NB) 813 return 0; 814 815 selr = readl(priv->base + pll[pll_id].rckxselr); 816 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); 817 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); 818 fracr = readl(priv->base + pll[pll_id].pllxfracr); 819 820 debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n", 821 pll_id, selr, cfgr1, cfgr2, fracr); 822 823 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 824 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 825 divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 826 827 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy); 828 829 src = selr & RCC_SELR_SRC_MASK; 830 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 831 832 debug(" refclk = %d kHz\n", (u32)(refclk / 1000)); 833 834 /* 835 * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2 836 * So same final result than PLL2 et 4 837 * with FRACV : 838 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13) 839 * / (DIVM + 1) * (DIVy + 1) 840 * without FRACV 841 * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1) 842 */ 843 if (fracr & RCC_PLLNFRACR_FRACLE) { 844 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 845 >> RCC_PLLNFRACR_FRACV_SHIFT; 846 dfout = (ulong)lldiv((unsigned long long)refclk * 847 (((divn + 1) << 13) + fracv), 848 ((unsigned long long)(divm + 1) * 849 (divy + 1)) << 13); 850 } else { 851 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1)); 852 } 853 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); 854 855 return dfout; 856 } 857 858 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 859 { 860 u32 reg; 861 ulong clock = 0; 862 863 switch (p) { 864 case _CK_MPU: 865 /* MPU sub system */ 866 reg = readl(priv->base + RCC_MPCKSELR); 867 switch (reg & RCC_SELR_SRC_MASK) { 868 case RCC_MPCKSELR_HSI: 869 clock = stm32mp1_clk_get_fixed(priv, _HSI); 870 break; 871 case RCC_MPCKSELR_HSE: 872 clock = stm32mp1_clk_get_fixed(priv, _HSE); 873 break; 874 case RCC_MPCKSELR_PLL: 875 case RCC_MPCKSELR_PLL_MPUDIV: 876 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 877 if (p == RCC_MPCKSELR_PLL_MPUDIV) { 878 reg = readl(priv->base + RCC_MPCKDIVR); 879 clock /= stm32mp1_mpu_div[reg & 880 RCC_MPUDIV_MASK]; 881 } 882 break; 883 } 884 break; 885 /* AXI sub system */ 886 case _ACLK: 887 case _HCLK2: 888 case _HCLK6: 889 case _PCLK4: 890 case _PCLK5: 891 reg = readl(priv->base + RCC_ASSCKSELR); 892 switch (reg & RCC_SELR_SRC_MASK) { 893 case RCC_ASSCKSELR_HSI: 894 clock = stm32mp1_clk_get_fixed(priv, _HSI); 895 break; 896 case RCC_ASSCKSELR_HSE: 897 clock = stm32mp1_clk_get_fixed(priv, _HSE); 898 break; 899 case RCC_ASSCKSELR_PLL: 900 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 901 break; 902 } 903 904 /* System clock divider */ 905 reg = readl(priv->base + RCC_AXIDIVR); 906 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 907 908 switch (p) { 909 case _PCLK4: 910 reg = readl(priv->base + RCC_APB4DIVR); 911 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 912 break; 913 case _PCLK5: 914 reg = readl(priv->base + RCC_APB5DIVR); 915 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 916 break; 917 default: 918 break; 919 } 920 break; 921 /* MCU sub system */ 922 case _CK_MCU: 923 case _PCLK1: 924 case _PCLK2: 925 case _PCLK3: 926 reg = readl(priv->base + RCC_MSSCKSELR); 927 switch (reg & RCC_SELR_SRC_MASK) { 928 case RCC_MSSCKSELR_HSI: 929 clock = stm32mp1_clk_get_fixed(priv, _HSI); 930 break; 931 case RCC_MSSCKSELR_HSE: 932 clock = stm32mp1_clk_get_fixed(priv, _HSE); 933 break; 934 case RCC_MSSCKSELR_CSI: 935 clock = stm32mp1_clk_get_fixed(priv, _CSI); 936 break; 937 case RCC_MSSCKSELR_PLL: 938 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 939 break; 940 } 941 942 /* MCU clock divider */ 943 reg = readl(priv->base + RCC_MCUDIVR); 944 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 945 946 switch (p) { 947 case _PCLK1: 948 reg = readl(priv->base + RCC_APB1DIVR); 949 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 950 break; 951 case _PCLK2: 952 reg = readl(priv->base + RCC_APB2DIVR); 953 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 954 break; 955 case _PCLK3: 956 reg = readl(priv->base + RCC_APB3DIVR); 957 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 958 break; 959 case _CK_MCU: 960 default: 961 break; 962 } 963 break; 964 case _CK_PER: 965 reg = readl(priv->base + RCC_CPERCKSELR); 966 switch (reg & RCC_SELR_SRC_MASK) { 967 case RCC_CPERCKSELR_HSI: 968 clock = stm32mp1_clk_get_fixed(priv, _HSI); 969 break; 970 case RCC_CPERCKSELR_HSE: 971 clock = stm32mp1_clk_get_fixed(priv, _HSE); 972 break; 973 case RCC_CPERCKSELR_CSI: 974 clock = stm32mp1_clk_get_fixed(priv, _CSI); 975 break; 976 } 977 break; 978 case _HSI: 979 case _HSI_KER: 980 clock = stm32mp1_clk_get_fixed(priv, _HSI); 981 break; 982 case _CSI: 983 case _CSI_KER: 984 clock = stm32mp1_clk_get_fixed(priv, _CSI); 985 break; 986 case _HSE: 987 case _HSE_KER: 988 case _HSE_KER_DIV2: 989 clock = stm32mp1_clk_get_fixed(priv, _HSE); 990 if (p == _HSE_KER_DIV2) 991 clock >>= 1; 992 break; 993 case _LSI: 994 clock = stm32mp1_clk_get_fixed(priv, _LSI); 995 break; 996 case _LSE: 997 clock = stm32mp1_clk_get_fixed(priv, _LSE); 998 break; 999 /* PLL */ 1000 case _PLL1_P: 1001 case _PLL1_Q: 1002 case _PLL1_R: 1003 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); 1004 break; 1005 case _PLL2_P: 1006 case _PLL2_Q: 1007 case _PLL2_R: 1008 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); 1009 break; 1010 case _PLL3_P: 1011 case _PLL3_Q: 1012 case _PLL3_R: 1013 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); 1014 break; 1015 case _PLL4_P: 1016 case _PLL4_Q: 1017 case _PLL4_R: 1018 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); 1019 break; 1020 /* other */ 1021 case _USB_PHY_48: 1022 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); 1023 break; 1024 1025 default: 1026 break; 1027 } 1028 1029 debug("%s(%d) clock = %lx : %ld kHz\n", 1030 __func__, p, clock, clock / 1000); 1031 1032 return clock; 1033 } 1034 1035 static int stm32mp1_clk_enable(struct clk *clk) 1036 { 1037 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1038 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1039 int i = stm32mp1_clk_get_id(priv, clk->id); 1040 1041 if (i < 0) 1042 return i; 1043 1044 if (gate[i].set_clr) 1045 writel(BIT(gate[i].bit), priv->base + gate[i].offset); 1046 else 1047 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1048 1049 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); 1050 1051 return 0; 1052 } 1053 1054 static int stm32mp1_clk_disable(struct clk *clk) 1055 { 1056 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1057 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1058 int i = stm32mp1_clk_get_id(priv, clk->id); 1059 1060 if (i < 0) 1061 return i; 1062 1063 if (gate[i].set_clr) 1064 writel(BIT(gate[i].bit), 1065 priv->base + gate[i].offset 1066 + RCC_MP_ENCLRR_OFFSET); 1067 else 1068 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1069 1070 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); 1071 1072 return 0; 1073 } 1074 1075 static ulong stm32mp1_clk_get_rate(struct clk *clk) 1076 { 1077 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1078 int p = stm32mp1_clk_get_parent(priv, clk->id); 1079 ulong rate; 1080 1081 if (p < 0) 1082 return 0; 1083 1084 rate = stm32mp1_clk_get(priv, p); 1085 1086 #ifdef DEBUG 1087 debug("%s: computed rate for id clock %d is %d (parent is %s)\n", 1088 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); 1089 #endif 1090 return rate; 1091 } 1092 1093 #ifdef STM32MP1_CLOCK_TREE_INIT 1094 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, 1095 u32 mask_on) 1096 { 1097 u32 address = rcc + offset; 1098 1099 if (enable) 1100 setbits_le32(address, mask_on); 1101 else 1102 clrbits_le32(address, mask_on); 1103 } 1104 1105 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) 1106 { 1107 if (enable) 1108 setbits_le32(rcc + RCC_OCENSETR, mask_on); 1109 else 1110 setbits_le32(rcc + RCC_OCENCLRR, mask_on); 1111 } 1112 1113 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, 1114 u32 mask_rdy) 1115 { 1116 u32 mask_test = 0; 1117 u32 address = rcc + offset; 1118 u32 val; 1119 int ret; 1120 1121 if (enable) 1122 mask_test = mask_rdy; 1123 1124 ret = readl_poll_timeout(address, val, 1125 (val & mask_rdy) == mask_test, 1126 TIMEOUT_1S); 1127 1128 if (ret) 1129 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", 1130 mask_rdy, address, enable, readl(address)); 1131 1132 return ret; 1133 } 1134 1135 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv) 1136 { 1137 u32 value; 1138 1139 if (bypass) 1140 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 1141 1142 /* 1143 * warning: not recommended to switch directly from "high drive" 1144 * to "medium low drive", and vice-versa. 1145 */ 1146 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) 1147 >> RCC_BDCR_LSEDRV_SHIFT; 1148 1149 while (value != lsedrv) { 1150 if (value > lsedrv) 1151 value--; 1152 else 1153 value++; 1154 1155 clrsetbits_le32(rcc + RCC_BDCR, 1156 RCC_BDCR_LSEDRV_MASK, 1157 value << RCC_BDCR_LSEDRV_SHIFT); 1158 } 1159 1160 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 1161 } 1162 1163 static void stm32mp1_lse_wait(fdt_addr_t rcc) 1164 { 1165 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); 1166 } 1167 1168 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) 1169 { 1170 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 1171 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY); 1172 } 1173 1174 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css) 1175 { 1176 if (bypass) 1177 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1178 1179 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 1180 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); 1181 1182 if (css) 1183 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1184 } 1185 1186 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) 1187 { 1188 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); 1189 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); 1190 } 1191 1192 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable) 1193 { 1194 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 1195 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY); 1196 } 1197 1198 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) 1199 { 1200 u32 address = rcc + RCC_OCRDYR; 1201 u32 val; 1202 int ret; 1203 1204 clrsetbits_le32(rcc + RCC_HSICFGR, 1205 RCC_HSICFGR_HSIDIV_MASK, 1206 RCC_HSICFGR_HSIDIV_MASK & hsidiv); 1207 1208 ret = readl_poll_timeout(address, val, 1209 val & RCC_OCRDYR_HSIDIVRDY, 1210 TIMEOUT_200MS); 1211 if (ret) 1212 pr_err("HSIDIV failed @ 0x%x: 0x%x\n", 1213 address, readl(address)); 1214 1215 return ret; 1216 } 1217 1218 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) 1219 { 1220 u8 hsidiv; 1221 u32 hsidivfreq = MAX_HSI_HZ; 1222 1223 for (hsidiv = 0; hsidiv < 4; hsidiv++, 1224 hsidivfreq = hsidivfreq / 2) 1225 if (hsidivfreq == hsifreq) 1226 break; 1227 1228 if (hsidiv == 4) { 1229 pr_err("clk-hsi frequency invalid"); 1230 return -1; 1231 } 1232 1233 if (hsidiv > 0) 1234 return stm32mp1_set_hsidiv(rcc, hsidiv); 1235 1236 return 0; 1237 } 1238 1239 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) 1240 { 1241 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1242 1243 writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); 1244 } 1245 1246 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) 1247 { 1248 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1249 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1250 u32 val; 1251 int ret; 1252 1253 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY, 1254 TIMEOUT_200MS); 1255 1256 if (ret) { 1257 pr_err("PLL%d start failed @ 0x%x: 0x%x\n", 1258 pll_id, pllxcr, readl(pllxcr)); 1259 return ret; 1260 } 1261 1262 /* start the requested output */ 1263 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1264 1265 return 0; 1266 } 1267 1268 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id) 1269 { 1270 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1271 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1272 u32 val; 1273 1274 /* stop all output */ 1275 clrbits_le32(pllxcr, 1276 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1277 1278 /* stop PLL */ 1279 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON); 1280 1281 /* wait PLL stopped */ 1282 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0, 1283 TIMEOUT_200MS); 1284 } 1285 1286 static void pll_config_output(struct stm32mp1_clk_priv *priv, 1287 int pll_id, u32 *pllcfg) 1288 { 1289 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1290 fdt_addr_t rcc = priv->base; 1291 u32 value; 1292 1293 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) 1294 & RCC_PLLNCFGR2_DIVP_MASK; 1295 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) 1296 & RCC_PLLNCFGR2_DIVQ_MASK; 1297 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) 1298 & RCC_PLLNCFGR2_DIVR_MASK; 1299 writel(value, rcc + pll[pll_id].pllxcfgr2); 1300 } 1301 1302 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, 1303 u32 *pllcfg, u32 fracv) 1304 { 1305 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1306 fdt_addr_t rcc = priv->base; 1307 enum stm32mp1_plltype type = pll[pll_id].plltype; 1308 int src; 1309 ulong refclk; 1310 u8 ifrge = 0; 1311 u32 value; 1312 1313 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; 1314 1315 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1316 (pllcfg[PLLCFG_M] + 1); 1317 1318 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || 1319 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { 1320 debug("invalid refclk = %x\n", (u32)refclk); 1321 return -EINVAL; 1322 } 1323 if (type == PLL_800 && refclk >= 8000000) 1324 ifrge = 1; 1325 1326 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) 1327 & RCC_PLLNCFGR1_DIVN_MASK; 1328 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) 1329 & RCC_PLLNCFGR1_DIVM_MASK; 1330 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) 1331 & RCC_PLLNCFGR1_IFRGE_MASK; 1332 writel(value, rcc + pll[pll_id].pllxcfgr1); 1333 1334 /* fractional configuration: load sigma-delta modulator (SDM) */ 1335 1336 /* Write into FRACV the new fractional value , and FRACLE to 0 */ 1337 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT, 1338 rcc + pll[pll_id].pllxfracr); 1339 1340 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */ 1341 setbits_le32(rcc + pll[pll_id].pllxfracr, 1342 RCC_PLLNFRACR_FRACLE); 1343 1344 pll_config_output(priv, pll_id, pllcfg); 1345 1346 return 0; 1347 } 1348 1349 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) 1350 { 1351 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1352 u32 pllxcsg; 1353 1354 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1355 RCC_PLLNCSGR_MOD_PER_MASK) | 1356 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1357 RCC_PLLNCSGR_INC_STEP_MASK) | 1358 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1359 RCC_PLLNCSGR_SSCG_MODE_MASK); 1360 1361 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); 1362 } 1363 1364 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) 1365 { 1366 u32 address = priv->base + (clksrc >> 4); 1367 u32 val; 1368 int ret; 1369 1370 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); 1371 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, 1372 TIMEOUT_200MS); 1373 if (ret) 1374 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1375 clksrc, address, readl(address)); 1376 1377 return ret; 1378 } 1379 1380 static int set_clkdiv(unsigned int clkdiv, u32 address) 1381 { 1382 u32 val; 1383 int ret; 1384 1385 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); 1386 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, 1387 TIMEOUT_200MS); 1388 if (ret) 1389 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1390 clkdiv, address, readl(address)); 1391 1392 return ret; 1393 } 1394 1395 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1396 u32 clksrc, u32 clkdiv) 1397 { 1398 u32 address = priv->base + (clksrc >> 4); 1399 1400 /* 1401 * binding clksrc : bit15-4 offset 1402 * bit3: disable 1403 * bit2-0: MCOSEL[2:0] 1404 */ 1405 if (clksrc & 0x8) { 1406 clrbits_le32(address, RCC_MCOCFG_MCOON); 1407 } else { 1408 clrsetbits_le32(address, 1409 RCC_MCOCFG_MCOSRC_MASK, 1410 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1411 clrsetbits_le32(address, 1412 RCC_MCOCFG_MCODIV_MASK, 1413 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1414 setbits_le32(address, RCC_MCOCFG_MCOON); 1415 } 1416 } 1417 1418 static void set_rtcsrc(struct stm32mp1_clk_priv *priv, 1419 unsigned int clksrc, 1420 int lse_css) 1421 { 1422 u32 address = priv->base + RCC_BDCR; 1423 1424 if (readl(address) & RCC_BDCR_RTCCKEN) 1425 goto skip_rtc; 1426 1427 if (clksrc == CLK_RTC_DISABLED) 1428 goto skip_rtc; 1429 1430 clrsetbits_le32(address, 1431 RCC_BDCR_RTCSRC_MASK, 1432 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1433 1434 setbits_le32(address, RCC_BDCR_RTCCKEN); 1435 1436 skip_rtc: 1437 if (lse_css) 1438 setbits_le32(address, RCC_BDCR_LSECSSON); 1439 } 1440 1441 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs) 1442 { 1443 u32 address = priv->base + ((pkcs >> 4) & 0xFFF); 1444 u32 value = pkcs & 0xF; 1445 u32 mask = 0xF; 1446 1447 if (pkcs & BIT(31)) { 1448 mask <<= 4; 1449 value <<= 4; 1450 } 1451 clrsetbits_le32(address, mask, value); 1452 } 1453 1454 static int stm32mp1_clktree(struct udevice *dev) 1455 { 1456 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1457 fdt_addr_t rcc = priv->base; 1458 unsigned int clksrc[CLKSRC_NB]; 1459 unsigned int clkdiv[CLKDIV_NB]; 1460 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1461 ofnode plloff[_PLL_NB]; 1462 int ret; 1463 int i, len; 1464 int lse_css = 0; 1465 const u32 *pkcs_cell; 1466 1467 /* check mandatory field */ 1468 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); 1469 if (ret < 0) { 1470 debug("field st,clksrc invalid: error %d\n", ret); 1471 return -FDT_ERR_NOTFOUND; 1472 } 1473 1474 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); 1475 if (ret < 0) { 1476 debug("field st,clkdiv invalid: error %d\n", ret); 1477 return -FDT_ERR_NOTFOUND; 1478 } 1479 1480 /* check mandatory field in each pll */ 1481 for (i = 0; i < _PLL_NB; i++) { 1482 char name[12]; 1483 1484 sprintf(name, "st,pll@%d", i); 1485 plloff[i] = dev_read_subnode(dev, name); 1486 if (!ofnode_valid(plloff[i])) 1487 continue; 1488 ret = ofnode_read_u32_array(plloff[i], "cfg", 1489 pllcfg[i], PLLCFG_NB); 1490 if (ret < 0) { 1491 debug("field cfg invalid: error %d\n", ret); 1492 return -FDT_ERR_NOTFOUND; 1493 } 1494 } 1495 1496 debug("configuration MCO\n"); 1497 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1498 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1499 1500 debug("switch ON osillator\n"); 1501 /* 1502 * switch ON oscillator found in device-tree, 1503 * HSI already ON after bootrom 1504 */ 1505 if (priv->osc[_LSI]) 1506 stm32mp1_lsi_set(rcc, 1); 1507 1508 if (priv->osc[_LSE]) { 1509 int bypass; 1510 int lsedrv; 1511 struct udevice *dev = priv->osc_dev[_LSE]; 1512 1513 bypass = dev_read_bool(dev, "st,bypass"); 1514 lse_css = dev_read_bool(dev, "st,css"); 1515 lsedrv = dev_read_u32_default(dev, "st,drive", 1516 LSEDRV_MEDIUM_HIGH); 1517 1518 stm32mp1_lse_enable(rcc, bypass, lsedrv); 1519 } 1520 1521 if (priv->osc[_HSE]) { 1522 int bypass, css; 1523 struct udevice *dev = priv->osc_dev[_HSE]; 1524 1525 bypass = dev_read_bool(dev, "st,bypass"); 1526 css = dev_read_bool(dev, "st,css"); 1527 1528 stm32mp1_hse_enable(rcc, bypass, css); 1529 } 1530 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1531 * => switch on CSI even if node is not present in device tree 1532 */ 1533 stm32mp1_csi_set(rcc, 1); 1534 1535 /* come back to HSI */ 1536 debug("come back to HSI\n"); 1537 set_clksrc(priv, CLK_MPU_HSI); 1538 set_clksrc(priv, CLK_AXI_HSI); 1539 set_clksrc(priv, CLK_MCU_HSI); 1540 1541 debug("pll stop\n"); 1542 for (i = 0; i < _PLL_NB; i++) 1543 pll_stop(priv, i); 1544 1545 /* configure HSIDIV */ 1546 debug("configure HSIDIV\n"); 1547 if (priv->osc[_HSI]) 1548 stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1549 1550 /* select DIV */ 1551 debug("select DIV\n"); 1552 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1553 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR); 1554 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1555 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1556 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1557 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR); 1558 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1559 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1560 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1561 1562 /* no ready bit for RTC */ 1563 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); 1564 1565 /* configure PLLs source */ 1566 debug("configure PLLs source\n"); 1567 set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1568 set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1569 set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1570 1571 /* configure and start PLLs */ 1572 debug("configure PLLs\n"); 1573 for (i = 0; i < _PLL_NB; i++) { 1574 u32 fracv; 1575 u32 csg[PLLCSG_NB]; 1576 1577 debug("configure PLL %d @ %d\n", i, 1578 ofnode_to_offset(plloff[i])); 1579 if (!ofnode_valid(plloff[i])) 1580 continue; 1581 1582 fracv = ofnode_read_u32_default(plloff[i], "frac", 0); 1583 pll_config(priv, i, pllcfg[i], fracv); 1584 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); 1585 if (!ret) { 1586 pll_csg(priv, i, csg); 1587 } else if (ret != -FDT_ERR_NOTFOUND) { 1588 debug("invalid csg node for pll@%d res=%d\n", i, ret); 1589 return ret; 1590 } 1591 pll_start(priv, i); 1592 } 1593 1594 /* wait and start PLLs ouptut when ready */ 1595 for (i = 0; i < _PLL_NB; i++) { 1596 if (!ofnode_valid(plloff[i])) 1597 continue; 1598 debug("output PLL %d\n", i); 1599 pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1600 } 1601 1602 /* wait LSE ready before to use it */ 1603 if (priv->osc[_LSE]) 1604 stm32mp1_lse_wait(rcc); 1605 1606 /* configure with expected clock source */ 1607 debug("CLKSRC\n"); 1608 set_clksrc(priv, clksrc[CLKSRC_MPU]); 1609 set_clksrc(priv, clksrc[CLKSRC_AXI]); 1610 set_clksrc(priv, clksrc[CLKSRC_MCU]); 1611 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1612 1613 /* configure PKCK */ 1614 debug("PKCK\n"); 1615 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); 1616 if (pkcs_cell) { 1617 bool ckper_disabled = false; 1618 1619 for (i = 0; i < len / sizeof(u32); i++) { 1620 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]); 1621 1622 if (pkcs == CLK_CKPER_DISABLED) { 1623 ckper_disabled = true; 1624 continue; 1625 } 1626 pkcs_config(priv, pkcs); 1627 } 1628 /* CKPER is source for some peripheral clock 1629 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1630 * only if previous clock is still ON 1631 * => deactivated CKPER only after switching clock 1632 */ 1633 if (ckper_disabled) 1634 pkcs_config(priv, CLK_CKPER_DISABLED); 1635 } 1636 1637 debug("oscillator off\n"); 1638 /* switch OFF HSI if not found in device-tree */ 1639 if (!priv->osc[_HSI]) 1640 stm32mp1_hsi_set(rcc, 0); 1641 1642 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1643 clrsetbits_le32(priv->base + RCC_DDRITFCR, 1644 RCC_DDRITFCR_DDRCKMOD_MASK, 1645 RCC_DDRITFCR_DDRCKMOD_SSR << 1646 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1647 1648 return 0; 1649 } 1650 #endif /* STM32MP1_CLOCK_TREE_INIT */ 1651 1652 static void stm32mp1_osc_clk_init(const char *name, 1653 struct stm32mp1_clk_priv *priv, 1654 int index) 1655 { 1656 struct clk clk; 1657 struct udevice *dev = NULL; 1658 1659 priv->osc[index] = 0; 1660 clk.id = 0; 1661 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { 1662 if (clk_request(dev, &clk)) 1663 pr_err("%s request", name); 1664 else 1665 priv->osc[index] = clk_get_rate(&clk); 1666 } 1667 priv->osc_dev[index] = dev; 1668 } 1669 1670 static void stm32mp1_osc_init(struct udevice *dev) 1671 { 1672 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1673 int i; 1674 const char *name[NB_OSC] = { 1675 [_LSI] = "clk-lsi", 1676 [_LSE] = "clk-lse", 1677 [_HSI] = "clk-hsi", 1678 [_HSE] = "clk-hse", 1679 [_CSI] = "clk-csi", 1680 [_I2S_CKIN] = "i2s_ckin", 1681 [_USB_PHY_48] = "ck_usbo_48m"}; 1682 1683 for (i = 0; i < NB_OSC; i++) { 1684 stm32mp1_osc_clk_init(name[i], priv, i); 1685 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); 1686 } 1687 } 1688 1689 static int stm32mp1_clk_probe(struct udevice *dev) 1690 { 1691 int result = 0; 1692 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1693 1694 priv->base = dev_read_addr(dev->parent); 1695 if (priv->base == FDT_ADDR_T_NONE) 1696 return -EINVAL; 1697 1698 priv->data = (void *)&stm32mp1_data; 1699 1700 if (!priv->data->gate || !priv->data->sel || 1701 !priv->data->pll) 1702 return -EINVAL; 1703 1704 stm32mp1_osc_init(dev); 1705 1706 #ifdef STM32MP1_CLOCK_TREE_INIT 1707 /* clock tree init is done only one time, before relocation */ 1708 if (!(gd->flags & GD_FLG_RELOC)) 1709 result = stm32mp1_clktree(dev); 1710 #endif 1711 1712 return result; 1713 } 1714 1715 static const struct clk_ops stm32mp1_clk_ops = { 1716 .enable = stm32mp1_clk_enable, 1717 .disable = stm32mp1_clk_disable, 1718 .get_rate = stm32mp1_clk_get_rate, 1719 }; 1720 1721 static const struct udevice_id stm32mp1_clk_ids[] = { 1722 { .compatible = "st,stm32mp1-rcc-clk" }, 1723 { } 1724 }; 1725 1726 U_BOOT_DRIVER(stm32mp1_clock) = { 1727 .name = "stm32mp1_clk", 1728 .id = UCLASS_CLK, 1729 .of_match = stm32mp1_clk_ids, 1730 .ops = &stm32mp1_clk_ops, 1731 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv), 1732 .probe = stm32mp1_clk_probe, 1733 }; 1734