1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <div64.h> 9 #include <dm.h> 10 #include <regmap.h> 11 #include <spl.h> 12 #include <syscon.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <dt-bindings/clock/stm32mp1-clks.h> 16 #include <dt-bindings/clock/stm32mp1-clksrc.h> 17 18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 19 /* activate clock tree initialization in the driver */ 20 #define STM32MP1_CLOCK_TREE_INIT 21 #endif 22 23 #define MAX_HSI_HZ 64000000 24 25 /* TIMEOUT */ 26 #define TIMEOUT_200MS 200000 27 #define TIMEOUT_1S 1000000 28 29 /* STGEN registers */ 30 #define STGENC_CNTCR 0x00 31 #define STGENC_CNTSR 0x04 32 #define STGENC_CNTCVL 0x08 33 #define STGENC_CNTCVU 0x0C 34 #define STGENC_CNTFID0 0x20 35 36 #define STGENC_CNTCR_EN BIT(0) 37 38 /* RCC registers */ 39 #define RCC_OCENSETR 0x0C 40 #define RCC_OCENCLRR 0x10 41 #define RCC_HSICFGR 0x18 42 #define RCC_MPCKSELR 0x20 43 #define RCC_ASSCKSELR 0x24 44 #define RCC_RCK12SELR 0x28 45 #define RCC_MPCKDIVR 0x2C 46 #define RCC_AXIDIVR 0x30 47 #define RCC_APB4DIVR 0x3C 48 #define RCC_APB5DIVR 0x40 49 #define RCC_RTCDIVR 0x44 50 #define RCC_MSSCKSELR 0x48 51 #define RCC_PLL1CR 0x80 52 #define RCC_PLL1CFGR1 0x84 53 #define RCC_PLL1CFGR2 0x88 54 #define RCC_PLL1FRACR 0x8C 55 #define RCC_PLL1CSGR 0x90 56 #define RCC_PLL2CR 0x94 57 #define RCC_PLL2CFGR1 0x98 58 #define RCC_PLL2CFGR2 0x9C 59 #define RCC_PLL2FRACR 0xA0 60 #define RCC_PLL2CSGR 0xA4 61 #define RCC_I2C46CKSELR 0xC0 62 #define RCC_CPERCKSELR 0xD0 63 #define RCC_STGENCKSELR 0xD4 64 #define RCC_DDRITFCR 0xD8 65 #define RCC_BDCR 0x140 66 #define RCC_RDLSICR 0x144 67 #define RCC_MP_APB4ENSETR 0x200 68 #define RCC_MP_APB5ENSETR 0x208 69 #define RCC_MP_AHB5ENSETR 0x210 70 #define RCC_MP_AHB6ENSETR 0x218 71 #define RCC_OCRDYR 0x808 72 #define RCC_DBGCFGR 0x80C 73 #define RCC_RCK3SELR 0x820 74 #define RCC_RCK4SELR 0x824 75 #define RCC_MCUDIVR 0x830 76 #define RCC_APB1DIVR 0x834 77 #define RCC_APB2DIVR 0x838 78 #define RCC_APB3DIVR 0x83C 79 #define RCC_PLL3CR 0x880 80 #define RCC_PLL3CFGR1 0x884 81 #define RCC_PLL3CFGR2 0x888 82 #define RCC_PLL3FRACR 0x88C 83 #define RCC_PLL3CSGR 0x890 84 #define RCC_PLL4CR 0x894 85 #define RCC_PLL4CFGR1 0x898 86 #define RCC_PLL4CFGR2 0x89C 87 #define RCC_PLL4FRACR 0x8A0 88 #define RCC_PLL4CSGR 0x8A4 89 #define RCC_I2C12CKSELR 0x8C0 90 #define RCC_I2C35CKSELR 0x8C4 91 #define RCC_UART6CKSELR 0x8E4 92 #define RCC_UART24CKSELR 0x8E8 93 #define RCC_UART35CKSELR 0x8EC 94 #define RCC_UART78CKSELR 0x8F0 95 #define RCC_SDMMC12CKSELR 0x8F4 96 #define RCC_SDMMC3CKSELR 0x8F8 97 #define RCC_ETHCKSELR 0x8FC 98 #define RCC_QSPICKSELR 0x900 99 #define RCC_FMCCKSELR 0x904 100 #define RCC_USBCKSELR 0x91C 101 #define RCC_DSICKSELR 0x924 102 #define RCC_ADCCKSELR 0x928 103 #define RCC_MP_APB1ENSETR 0xA00 104 #define RCC_MP_APB2ENSETR 0XA08 105 #define RCC_MP_APB3ENSETR 0xA10 106 #define RCC_MP_AHB2ENSETR 0xA18 107 #define RCC_MP_AHB4ENSETR 0xA28 108 109 /* used for most of SELR register */ 110 #define RCC_SELR_SRC_MASK GENMASK(2, 0) 111 #define RCC_SELR_SRCRDY BIT(31) 112 113 /* Values of RCC_MPCKSELR register */ 114 #define RCC_MPCKSELR_HSI 0 115 #define RCC_MPCKSELR_HSE 1 116 #define RCC_MPCKSELR_PLL 2 117 #define RCC_MPCKSELR_PLL_MPUDIV 3 118 119 /* Values of RCC_ASSCKSELR register */ 120 #define RCC_ASSCKSELR_HSI 0 121 #define RCC_ASSCKSELR_HSE 1 122 #define RCC_ASSCKSELR_PLL 2 123 124 /* Values of RCC_MSSCKSELR register */ 125 #define RCC_MSSCKSELR_HSI 0 126 #define RCC_MSSCKSELR_HSE 1 127 #define RCC_MSSCKSELR_CSI 2 128 #define RCC_MSSCKSELR_PLL 3 129 130 /* Values of RCC_CPERCKSELR register */ 131 #define RCC_CPERCKSELR_HSI 0 132 #define RCC_CPERCKSELR_CSI 1 133 #define RCC_CPERCKSELR_HSE 2 134 135 /* used for most of DIVR register : max div for RTC */ 136 #define RCC_DIVR_DIV_MASK GENMASK(5, 0) 137 #define RCC_DIVR_DIVRDY BIT(31) 138 139 /* Masks for specific DIVR registers */ 140 #define RCC_APBXDIV_MASK GENMASK(2, 0) 141 #define RCC_MPUDIV_MASK GENMASK(2, 0) 142 #define RCC_AXIDIV_MASK GENMASK(2, 0) 143 #define RCC_MCUDIV_MASK GENMASK(3, 0) 144 145 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 146 #define RCC_MP_ENCLRR_OFFSET 4 147 148 /* Fields of RCC_BDCR register */ 149 #define RCC_BDCR_LSEON BIT(0) 150 #define RCC_BDCR_LSEBYP BIT(1) 151 #define RCC_BDCR_LSERDY BIT(2) 152 #define RCC_BDCR_DIGBYP BIT(3) 153 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) 154 #define RCC_BDCR_LSEDRV_SHIFT 4 155 #define RCC_BDCR_LSECSSON BIT(8) 156 #define RCC_BDCR_RTCCKEN BIT(20) 157 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) 158 #define RCC_BDCR_RTCSRC_SHIFT 16 159 160 /* Fields of RCC_RDLSICR register */ 161 #define RCC_RDLSICR_LSION BIT(0) 162 #define RCC_RDLSICR_LSIRDY BIT(1) 163 164 /* used for ALL PLLNCR registers */ 165 #define RCC_PLLNCR_PLLON BIT(0) 166 #define RCC_PLLNCR_PLLRDY BIT(1) 167 #define RCC_PLLNCR_DIVPEN BIT(4) 168 #define RCC_PLLNCR_DIVQEN BIT(5) 169 #define RCC_PLLNCR_DIVREN BIT(6) 170 #define RCC_PLLNCR_DIVEN_SHIFT 4 171 172 /* used for ALL PLLNCFGR1 registers */ 173 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 174 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) 175 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 176 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) 177 /* only for PLL3 and PLL4 */ 178 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 179 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) 180 181 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */ 182 #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8) 183 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) 184 #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P) 185 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) 186 #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q) 187 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) 188 #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R) 189 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) 190 191 /* used for ALL PLLNFRACR registers */ 192 #define RCC_PLLNFRACR_FRACV_SHIFT 3 193 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) 194 #define RCC_PLLNFRACR_FRACLE BIT(16) 195 196 /* used for ALL PLLNCSGR registers */ 197 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 198 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) 199 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 200 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) 201 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 202 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) 203 204 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */ 205 #define RCC_OCENR_HSION BIT(0) 206 #define RCC_OCENR_CSION BIT(4) 207 #define RCC_OCENR_DIGBYP BIT(7) 208 #define RCC_OCENR_HSEON BIT(8) 209 #define RCC_OCENR_HSEBYP BIT(10) 210 #define RCC_OCENR_HSECSSON BIT(11) 211 212 /* Fields of RCC_OCRDYR register */ 213 #define RCC_OCRDYR_HSIRDY BIT(0) 214 #define RCC_OCRDYR_HSIDIVRDY BIT(2) 215 #define RCC_OCRDYR_CSIRDY BIT(4) 216 #define RCC_OCRDYR_HSERDY BIT(8) 217 218 /* Fields of DDRITFCR register */ 219 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) 220 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 221 #define RCC_DDRITFCR_DDRCKMOD_SSR 0 222 223 /* Fields of RCC_HSICFGR register */ 224 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) 225 226 /* used for MCO related operations */ 227 #define RCC_MCOCFG_MCOON BIT(12) 228 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) 229 #define RCC_MCOCFG_MCODIV_SHIFT 4 230 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) 231 232 enum stm32mp1_parent_id { 233 /* 234 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved 235 * they are used as index in osc[] as entry point 236 */ 237 _HSI, 238 _HSE, 239 _CSI, 240 _LSI, 241 _LSE, 242 _I2S_CKIN, 243 _USB_PHY_48, 244 NB_OSC, 245 246 /* other parent source */ 247 _HSI_KER = NB_OSC, 248 _HSE_KER, 249 _HSE_KER_DIV2, 250 _CSI_KER, 251 _PLL1_P, 252 _PLL1_Q, 253 _PLL1_R, 254 _PLL2_P, 255 _PLL2_Q, 256 _PLL2_R, 257 _PLL3_P, 258 _PLL3_Q, 259 _PLL3_R, 260 _PLL4_P, 261 _PLL4_Q, 262 _PLL4_R, 263 _ACLK, 264 _PCLK1, 265 _PCLK2, 266 _PCLK3, 267 _PCLK4, 268 _PCLK5, 269 _HCLK6, 270 _HCLK2, 271 _CK_PER, 272 _CK_MPU, 273 _CK_MCU, 274 _DSI_PHY, 275 _PARENT_NB, 276 _UNKNOWN_ID = 0xff, 277 }; 278 279 enum stm32mp1_parent_sel { 280 _I2C12_SEL, 281 _I2C35_SEL, 282 _I2C46_SEL, 283 _UART6_SEL, 284 _UART24_SEL, 285 _UART35_SEL, 286 _UART78_SEL, 287 _SDMMC12_SEL, 288 _SDMMC3_SEL, 289 _ETH_SEL, 290 _QSPI_SEL, 291 _FMC_SEL, 292 _USBPHY_SEL, 293 _USBO_SEL, 294 _STGEN_SEL, 295 _DSI_SEL, 296 _ADC12_SEL, 297 _PARENT_SEL_NB, 298 _UNKNOWN_SEL = 0xff, 299 }; 300 301 enum stm32mp1_pll_id { 302 _PLL1, 303 _PLL2, 304 _PLL3, 305 _PLL4, 306 _PLL_NB 307 }; 308 309 enum stm32mp1_div_id { 310 _DIV_P, 311 _DIV_Q, 312 _DIV_R, 313 _DIV_NB, 314 }; 315 316 enum stm32mp1_clksrc_id { 317 CLKSRC_MPU, 318 CLKSRC_AXI, 319 CLKSRC_MCU, 320 CLKSRC_PLL12, 321 CLKSRC_PLL3, 322 CLKSRC_PLL4, 323 CLKSRC_RTC, 324 CLKSRC_MCO1, 325 CLKSRC_MCO2, 326 CLKSRC_NB 327 }; 328 329 enum stm32mp1_clkdiv_id { 330 CLKDIV_MPU, 331 CLKDIV_AXI, 332 CLKDIV_MCU, 333 CLKDIV_APB1, 334 CLKDIV_APB2, 335 CLKDIV_APB3, 336 CLKDIV_APB4, 337 CLKDIV_APB5, 338 CLKDIV_RTC, 339 CLKDIV_MCO1, 340 CLKDIV_MCO2, 341 CLKDIV_NB 342 }; 343 344 enum stm32mp1_pllcfg { 345 PLLCFG_M, 346 PLLCFG_N, 347 PLLCFG_P, 348 PLLCFG_Q, 349 PLLCFG_R, 350 PLLCFG_O, 351 PLLCFG_NB 352 }; 353 354 enum stm32mp1_pllcsg { 355 PLLCSG_MOD_PER, 356 PLLCSG_INC_STEP, 357 PLLCSG_SSCG_MODE, 358 PLLCSG_NB 359 }; 360 361 enum stm32mp1_plltype { 362 PLL_800, 363 PLL_1600, 364 PLL_TYPE_NB 365 }; 366 367 struct stm32mp1_pll { 368 u8 refclk_min; 369 u8 refclk_max; 370 u8 divn_max; 371 }; 372 373 struct stm32mp1_clk_gate { 374 u16 offset; 375 u8 bit; 376 u8 index; 377 u8 set_clr; 378 u8 sel; 379 u8 fixed; 380 }; 381 382 struct stm32mp1_clk_sel { 383 u16 offset; 384 u8 src; 385 u8 msk; 386 u8 nb_parent; 387 const u8 *parent; 388 }; 389 390 #define REFCLK_SIZE 4 391 struct stm32mp1_clk_pll { 392 enum stm32mp1_plltype plltype; 393 u16 rckxselr; 394 u16 pllxcfgr1; 395 u16 pllxcfgr2; 396 u16 pllxfracr; 397 u16 pllxcr; 398 u16 pllxcsgr; 399 u8 refclk[REFCLK_SIZE]; 400 }; 401 402 struct stm32mp1_clk_data { 403 const struct stm32mp1_clk_gate *gate; 404 const struct stm32mp1_clk_sel *sel; 405 const struct stm32mp1_clk_pll *pll; 406 const int nb_gate; 407 }; 408 409 struct stm32mp1_clk_priv { 410 fdt_addr_t base; 411 const struct stm32mp1_clk_data *data; 412 ulong osc[NB_OSC]; 413 struct udevice *osc_dev[NB_OSC]; 414 }; 415 416 #define STM32MP1_CLK(off, b, idx, s) \ 417 { \ 418 .offset = (off), \ 419 .bit = (b), \ 420 .index = (idx), \ 421 .set_clr = 0, \ 422 .sel = (s), \ 423 .fixed = _UNKNOWN_ID, \ 424 } 425 426 #define STM32MP1_CLK_F(off, b, idx, f) \ 427 { \ 428 .offset = (off), \ 429 .bit = (b), \ 430 .index = (idx), \ 431 .set_clr = 0, \ 432 .sel = _UNKNOWN_SEL, \ 433 .fixed = (f), \ 434 } 435 436 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 437 { \ 438 .offset = (off), \ 439 .bit = (b), \ 440 .index = (idx), \ 441 .set_clr = 1, \ 442 .sel = (s), \ 443 .fixed = _UNKNOWN_ID, \ 444 } 445 446 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 447 { \ 448 .offset = (off), \ 449 .bit = (b), \ 450 .index = (idx), \ 451 .set_clr = 1, \ 452 .sel = _UNKNOWN_SEL, \ 453 .fixed = (f), \ 454 } 455 456 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 457 [(idx)] = { \ 458 .offset = (off), \ 459 .src = (s), \ 460 .msk = (m), \ 461 .parent = (p), \ 462 .nb_parent = ARRAY_SIZE((p)) \ 463 } 464 465 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ 466 p1, p2, p3, p4) \ 467 [(idx)] = { \ 468 .plltype = (type), \ 469 .rckxselr = (off1), \ 470 .pllxcfgr1 = (off2), \ 471 .pllxcfgr2 = (off3), \ 472 .pllxfracr = (off4), \ 473 .pllxcr = (off5), \ 474 .pllxcsgr = (off6), \ 475 .refclk[0] = (p1), \ 476 .refclk[1] = (p2), \ 477 .refclk[2] = (p3), \ 478 .refclk[3] = (p4), \ 479 } 480 481 static const u8 stm32mp1_clks[][2] = { 482 {CK_PER, _CK_PER}, 483 {CK_MPU, _CK_MPU}, 484 {CK_AXI, _ACLK}, 485 {CK_MCU, _CK_MCU}, 486 {CK_HSE, _HSE}, 487 {CK_CSI, _CSI}, 488 {CK_LSI, _LSI}, 489 {CK_LSE, _LSE}, 490 {CK_HSI, _HSI}, 491 {CK_HSE_DIV2, _HSE_KER_DIV2}, 492 }; 493 494 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 495 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 496 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 497 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 498 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 499 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 500 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 501 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 502 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 503 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 504 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 505 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 506 507 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 508 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 509 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 510 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 517 518 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 519 520 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), 521 522 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q), 523 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q), 524 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL), 525 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 526 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 527 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 528 529 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 530 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 531 532 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2), 533 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL), 534 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 536 537 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 538 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 539 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 540 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 543 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 546 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 548 549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 550 551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL), 552 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), 553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL), 554 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK), 555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 559 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 560 561 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 562 }; 563 564 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 565 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 566 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 567 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 568 _HSE_KER}; 569 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 570 _HSE_KER}; 571 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 572 _HSE_KER}; 573 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 574 _HSE_KER}; 575 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 576 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 577 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; 578 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 579 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 580 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 581 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 582 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER}; 583 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P}; 584 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q}; 585 586 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 587 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), 588 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 589 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 590 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 591 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 592 uart24_parents), 593 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 594 uart35_parents), 595 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 596 uart78_parents), 597 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 598 sdmmc12_parents), 599 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 600 sdmmc3_parents), 601 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), 602 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 603 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 604 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 605 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 606 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 607 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), 608 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents), 609 }; 610 611 #ifdef STM32MP1_CLOCK_TREE_INIT 612 /* define characteristic of PLL according type */ 613 #define DIVN_MIN 24 614 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 615 [PLL_800] = { 616 .refclk_min = 4, 617 .refclk_max = 16, 618 .divn_max = 99, 619 }, 620 [PLL_1600] = { 621 .refclk_min = 8, 622 .refclk_max = 16, 623 .divn_max = 199, 624 }, 625 }; 626 #endif /* STM32MP1_CLOCK_TREE_INIT */ 627 628 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 629 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 630 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 631 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 632 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 633 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 634 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 635 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 636 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 637 STM32MP1_CLK_PLL(_PLL3, PLL_800, 638 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 639 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 640 _HSI, _HSE, _CSI, _UNKNOWN_ID), 641 STM32MP1_CLK_PLL(_PLL4, PLL_800, 642 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 643 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 644 _HSI, _HSE, _CSI, _I2S_CKIN), 645 }; 646 647 /* Prescaler table lookups for clock computation */ 648 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 649 static const u8 stm32mp1_mcu_div[16] = { 650 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 651 }; 652 653 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/ 654 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 655 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 656 static const u8 stm32mp1_mpu_apbx_div[8] = { 657 0, 1, 2, 3, 4, 4, 4, 4 658 }; 659 660 /* div = /1 /2 /3 /4 */ 661 static const u8 stm32mp1_axi_div[8] = { 662 1, 2, 3, 4, 4, 4, 4, 4 663 }; 664 665 #ifdef DEBUG 666 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { 667 [_HSI] = "HSI", 668 [_HSE] = "HSE", 669 [_CSI] = "CSI", 670 [_LSI] = "LSI", 671 [_LSE] = "LSE", 672 [_I2S_CKIN] = "I2S_CKIN", 673 [_HSI_KER] = "HSI_KER", 674 [_HSE_KER] = "HSE_KER", 675 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 676 [_CSI_KER] = "CSI_KER", 677 [_PLL1_P] = "PLL1_P", 678 [_PLL1_Q] = "PLL1_Q", 679 [_PLL1_R] = "PLL1_R", 680 [_PLL2_P] = "PLL2_P", 681 [_PLL2_Q] = "PLL2_Q", 682 [_PLL2_R] = "PLL2_R", 683 [_PLL3_P] = "PLL3_P", 684 [_PLL3_Q] = "PLL3_Q", 685 [_PLL3_R] = "PLL3_R", 686 [_PLL4_P] = "PLL4_P", 687 [_PLL4_Q] = "PLL4_Q", 688 [_PLL4_R] = "PLL4_R", 689 [_ACLK] = "ACLK", 690 [_PCLK1] = "PCLK1", 691 [_PCLK2] = "PCLK2", 692 [_PCLK3] = "PCLK3", 693 [_PCLK4] = "PCLK4", 694 [_PCLK5] = "PCLK5", 695 [_HCLK6] = "KCLK6", 696 [_HCLK2] = "HCLK2", 697 [_CK_PER] = "CK_PER", 698 [_CK_MPU] = "CK_MPU", 699 [_CK_MCU] = "CK_MCU", 700 [_USB_PHY_48] = "USB_PHY_48", 701 [_DSI_PHY] = "DSI_PHY_PLL", 702 }; 703 704 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { 705 [_I2C12_SEL] = "I2C12", 706 [_I2C35_SEL] = "I2C35", 707 [_I2C46_SEL] = "I2C46", 708 [_UART6_SEL] = "UART6", 709 [_UART24_SEL] = "UART24", 710 [_UART35_SEL] = "UART35", 711 [_UART78_SEL] = "UART78", 712 [_SDMMC12_SEL] = "SDMMC12", 713 [_SDMMC3_SEL] = "SDMMC3", 714 [_ETH_SEL] = "ETH", 715 [_QSPI_SEL] = "QSPI", 716 [_FMC_SEL] = "FMC", 717 [_USBPHY_SEL] = "USBPHY", 718 [_USBO_SEL] = "USBO", 719 [_STGEN_SEL] = "STGEN", 720 [_DSI_SEL] = "DSI", 721 [_ADC12_SEL] = "ADC12", 722 }; 723 #endif 724 725 static const struct stm32mp1_clk_data stm32mp1_data = { 726 .gate = stm32mp1_clk_gate, 727 .sel = stm32mp1_clk_sel, 728 .pll = stm32mp1_clk_pll, 729 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 730 }; 731 732 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) 733 { 734 if (idx >= NB_OSC) { 735 debug("%s: clk id %d not found\n", __func__, idx); 736 return 0; 737 } 738 739 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, 740 (u32)priv->osc[idx], priv->osc[idx] / 1000); 741 742 return priv->osc[idx]; 743 } 744 745 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 746 { 747 const struct stm32mp1_clk_gate *gate = priv->data->gate; 748 int i, nb_clks = priv->data->nb_gate; 749 750 for (i = 0; i < nb_clks; i++) { 751 if (gate[i].index == id) 752 break; 753 } 754 755 if (i == nb_clks) { 756 printf("%s: clk id %d not found\n", __func__, (u32)id); 757 return -EINVAL; 758 } 759 760 return i; 761 } 762 763 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, 764 int i) 765 { 766 const struct stm32mp1_clk_gate *gate = priv->data->gate; 767 768 if (gate[i].sel > _PARENT_SEL_NB) { 769 printf("%s: parents for clk id %d not found\n", 770 __func__, i); 771 return -EINVAL; 772 } 773 774 return gate[i].sel; 775 } 776 777 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, 778 int i) 779 { 780 const struct stm32mp1_clk_gate *gate = priv->data->gate; 781 782 if (gate[i].fixed == _UNKNOWN_ID) 783 return -ENOENT; 784 785 return gate[i].fixed; 786 } 787 788 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 789 unsigned long id) 790 { 791 const struct stm32mp1_clk_sel *sel = priv->data->sel; 792 int i; 793 int s, p; 794 795 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) 796 if (stm32mp1_clks[i][0] == id) 797 return stm32mp1_clks[i][1]; 798 799 i = stm32mp1_clk_get_id(priv, id); 800 if (i < 0) 801 return i; 802 803 p = stm32mp1_clk_get_fixed_parent(priv, i); 804 if (p >= 0 && p < _PARENT_NB) 805 return p; 806 807 s = stm32mp1_clk_get_sel(priv, i); 808 if (s < 0) 809 return s; 810 811 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; 812 813 if (p < sel[s].nb_parent) { 814 #ifdef DEBUG 815 debug("%s: %s clock is the parent %s of clk id %d\n", __func__, 816 stm32mp1_clk_parent_name[sel[s].parent[p]], 817 stm32mp1_clk_parent_sel_name[s], 818 (u32)id); 819 #endif 820 return sel[s].parent[p]; 821 } 822 823 pr_err("%s: no parents defined for clk id %d\n", 824 __func__, (u32)id); 825 826 return -EINVAL; 827 } 828 829 static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv, 830 int pll_id) 831 { 832 const struct stm32mp1_clk_pll *pll = priv->data->pll; 833 u32 selr; 834 int src; 835 ulong refclk; 836 837 /* Get current refclk */ 838 selr = readl(priv->base + pll[pll_id].rckxselr); 839 src = selr & RCC_SELR_SRC_MASK; 840 841 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 842 debug("PLL%d : selr=%x refclk = %d kHz\n", 843 pll_id, selr, (u32)(refclk / 1000)); 844 845 return refclk; 846 } 847 848 /* 849 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 850 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 851 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 852 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 853 */ 854 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, 855 int pll_id) 856 { 857 const struct stm32mp1_clk_pll *pll = priv->data->pll; 858 int divm, divn; 859 ulong refclk, fvco; 860 u32 cfgr1, fracr; 861 862 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); 863 fracr = readl(priv->base + pll[pll_id].pllxfracr); 864 865 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 866 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 867 868 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n", 869 pll_id, cfgr1, fracr, divn, divm); 870 871 refclk = pll_get_fref_ck(priv, pll_id); 872 873 /* with FRACV : 874 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 875 * without FRACV 876 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 877 */ 878 if (fracr & RCC_PLLNFRACR_FRACLE) { 879 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 880 >> RCC_PLLNFRACR_FRACV_SHIFT; 881 fvco = (ulong)lldiv((unsigned long long)refclk * 882 (((divn + 1) << 13) + fracv), 883 ((unsigned long long)(divm + 1)) << 13); 884 } else { 885 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); 886 } 887 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco); 888 889 return fvco; 890 } 891 892 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 893 int pll_id, int div_id) 894 { 895 const struct stm32mp1_clk_pll *pll = priv->data->pll; 896 int divy; 897 ulong dfout; 898 u32 cfgr2; 899 900 debug("%s(%d, %d)\n", __func__, pll_id, div_id); 901 if (div_id >= _DIV_NB) 902 return 0; 903 904 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); 905 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK; 906 907 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy); 908 909 dfout = pll_get_fvco(priv, pll_id) / (divy + 1); 910 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); 911 912 return dfout; 913 } 914 915 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 916 { 917 u32 reg; 918 ulong clock = 0; 919 920 switch (p) { 921 case _CK_MPU: 922 /* MPU sub system */ 923 reg = readl(priv->base + RCC_MPCKSELR); 924 switch (reg & RCC_SELR_SRC_MASK) { 925 case RCC_MPCKSELR_HSI: 926 clock = stm32mp1_clk_get_fixed(priv, _HSI); 927 break; 928 case RCC_MPCKSELR_HSE: 929 clock = stm32mp1_clk_get_fixed(priv, _HSE); 930 break; 931 case RCC_MPCKSELR_PLL: 932 case RCC_MPCKSELR_PLL_MPUDIV: 933 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 934 if (p == RCC_MPCKSELR_PLL_MPUDIV) { 935 reg = readl(priv->base + RCC_MPCKDIVR); 936 clock /= stm32mp1_mpu_div[reg & 937 RCC_MPUDIV_MASK]; 938 } 939 break; 940 } 941 break; 942 /* AXI sub system */ 943 case _ACLK: 944 case _HCLK2: 945 case _HCLK6: 946 case _PCLK4: 947 case _PCLK5: 948 reg = readl(priv->base + RCC_ASSCKSELR); 949 switch (reg & RCC_SELR_SRC_MASK) { 950 case RCC_ASSCKSELR_HSI: 951 clock = stm32mp1_clk_get_fixed(priv, _HSI); 952 break; 953 case RCC_ASSCKSELR_HSE: 954 clock = stm32mp1_clk_get_fixed(priv, _HSE); 955 break; 956 case RCC_ASSCKSELR_PLL: 957 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 958 break; 959 } 960 961 /* System clock divider */ 962 reg = readl(priv->base + RCC_AXIDIVR); 963 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 964 965 switch (p) { 966 case _PCLK4: 967 reg = readl(priv->base + RCC_APB4DIVR); 968 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 969 break; 970 case _PCLK5: 971 reg = readl(priv->base + RCC_APB5DIVR); 972 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 973 break; 974 default: 975 break; 976 } 977 break; 978 /* MCU sub system */ 979 case _CK_MCU: 980 case _PCLK1: 981 case _PCLK2: 982 case _PCLK3: 983 reg = readl(priv->base + RCC_MSSCKSELR); 984 switch (reg & RCC_SELR_SRC_MASK) { 985 case RCC_MSSCKSELR_HSI: 986 clock = stm32mp1_clk_get_fixed(priv, _HSI); 987 break; 988 case RCC_MSSCKSELR_HSE: 989 clock = stm32mp1_clk_get_fixed(priv, _HSE); 990 break; 991 case RCC_MSSCKSELR_CSI: 992 clock = stm32mp1_clk_get_fixed(priv, _CSI); 993 break; 994 case RCC_MSSCKSELR_PLL: 995 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 996 break; 997 } 998 999 /* MCU clock divider */ 1000 reg = readl(priv->base + RCC_MCUDIVR); 1001 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 1002 1003 switch (p) { 1004 case _PCLK1: 1005 reg = readl(priv->base + RCC_APB1DIVR); 1006 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1007 break; 1008 case _PCLK2: 1009 reg = readl(priv->base + RCC_APB2DIVR); 1010 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1011 break; 1012 case _PCLK3: 1013 reg = readl(priv->base + RCC_APB3DIVR); 1014 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1015 break; 1016 case _CK_MCU: 1017 default: 1018 break; 1019 } 1020 break; 1021 case _CK_PER: 1022 reg = readl(priv->base + RCC_CPERCKSELR); 1023 switch (reg & RCC_SELR_SRC_MASK) { 1024 case RCC_CPERCKSELR_HSI: 1025 clock = stm32mp1_clk_get_fixed(priv, _HSI); 1026 break; 1027 case RCC_CPERCKSELR_HSE: 1028 clock = stm32mp1_clk_get_fixed(priv, _HSE); 1029 break; 1030 case RCC_CPERCKSELR_CSI: 1031 clock = stm32mp1_clk_get_fixed(priv, _CSI); 1032 break; 1033 } 1034 break; 1035 case _HSI: 1036 case _HSI_KER: 1037 clock = stm32mp1_clk_get_fixed(priv, _HSI); 1038 break; 1039 case _CSI: 1040 case _CSI_KER: 1041 clock = stm32mp1_clk_get_fixed(priv, _CSI); 1042 break; 1043 case _HSE: 1044 case _HSE_KER: 1045 case _HSE_KER_DIV2: 1046 clock = stm32mp1_clk_get_fixed(priv, _HSE); 1047 if (p == _HSE_KER_DIV2) 1048 clock >>= 1; 1049 break; 1050 case _LSI: 1051 clock = stm32mp1_clk_get_fixed(priv, _LSI); 1052 break; 1053 case _LSE: 1054 clock = stm32mp1_clk_get_fixed(priv, _LSE); 1055 break; 1056 /* PLL */ 1057 case _PLL1_P: 1058 case _PLL1_Q: 1059 case _PLL1_R: 1060 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); 1061 break; 1062 case _PLL2_P: 1063 case _PLL2_Q: 1064 case _PLL2_R: 1065 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); 1066 break; 1067 case _PLL3_P: 1068 case _PLL3_Q: 1069 case _PLL3_R: 1070 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); 1071 break; 1072 case _PLL4_P: 1073 case _PLL4_Q: 1074 case _PLL4_R: 1075 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); 1076 break; 1077 /* other */ 1078 case _USB_PHY_48: 1079 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); 1080 break; 1081 case _DSI_PHY: 1082 { 1083 struct clk clk; 1084 struct udevice *dev = NULL; 1085 1086 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy", 1087 &dev)) { 1088 if (clk_request(dev, &clk)) { 1089 pr_err("ck_dsi_phy request"); 1090 } else { 1091 clk.id = 0; 1092 clock = clk_get_rate(&clk); 1093 } 1094 } 1095 break; 1096 } 1097 default: 1098 break; 1099 } 1100 1101 debug("%s(%d) clock = %lx : %ld kHz\n", 1102 __func__, p, clock, clock / 1000); 1103 1104 return clock; 1105 } 1106 1107 static int stm32mp1_clk_enable(struct clk *clk) 1108 { 1109 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1110 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1111 int i = stm32mp1_clk_get_id(priv, clk->id); 1112 1113 if (i < 0) 1114 return i; 1115 1116 if (gate[i].set_clr) 1117 writel(BIT(gate[i].bit), priv->base + gate[i].offset); 1118 else 1119 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1120 1121 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); 1122 1123 return 0; 1124 } 1125 1126 static int stm32mp1_clk_disable(struct clk *clk) 1127 { 1128 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1129 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1130 int i = stm32mp1_clk_get_id(priv, clk->id); 1131 1132 if (i < 0) 1133 return i; 1134 1135 if (gate[i].set_clr) 1136 writel(BIT(gate[i].bit), 1137 priv->base + gate[i].offset 1138 + RCC_MP_ENCLRR_OFFSET); 1139 else 1140 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1141 1142 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); 1143 1144 return 0; 1145 } 1146 1147 static ulong stm32mp1_clk_get_rate(struct clk *clk) 1148 { 1149 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1150 int p = stm32mp1_clk_get_parent(priv, clk->id); 1151 ulong rate; 1152 1153 if (p < 0) 1154 return 0; 1155 1156 rate = stm32mp1_clk_get(priv, p); 1157 1158 #ifdef DEBUG 1159 debug("%s: computed rate for id clock %d is %d (parent is %s)\n", 1160 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); 1161 #endif 1162 return rate; 1163 } 1164 1165 #ifdef STM32MP1_CLOCK_TREE_INIT 1166 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, 1167 u32 mask_on) 1168 { 1169 u32 address = rcc + offset; 1170 1171 if (enable) 1172 setbits_le32(address, mask_on); 1173 else 1174 clrbits_le32(address, mask_on); 1175 } 1176 1177 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) 1178 { 1179 if (enable) 1180 setbits_le32(rcc + RCC_OCENSETR, mask_on); 1181 else 1182 setbits_le32(rcc + RCC_OCENCLRR, mask_on); 1183 } 1184 1185 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, 1186 u32 mask_rdy) 1187 { 1188 u32 mask_test = 0; 1189 u32 address = rcc + offset; 1190 u32 val; 1191 int ret; 1192 1193 if (enable) 1194 mask_test = mask_rdy; 1195 1196 ret = readl_poll_timeout(address, val, 1197 (val & mask_rdy) == mask_test, 1198 TIMEOUT_1S); 1199 1200 if (ret) 1201 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", 1202 mask_rdy, address, enable, readl(address)); 1203 1204 return ret; 1205 } 1206 1207 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, 1208 int lsedrv) 1209 { 1210 u32 value; 1211 1212 if (digbyp) 1213 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); 1214 1215 if (bypass || digbyp) 1216 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 1217 1218 /* 1219 * warning: not recommended to switch directly from "high drive" 1220 * to "medium low drive", and vice-versa. 1221 */ 1222 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) 1223 >> RCC_BDCR_LSEDRV_SHIFT; 1224 1225 while (value != lsedrv) { 1226 if (value > lsedrv) 1227 value--; 1228 else 1229 value++; 1230 1231 clrsetbits_le32(rcc + RCC_BDCR, 1232 RCC_BDCR_LSEDRV_MASK, 1233 value << RCC_BDCR_LSEDRV_SHIFT); 1234 } 1235 1236 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 1237 } 1238 1239 static void stm32mp1_lse_wait(fdt_addr_t rcc) 1240 { 1241 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); 1242 } 1243 1244 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) 1245 { 1246 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 1247 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY); 1248 } 1249 1250 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css) 1251 { 1252 if (digbyp) 1253 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1254 if (bypass || digbyp) 1255 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1256 1257 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 1258 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); 1259 1260 if (css) 1261 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1262 } 1263 1264 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) 1265 { 1266 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); 1267 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); 1268 } 1269 1270 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable) 1271 { 1272 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 1273 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY); 1274 } 1275 1276 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) 1277 { 1278 u32 address = rcc + RCC_OCRDYR; 1279 u32 val; 1280 int ret; 1281 1282 clrsetbits_le32(rcc + RCC_HSICFGR, 1283 RCC_HSICFGR_HSIDIV_MASK, 1284 RCC_HSICFGR_HSIDIV_MASK & hsidiv); 1285 1286 ret = readl_poll_timeout(address, val, 1287 val & RCC_OCRDYR_HSIDIVRDY, 1288 TIMEOUT_200MS); 1289 if (ret) 1290 pr_err("HSIDIV failed @ 0x%x: 0x%x\n", 1291 address, readl(address)); 1292 1293 return ret; 1294 } 1295 1296 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) 1297 { 1298 u8 hsidiv; 1299 u32 hsidivfreq = MAX_HSI_HZ; 1300 1301 for (hsidiv = 0; hsidiv < 4; hsidiv++, 1302 hsidivfreq = hsidivfreq / 2) 1303 if (hsidivfreq == hsifreq) 1304 break; 1305 1306 if (hsidiv == 4) { 1307 pr_err("clk-hsi frequency invalid"); 1308 return -1; 1309 } 1310 1311 if (hsidiv > 0) 1312 return stm32mp1_set_hsidiv(rcc, hsidiv); 1313 1314 return 0; 1315 } 1316 1317 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) 1318 { 1319 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1320 1321 writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); 1322 } 1323 1324 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) 1325 { 1326 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1327 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1328 u32 val; 1329 int ret; 1330 1331 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY, 1332 TIMEOUT_200MS); 1333 1334 if (ret) { 1335 pr_err("PLL%d start failed @ 0x%x: 0x%x\n", 1336 pll_id, pllxcr, readl(pllxcr)); 1337 return ret; 1338 } 1339 1340 /* start the requested output */ 1341 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1342 1343 return 0; 1344 } 1345 1346 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id) 1347 { 1348 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1349 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1350 u32 val; 1351 1352 /* stop all output */ 1353 clrbits_le32(pllxcr, 1354 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1355 1356 /* stop PLL */ 1357 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON); 1358 1359 /* wait PLL stopped */ 1360 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0, 1361 TIMEOUT_200MS); 1362 } 1363 1364 static void pll_config_output(struct stm32mp1_clk_priv *priv, 1365 int pll_id, u32 *pllcfg) 1366 { 1367 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1368 fdt_addr_t rcc = priv->base; 1369 u32 value; 1370 1371 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) 1372 & RCC_PLLNCFGR2_DIVP_MASK; 1373 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) 1374 & RCC_PLLNCFGR2_DIVQ_MASK; 1375 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) 1376 & RCC_PLLNCFGR2_DIVR_MASK; 1377 writel(value, rcc + pll[pll_id].pllxcfgr2); 1378 } 1379 1380 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, 1381 u32 *pllcfg, u32 fracv) 1382 { 1383 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1384 fdt_addr_t rcc = priv->base; 1385 enum stm32mp1_plltype type = pll[pll_id].plltype; 1386 int src; 1387 ulong refclk; 1388 u8 ifrge = 0; 1389 u32 value; 1390 1391 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; 1392 1393 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1394 (pllcfg[PLLCFG_M] + 1); 1395 1396 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || 1397 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { 1398 debug("invalid refclk = %x\n", (u32)refclk); 1399 return -EINVAL; 1400 } 1401 if (type == PLL_800 && refclk >= 8000000) 1402 ifrge = 1; 1403 1404 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) 1405 & RCC_PLLNCFGR1_DIVN_MASK; 1406 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) 1407 & RCC_PLLNCFGR1_DIVM_MASK; 1408 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) 1409 & RCC_PLLNCFGR1_IFRGE_MASK; 1410 writel(value, rcc + pll[pll_id].pllxcfgr1); 1411 1412 /* fractional configuration: load sigma-delta modulator (SDM) */ 1413 1414 /* Write into FRACV the new fractional value , and FRACLE to 0 */ 1415 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT, 1416 rcc + pll[pll_id].pllxfracr); 1417 1418 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */ 1419 setbits_le32(rcc + pll[pll_id].pllxfracr, 1420 RCC_PLLNFRACR_FRACLE); 1421 1422 pll_config_output(priv, pll_id, pllcfg); 1423 1424 return 0; 1425 } 1426 1427 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) 1428 { 1429 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1430 u32 pllxcsg; 1431 1432 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1433 RCC_PLLNCSGR_MOD_PER_MASK) | 1434 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1435 RCC_PLLNCSGR_INC_STEP_MASK) | 1436 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1437 RCC_PLLNCSGR_SSCG_MODE_MASK); 1438 1439 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); 1440 } 1441 1442 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) 1443 { 1444 u32 address = priv->base + (clksrc >> 4); 1445 u32 val; 1446 int ret; 1447 1448 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); 1449 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, 1450 TIMEOUT_200MS); 1451 if (ret) 1452 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1453 clksrc, address, readl(address)); 1454 1455 return ret; 1456 } 1457 1458 static void stgen_config(struct stm32mp1_clk_priv *priv) 1459 { 1460 int p; 1461 u32 stgenc, cntfid0; 1462 ulong rate; 1463 1464 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); 1465 1466 cntfid0 = readl(stgenc + STGENC_CNTFID0); 1467 p = stm32mp1_clk_get_parent(priv, STGEN_K); 1468 rate = stm32mp1_clk_get(priv, p); 1469 1470 if (cntfid0 != rate) { 1471 pr_debug("System Generic Counter (STGEN) update\n"); 1472 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); 1473 writel(0x0, stgenc + STGENC_CNTCVL); 1474 writel(0x0, stgenc + STGENC_CNTCVU); 1475 writel(rate, stgenc + STGENC_CNTFID0); 1476 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); 1477 1478 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); 1479 1480 /* need to update gd->arch.timer_rate_hz with new frequency */ 1481 timer_init(); 1482 pr_debug("gd->arch.timer_rate_hz = %x\n", 1483 (u32)gd->arch.timer_rate_hz); 1484 pr_debug("Tick = %x\n", (u32)(get_ticks())); 1485 } 1486 } 1487 1488 static int set_clkdiv(unsigned int clkdiv, u32 address) 1489 { 1490 u32 val; 1491 int ret; 1492 1493 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); 1494 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, 1495 TIMEOUT_200MS); 1496 if (ret) 1497 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1498 clkdiv, address, readl(address)); 1499 1500 return ret; 1501 } 1502 1503 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1504 u32 clksrc, u32 clkdiv) 1505 { 1506 u32 address = priv->base + (clksrc >> 4); 1507 1508 /* 1509 * binding clksrc : bit15-4 offset 1510 * bit3: disable 1511 * bit2-0: MCOSEL[2:0] 1512 */ 1513 if (clksrc & 0x8) { 1514 clrbits_le32(address, RCC_MCOCFG_MCOON); 1515 } else { 1516 clrsetbits_le32(address, 1517 RCC_MCOCFG_MCOSRC_MASK, 1518 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1519 clrsetbits_le32(address, 1520 RCC_MCOCFG_MCODIV_MASK, 1521 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1522 setbits_le32(address, RCC_MCOCFG_MCOON); 1523 } 1524 } 1525 1526 static void set_rtcsrc(struct stm32mp1_clk_priv *priv, 1527 unsigned int clksrc, 1528 int lse_css) 1529 { 1530 u32 address = priv->base + RCC_BDCR; 1531 1532 if (readl(address) & RCC_BDCR_RTCCKEN) 1533 goto skip_rtc; 1534 1535 if (clksrc == CLK_RTC_DISABLED) 1536 goto skip_rtc; 1537 1538 clrsetbits_le32(address, 1539 RCC_BDCR_RTCSRC_MASK, 1540 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1541 1542 setbits_le32(address, RCC_BDCR_RTCCKEN); 1543 1544 skip_rtc: 1545 if (lse_css) 1546 setbits_le32(address, RCC_BDCR_LSECSSON); 1547 } 1548 1549 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs) 1550 { 1551 u32 address = priv->base + ((pkcs >> 4) & 0xFFF); 1552 u32 value = pkcs & 0xF; 1553 u32 mask = 0xF; 1554 1555 if (pkcs & BIT(31)) { 1556 mask <<= 4; 1557 value <<= 4; 1558 } 1559 clrsetbits_le32(address, mask, value); 1560 } 1561 1562 static int stm32mp1_clktree(struct udevice *dev) 1563 { 1564 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1565 fdt_addr_t rcc = priv->base; 1566 unsigned int clksrc[CLKSRC_NB]; 1567 unsigned int clkdiv[CLKDIV_NB]; 1568 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1569 ofnode plloff[_PLL_NB]; 1570 int ret; 1571 int i, len; 1572 int lse_css = 0; 1573 const u32 *pkcs_cell; 1574 1575 /* check mandatory field */ 1576 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); 1577 if (ret < 0) { 1578 debug("field st,clksrc invalid: error %d\n", ret); 1579 return -FDT_ERR_NOTFOUND; 1580 } 1581 1582 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); 1583 if (ret < 0) { 1584 debug("field st,clkdiv invalid: error %d\n", ret); 1585 return -FDT_ERR_NOTFOUND; 1586 } 1587 1588 /* check mandatory field in each pll */ 1589 for (i = 0; i < _PLL_NB; i++) { 1590 char name[12]; 1591 1592 sprintf(name, "st,pll@%d", i); 1593 plloff[i] = dev_read_subnode(dev, name); 1594 if (!ofnode_valid(plloff[i])) 1595 continue; 1596 ret = ofnode_read_u32_array(plloff[i], "cfg", 1597 pllcfg[i], PLLCFG_NB); 1598 if (ret < 0) { 1599 debug("field cfg invalid: error %d\n", ret); 1600 return -FDT_ERR_NOTFOUND; 1601 } 1602 } 1603 1604 debug("configuration MCO\n"); 1605 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1606 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1607 1608 debug("switch ON osillator\n"); 1609 /* 1610 * switch ON oscillator found in device-tree, 1611 * HSI already ON after bootrom 1612 */ 1613 if (priv->osc[_LSI]) 1614 stm32mp1_lsi_set(rcc, 1); 1615 1616 if (priv->osc[_LSE]) { 1617 int bypass, digbyp, lsedrv; 1618 struct udevice *dev = priv->osc_dev[_LSE]; 1619 1620 bypass = dev_read_bool(dev, "st,bypass"); 1621 digbyp = dev_read_bool(dev, "st,digbypass"); 1622 lse_css = dev_read_bool(dev, "st,css"); 1623 lsedrv = dev_read_u32_default(dev, "st,drive", 1624 LSEDRV_MEDIUM_HIGH); 1625 1626 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv); 1627 } 1628 1629 if (priv->osc[_HSE]) { 1630 int bypass, digbyp, css; 1631 struct udevice *dev = priv->osc_dev[_HSE]; 1632 1633 bypass = dev_read_bool(dev, "st,bypass"); 1634 digbyp = dev_read_bool(dev, "st,digbypass"); 1635 css = dev_read_bool(dev, "st,css"); 1636 1637 stm32mp1_hse_enable(rcc, bypass, digbyp, css); 1638 } 1639 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1640 * => switch on CSI even if node is not present in device tree 1641 */ 1642 stm32mp1_csi_set(rcc, 1); 1643 1644 /* come back to HSI */ 1645 debug("come back to HSI\n"); 1646 set_clksrc(priv, CLK_MPU_HSI); 1647 set_clksrc(priv, CLK_AXI_HSI); 1648 set_clksrc(priv, CLK_MCU_HSI); 1649 1650 debug("pll stop\n"); 1651 for (i = 0; i < _PLL_NB; i++) 1652 pll_stop(priv, i); 1653 1654 /* configure HSIDIV */ 1655 debug("configure HSIDIV\n"); 1656 if (priv->osc[_HSI]) { 1657 stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1658 stgen_config(priv); 1659 } 1660 1661 /* select DIV */ 1662 debug("select DIV\n"); 1663 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1664 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR); 1665 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1666 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1667 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1668 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR); 1669 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1670 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1671 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1672 1673 /* no ready bit for RTC */ 1674 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); 1675 1676 /* configure PLLs source */ 1677 debug("configure PLLs source\n"); 1678 set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1679 set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1680 set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1681 1682 /* configure and start PLLs */ 1683 debug("configure PLLs\n"); 1684 for (i = 0; i < _PLL_NB; i++) { 1685 u32 fracv; 1686 u32 csg[PLLCSG_NB]; 1687 1688 debug("configure PLL %d @ %d\n", i, 1689 ofnode_to_offset(plloff[i])); 1690 if (!ofnode_valid(plloff[i])) 1691 continue; 1692 1693 fracv = ofnode_read_u32_default(plloff[i], "frac", 0); 1694 pll_config(priv, i, pllcfg[i], fracv); 1695 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); 1696 if (!ret) { 1697 pll_csg(priv, i, csg); 1698 } else if (ret != -FDT_ERR_NOTFOUND) { 1699 debug("invalid csg node for pll@%d res=%d\n", i, ret); 1700 return ret; 1701 } 1702 pll_start(priv, i); 1703 } 1704 1705 /* wait and start PLLs ouptut when ready */ 1706 for (i = 0; i < _PLL_NB; i++) { 1707 if (!ofnode_valid(plloff[i])) 1708 continue; 1709 debug("output PLL %d\n", i); 1710 pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1711 } 1712 1713 /* wait LSE ready before to use it */ 1714 if (priv->osc[_LSE]) 1715 stm32mp1_lse_wait(rcc); 1716 1717 /* configure with expected clock source */ 1718 debug("CLKSRC\n"); 1719 set_clksrc(priv, clksrc[CLKSRC_MPU]); 1720 set_clksrc(priv, clksrc[CLKSRC_AXI]); 1721 set_clksrc(priv, clksrc[CLKSRC_MCU]); 1722 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1723 1724 /* configure PKCK */ 1725 debug("PKCK\n"); 1726 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); 1727 if (pkcs_cell) { 1728 bool ckper_disabled = false; 1729 1730 for (i = 0; i < len / sizeof(u32); i++) { 1731 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]); 1732 1733 if (pkcs == CLK_CKPER_DISABLED) { 1734 ckper_disabled = true; 1735 continue; 1736 } 1737 pkcs_config(priv, pkcs); 1738 } 1739 /* CKPER is source for some peripheral clock 1740 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1741 * only if previous clock is still ON 1742 * => deactivated CKPER only after switching clock 1743 */ 1744 if (ckper_disabled) 1745 pkcs_config(priv, CLK_CKPER_DISABLED); 1746 } 1747 1748 /* STGEN clock source can change with CLK_STGEN_XXX */ 1749 stgen_config(priv); 1750 1751 debug("oscillator off\n"); 1752 /* switch OFF HSI if not found in device-tree */ 1753 if (!priv->osc[_HSI]) 1754 stm32mp1_hsi_set(rcc, 0); 1755 1756 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1757 clrsetbits_le32(priv->base + RCC_DDRITFCR, 1758 RCC_DDRITFCR_DDRCKMOD_MASK, 1759 RCC_DDRITFCR_DDRCKMOD_SSR << 1760 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1761 1762 return 0; 1763 } 1764 #endif /* STM32MP1_CLOCK_TREE_INIT */ 1765 1766 static int pll_set_output_rate(struct udevice *dev, 1767 int pll_id, 1768 int div_id, 1769 unsigned long clk_rate) 1770 { 1771 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1772 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1773 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1774 int div; 1775 ulong fvco; 1776 1777 if (div_id > _DIV_NB) 1778 return -EINVAL; 1779 1780 fvco = pll_get_fvco(priv, pll_id); 1781 1782 if (fvco <= clk_rate) 1783 div = 1; 1784 else 1785 div = DIV_ROUND_UP(fvco, clk_rate); 1786 1787 if (div > 128) 1788 div = 128; 1789 1790 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div); 1791 /* stop the requested output */ 1792 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); 1793 /* change divider */ 1794 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2, 1795 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id), 1796 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id)); 1797 /* start the requested output */ 1798 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); 1799 1800 return 0; 1801 } 1802 1803 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) 1804 { 1805 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1806 int p; 1807 1808 switch (clk->id) { 1809 case LTDC_PX: 1810 case DSI_PX: 1811 break; 1812 default: 1813 pr_err("not supported"); 1814 return -EINVAL; 1815 } 1816 1817 p = stm32mp1_clk_get_parent(priv, clk->id); 1818 if (p < 0) 1819 return -EINVAL; 1820 1821 switch (p) { 1822 case _PLL4_Q: 1823 /* for LTDC_PX and DSI_PX case */ 1824 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate); 1825 } 1826 1827 return -EINVAL; 1828 } 1829 1830 static void stm32mp1_osc_clk_init(const char *name, 1831 struct stm32mp1_clk_priv *priv, 1832 int index) 1833 { 1834 struct clk clk; 1835 struct udevice *dev = NULL; 1836 1837 priv->osc[index] = 0; 1838 clk.id = 0; 1839 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { 1840 if (clk_request(dev, &clk)) 1841 pr_err("%s request", name); 1842 else 1843 priv->osc[index] = clk_get_rate(&clk); 1844 } 1845 priv->osc_dev[index] = dev; 1846 } 1847 1848 static void stm32mp1_osc_init(struct udevice *dev) 1849 { 1850 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1851 int i; 1852 const char *name[NB_OSC] = { 1853 [_LSI] = "clk-lsi", 1854 [_LSE] = "clk-lse", 1855 [_HSI] = "clk-hsi", 1856 [_HSE] = "clk-hse", 1857 [_CSI] = "clk-csi", 1858 [_I2S_CKIN] = "i2s_ckin", 1859 [_USB_PHY_48] = "ck_usbo_48m"}; 1860 1861 for (i = 0; i < NB_OSC; i++) { 1862 stm32mp1_osc_clk_init(name[i], priv, i); 1863 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); 1864 } 1865 } 1866 1867 static int stm32mp1_clk_probe(struct udevice *dev) 1868 { 1869 int result = 0; 1870 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1871 1872 priv->base = dev_read_addr(dev->parent); 1873 if (priv->base == FDT_ADDR_T_NONE) 1874 return -EINVAL; 1875 1876 priv->data = (void *)&stm32mp1_data; 1877 1878 if (!priv->data->gate || !priv->data->sel || 1879 !priv->data->pll) 1880 return -EINVAL; 1881 1882 stm32mp1_osc_init(dev); 1883 1884 #ifdef STM32MP1_CLOCK_TREE_INIT 1885 /* clock tree init is done only one time, before relocation */ 1886 if (!(gd->flags & GD_FLG_RELOC)) 1887 result = stm32mp1_clktree(dev); 1888 #endif 1889 1890 return result; 1891 } 1892 1893 static const struct clk_ops stm32mp1_clk_ops = { 1894 .enable = stm32mp1_clk_enable, 1895 .disable = stm32mp1_clk_disable, 1896 .get_rate = stm32mp1_clk_get_rate, 1897 .set_rate = stm32mp1_clk_set_rate, 1898 }; 1899 1900 U_BOOT_DRIVER(stm32mp1_clock) = { 1901 .name = "stm32mp1_clk", 1902 .id = UCLASS_CLK, 1903 .ops = &stm32mp1_clk_ops, 1904 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv), 1905 .probe = stm32mp1_clk_probe, 1906 }; 1907