1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <div64.h> 9 #include <dm.h> 10 #include <regmap.h> 11 #include <spl.h> 12 #include <syscon.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <dt-bindings/clock/stm32mp1-clks.h> 16 #include <dt-bindings/clock/stm32mp1-clksrc.h> 17 18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 19 /* activate clock tree initialization in the driver */ 20 #define STM32MP1_CLOCK_TREE_INIT 21 #endif 22 23 #define MAX_HSI_HZ 64000000 24 25 /* TIMEOUT */ 26 #define TIMEOUT_200MS 200000 27 #define TIMEOUT_1S 1000000 28 29 /* STGEN registers */ 30 #define STGENC_CNTCR 0x00 31 #define STGENC_CNTSR 0x04 32 #define STGENC_CNTCVL 0x08 33 #define STGENC_CNTCVU 0x0C 34 #define STGENC_CNTFID0 0x20 35 36 #define STGENC_CNTCR_EN BIT(0) 37 38 /* RCC registers */ 39 #define RCC_OCENSETR 0x0C 40 #define RCC_OCENCLRR 0x10 41 #define RCC_HSICFGR 0x18 42 #define RCC_MPCKSELR 0x20 43 #define RCC_ASSCKSELR 0x24 44 #define RCC_RCK12SELR 0x28 45 #define RCC_MPCKDIVR 0x2C 46 #define RCC_AXIDIVR 0x30 47 #define RCC_APB4DIVR 0x3C 48 #define RCC_APB5DIVR 0x40 49 #define RCC_RTCDIVR 0x44 50 #define RCC_MSSCKSELR 0x48 51 #define RCC_PLL1CR 0x80 52 #define RCC_PLL1CFGR1 0x84 53 #define RCC_PLL1CFGR2 0x88 54 #define RCC_PLL1FRACR 0x8C 55 #define RCC_PLL1CSGR 0x90 56 #define RCC_PLL2CR 0x94 57 #define RCC_PLL2CFGR1 0x98 58 #define RCC_PLL2CFGR2 0x9C 59 #define RCC_PLL2FRACR 0xA0 60 #define RCC_PLL2CSGR 0xA4 61 #define RCC_I2C46CKSELR 0xC0 62 #define RCC_CPERCKSELR 0xD0 63 #define RCC_STGENCKSELR 0xD4 64 #define RCC_DDRITFCR 0xD8 65 #define RCC_BDCR 0x140 66 #define RCC_RDLSICR 0x144 67 #define RCC_MP_APB4ENSETR 0x200 68 #define RCC_MP_APB5ENSETR 0x208 69 #define RCC_MP_AHB5ENSETR 0x210 70 #define RCC_MP_AHB6ENSETR 0x218 71 #define RCC_OCRDYR 0x808 72 #define RCC_DBGCFGR 0x80C 73 #define RCC_RCK3SELR 0x820 74 #define RCC_RCK4SELR 0x824 75 #define RCC_MCUDIVR 0x830 76 #define RCC_APB1DIVR 0x834 77 #define RCC_APB2DIVR 0x838 78 #define RCC_APB3DIVR 0x83C 79 #define RCC_PLL3CR 0x880 80 #define RCC_PLL3CFGR1 0x884 81 #define RCC_PLL3CFGR2 0x888 82 #define RCC_PLL3FRACR 0x88C 83 #define RCC_PLL3CSGR 0x890 84 #define RCC_PLL4CR 0x894 85 #define RCC_PLL4CFGR1 0x898 86 #define RCC_PLL4CFGR2 0x89C 87 #define RCC_PLL4FRACR 0x8A0 88 #define RCC_PLL4CSGR 0x8A4 89 #define RCC_I2C12CKSELR 0x8C0 90 #define RCC_I2C35CKSELR 0x8C4 91 #define RCC_UART6CKSELR 0x8E4 92 #define RCC_UART24CKSELR 0x8E8 93 #define RCC_UART35CKSELR 0x8EC 94 #define RCC_UART78CKSELR 0x8F0 95 #define RCC_SDMMC12CKSELR 0x8F4 96 #define RCC_SDMMC3CKSELR 0x8F8 97 #define RCC_ETHCKSELR 0x8FC 98 #define RCC_QSPICKSELR 0x900 99 #define RCC_FMCCKSELR 0x904 100 #define RCC_USBCKSELR 0x91C 101 #define RCC_MP_APB1ENSETR 0xA00 102 #define RCC_MP_APB2ENSETR 0XA08 103 #define RCC_MP_AHB2ENSETR 0xA18 104 #define RCC_MP_AHB4ENSETR 0xA28 105 106 /* used for most of SELR register */ 107 #define RCC_SELR_SRC_MASK GENMASK(2, 0) 108 #define RCC_SELR_SRCRDY BIT(31) 109 110 /* Values of RCC_MPCKSELR register */ 111 #define RCC_MPCKSELR_HSI 0 112 #define RCC_MPCKSELR_HSE 1 113 #define RCC_MPCKSELR_PLL 2 114 #define RCC_MPCKSELR_PLL_MPUDIV 3 115 116 /* Values of RCC_ASSCKSELR register */ 117 #define RCC_ASSCKSELR_HSI 0 118 #define RCC_ASSCKSELR_HSE 1 119 #define RCC_ASSCKSELR_PLL 2 120 121 /* Values of RCC_MSSCKSELR register */ 122 #define RCC_MSSCKSELR_HSI 0 123 #define RCC_MSSCKSELR_HSE 1 124 #define RCC_MSSCKSELR_CSI 2 125 #define RCC_MSSCKSELR_PLL 3 126 127 /* Values of RCC_CPERCKSELR register */ 128 #define RCC_CPERCKSELR_HSI 0 129 #define RCC_CPERCKSELR_CSI 1 130 #define RCC_CPERCKSELR_HSE 2 131 132 /* used for most of DIVR register : max div for RTC */ 133 #define RCC_DIVR_DIV_MASK GENMASK(5, 0) 134 #define RCC_DIVR_DIVRDY BIT(31) 135 136 /* Masks for specific DIVR registers */ 137 #define RCC_APBXDIV_MASK GENMASK(2, 0) 138 #define RCC_MPUDIV_MASK GENMASK(2, 0) 139 #define RCC_AXIDIV_MASK GENMASK(2, 0) 140 #define RCC_MCUDIV_MASK GENMASK(3, 0) 141 142 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 143 #define RCC_MP_ENCLRR_OFFSET 4 144 145 /* Fields of RCC_BDCR register */ 146 #define RCC_BDCR_LSEON BIT(0) 147 #define RCC_BDCR_LSEBYP BIT(1) 148 #define RCC_BDCR_LSERDY BIT(2) 149 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) 150 #define RCC_BDCR_LSEDRV_SHIFT 4 151 #define RCC_BDCR_LSECSSON BIT(8) 152 #define RCC_BDCR_RTCCKEN BIT(20) 153 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) 154 #define RCC_BDCR_RTCSRC_SHIFT 16 155 156 /* Fields of RCC_RDLSICR register */ 157 #define RCC_RDLSICR_LSION BIT(0) 158 #define RCC_RDLSICR_LSIRDY BIT(1) 159 160 /* used for ALL PLLNCR registers */ 161 #define RCC_PLLNCR_PLLON BIT(0) 162 #define RCC_PLLNCR_PLLRDY BIT(1) 163 #define RCC_PLLNCR_DIVPEN BIT(4) 164 #define RCC_PLLNCR_DIVQEN BIT(5) 165 #define RCC_PLLNCR_DIVREN BIT(6) 166 #define RCC_PLLNCR_DIVEN_SHIFT 4 167 168 /* used for ALL PLLNCFGR1 registers */ 169 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 170 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) 171 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 172 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) 173 /* only for PLL3 and PLL4 */ 174 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 175 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) 176 177 /* used for ALL PLLNCFGR2 registers */ 178 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) 179 #define RCC_PLLNCFGR2_DIVP_SHIFT 0 180 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) 181 #define RCC_PLLNCFGR2_DIVQ_SHIFT 8 182 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) 183 #define RCC_PLLNCFGR2_DIVR_SHIFT 16 184 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) 185 186 /* used for ALL PLLNFRACR registers */ 187 #define RCC_PLLNFRACR_FRACV_SHIFT 3 188 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) 189 #define RCC_PLLNFRACR_FRACLE BIT(16) 190 191 /* used for ALL PLLNCSGR registers */ 192 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 193 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) 194 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 195 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) 196 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 197 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) 198 199 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */ 200 #define RCC_OCENR_HSION BIT(0) 201 #define RCC_OCENR_CSION BIT(4) 202 #define RCC_OCENR_HSEON BIT(8) 203 #define RCC_OCENR_HSEBYP BIT(10) 204 #define RCC_OCENR_HSECSSON BIT(11) 205 206 /* Fields of RCC_OCRDYR register */ 207 #define RCC_OCRDYR_HSIRDY BIT(0) 208 #define RCC_OCRDYR_HSIDIVRDY BIT(2) 209 #define RCC_OCRDYR_CSIRDY BIT(4) 210 #define RCC_OCRDYR_HSERDY BIT(8) 211 212 /* Fields of DDRITFCR register */ 213 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) 214 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 215 #define RCC_DDRITFCR_DDRCKMOD_SSR 0 216 217 /* Fields of RCC_HSICFGR register */ 218 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) 219 220 /* used for MCO related operations */ 221 #define RCC_MCOCFG_MCOON BIT(12) 222 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) 223 #define RCC_MCOCFG_MCODIV_SHIFT 4 224 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) 225 226 enum stm32mp1_parent_id { 227 /* 228 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved 229 * they are used as index in osc[] as entry point 230 */ 231 _HSI, 232 _HSE, 233 _CSI, 234 _LSI, 235 _LSE, 236 _I2S_CKIN, 237 _USB_PHY_48, 238 NB_OSC, 239 240 /* other parent source */ 241 _HSI_KER = NB_OSC, 242 _HSE_KER, 243 _HSE_KER_DIV2, 244 _CSI_KER, 245 _PLL1_P, 246 _PLL1_Q, 247 _PLL1_R, 248 _PLL2_P, 249 _PLL2_Q, 250 _PLL2_R, 251 _PLL3_P, 252 _PLL3_Q, 253 _PLL3_R, 254 _PLL4_P, 255 _PLL4_Q, 256 _PLL4_R, 257 _ACLK, 258 _PCLK1, 259 _PCLK2, 260 _PCLK3, 261 _PCLK4, 262 _PCLK5, 263 _HCLK6, 264 _HCLK2, 265 _CK_PER, 266 _CK_MPU, 267 _CK_MCU, 268 _PARENT_NB, 269 _UNKNOWN_ID = 0xff, 270 }; 271 272 enum stm32mp1_parent_sel { 273 _I2C12_SEL, 274 _I2C35_SEL, 275 _I2C46_SEL, 276 _UART6_SEL, 277 _UART24_SEL, 278 _UART35_SEL, 279 _UART78_SEL, 280 _SDMMC12_SEL, 281 _SDMMC3_SEL, 282 _ETH_SEL, 283 _QSPI_SEL, 284 _FMC_SEL, 285 _USBPHY_SEL, 286 _USBO_SEL, 287 _STGEN_SEL, 288 _PARENT_SEL_NB, 289 _UNKNOWN_SEL = 0xff, 290 }; 291 292 enum stm32mp1_pll_id { 293 _PLL1, 294 _PLL2, 295 _PLL3, 296 _PLL4, 297 _PLL_NB 298 }; 299 300 enum stm32mp1_div_id { 301 _DIV_P, 302 _DIV_Q, 303 _DIV_R, 304 _DIV_NB, 305 }; 306 307 enum stm32mp1_clksrc_id { 308 CLKSRC_MPU, 309 CLKSRC_AXI, 310 CLKSRC_MCU, 311 CLKSRC_PLL12, 312 CLKSRC_PLL3, 313 CLKSRC_PLL4, 314 CLKSRC_RTC, 315 CLKSRC_MCO1, 316 CLKSRC_MCO2, 317 CLKSRC_NB 318 }; 319 320 enum stm32mp1_clkdiv_id { 321 CLKDIV_MPU, 322 CLKDIV_AXI, 323 CLKDIV_MCU, 324 CLKDIV_APB1, 325 CLKDIV_APB2, 326 CLKDIV_APB3, 327 CLKDIV_APB4, 328 CLKDIV_APB5, 329 CLKDIV_RTC, 330 CLKDIV_MCO1, 331 CLKDIV_MCO2, 332 CLKDIV_NB 333 }; 334 335 enum stm32mp1_pllcfg { 336 PLLCFG_M, 337 PLLCFG_N, 338 PLLCFG_P, 339 PLLCFG_Q, 340 PLLCFG_R, 341 PLLCFG_O, 342 PLLCFG_NB 343 }; 344 345 enum stm32mp1_pllcsg { 346 PLLCSG_MOD_PER, 347 PLLCSG_INC_STEP, 348 PLLCSG_SSCG_MODE, 349 PLLCSG_NB 350 }; 351 352 enum stm32mp1_plltype { 353 PLL_800, 354 PLL_1600, 355 PLL_TYPE_NB 356 }; 357 358 struct stm32mp1_pll { 359 u8 refclk_min; 360 u8 refclk_max; 361 u8 divn_max; 362 }; 363 364 struct stm32mp1_clk_gate { 365 u16 offset; 366 u8 bit; 367 u8 index; 368 u8 set_clr; 369 u8 sel; 370 u8 fixed; 371 }; 372 373 struct stm32mp1_clk_sel { 374 u16 offset; 375 u8 src; 376 u8 msk; 377 u8 nb_parent; 378 const u8 *parent; 379 }; 380 381 #define REFCLK_SIZE 4 382 struct stm32mp1_clk_pll { 383 enum stm32mp1_plltype plltype; 384 u16 rckxselr; 385 u16 pllxcfgr1; 386 u16 pllxcfgr2; 387 u16 pllxfracr; 388 u16 pllxcr; 389 u16 pllxcsgr; 390 u8 refclk[REFCLK_SIZE]; 391 }; 392 393 struct stm32mp1_clk_data { 394 const struct stm32mp1_clk_gate *gate; 395 const struct stm32mp1_clk_sel *sel; 396 const struct stm32mp1_clk_pll *pll; 397 const int nb_gate; 398 }; 399 400 struct stm32mp1_clk_priv { 401 fdt_addr_t base; 402 const struct stm32mp1_clk_data *data; 403 ulong osc[NB_OSC]; 404 struct udevice *osc_dev[NB_OSC]; 405 }; 406 407 #define STM32MP1_CLK(off, b, idx, s) \ 408 { \ 409 .offset = (off), \ 410 .bit = (b), \ 411 .index = (idx), \ 412 .set_clr = 0, \ 413 .sel = (s), \ 414 .fixed = _UNKNOWN_ID, \ 415 } 416 417 #define STM32MP1_CLK_F(off, b, idx, f) \ 418 { \ 419 .offset = (off), \ 420 .bit = (b), \ 421 .index = (idx), \ 422 .set_clr = 0, \ 423 .sel = _UNKNOWN_SEL, \ 424 .fixed = (f), \ 425 } 426 427 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 428 { \ 429 .offset = (off), \ 430 .bit = (b), \ 431 .index = (idx), \ 432 .set_clr = 1, \ 433 .sel = (s), \ 434 .fixed = _UNKNOWN_ID, \ 435 } 436 437 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 438 { \ 439 .offset = (off), \ 440 .bit = (b), \ 441 .index = (idx), \ 442 .set_clr = 1, \ 443 .sel = _UNKNOWN_SEL, \ 444 .fixed = (f), \ 445 } 446 447 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 448 [(idx)] = { \ 449 .offset = (off), \ 450 .src = (s), \ 451 .msk = (m), \ 452 .parent = (p), \ 453 .nb_parent = ARRAY_SIZE((p)) \ 454 } 455 456 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ 457 p1, p2, p3, p4) \ 458 [(idx)] = { \ 459 .plltype = (type), \ 460 .rckxselr = (off1), \ 461 .pllxcfgr1 = (off2), \ 462 .pllxcfgr2 = (off3), \ 463 .pllxfracr = (off4), \ 464 .pllxcr = (off5), \ 465 .pllxcsgr = (off6), \ 466 .refclk[0] = (p1), \ 467 .refclk[1] = (p2), \ 468 .refclk[2] = (p3), \ 469 .refclk[3] = (p4), \ 470 } 471 472 static const u8 stm32mp1_clks[][2] = { 473 {CK_PER, _CK_PER}, 474 {CK_MPU, _CK_MPU}, 475 {CK_AXI, _ACLK}, 476 {CK_MCU, _CK_MCU}, 477 {CK_HSE, _HSE}, 478 {CK_CSI, _CSI}, 479 {CK_LSI, _LSI}, 480 {CK_LSE, _LSE}, 481 {CK_HSI, _HSI}, 482 {CK_HSE_DIV2, _HSE_KER_DIV2}, 483 }; 484 485 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 486 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 487 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 488 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 489 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 490 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 491 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 492 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 493 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 494 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 495 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 496 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 497 498 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 499 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 500 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 501 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 502 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 503 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 504 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 505 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 506 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 507 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 508 509 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 510 511 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 512 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 513 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 514 515 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 516 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 517 518 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 519 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 520 521 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 522 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 523 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 524 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 525 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 526 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 527 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 528 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 529 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 530 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 531 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 532 533 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 534 535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL), 536 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), 537 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL), 538 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL), 539 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK), 540 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 543 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 545 546 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 547 }; 548 549 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 550 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 551 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 552 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 553 _HSE_KER}; 554 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 555 _HSE_KER}; 556 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 557 _HSE_KER}; 558 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 559 _HSE_KER}; 560 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 561 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 562 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; 563 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 564 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 565 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 566 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 567 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER}; 568 569 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 570 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), 571 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 572 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 573 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 574 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 575 uart24_parents), 576 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 577 uart35_parents), 578 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 579 uart78_parents), 580 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 581 sdmmc12_parents), 582 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 583 sdmmc3_parents), 584 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), 585 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 586 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 587 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 588 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 589 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 590 }; 591 592 #ifdef STM32MP1_CLOCK_TREE_INIT 593 /* define characteristic of PLL according type */ 594 #define DIVN_MIN 24 595 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 596 [PLL_800] = { 597 .refclk_min = 4, 598 .refclk_max = 16, 599 .divn_max = 99, 600 }, 601 [PLL_1600] = { 602 .refclk_min = 8, 603 .refclk_max = 16, 604 .divn_max = 199, 605 }, 606 }; 607 #endif /* STM32MP1_CLOCK_TREE_INIT */ 608 609 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 610 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 611 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 612 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 613 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 614 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 615 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 616 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 617 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 618 STM32MP1_CLK_PLL(_PLL3, PLL_800, 619 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 620 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 621 _HSI, _HSE, _CSI, _UNKNOWN_ID), 622 STM32MP1_CLK_PLL(_PLL4, PLL_800, 623 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 624 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 625 _HSI, _HSE, _CSI, _I2S_CKIN), 626 }; 627 628 /* Prescaler table lookups for clock computation */ 629 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 630 static const u8 stm32mp1_mcu_div[16] = { 631 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 632 }; 633 634 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/ 635 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 636 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 637 static const u8 stm32mp1_mpu_apbx_div[8] = { 638 0, 1, 2, 3, 4, 4, 4, 4 639 }; 640 641 /* div = /1 /2 /3 /4 */ 642 static const u8 stm32mp1_axi_div[8] = { 643 1, 2, 3, 4, 4, 4, 4, 4 644 }; 645 646 #ifdef DEBUG 647 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { 648 [_HSI] = "HSI", 649 [_HSE] = "HSE", 650 [_CSI] = "CSI", 651 [_LSI] = "LSI", 652 [_LSE] = "LSE", 653 [_I2S_CKIN] = "I2S_CKIN", 654 [_HSI_KER] = "HSI_KER", 655 [_HSE_KER] = "HSE_KER", 656 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 657 [_CSI_KER] = "CSI_KER", 658 [_PLL1_P] = "PLL1_P", 659 [_PLL1_Q] = "PLL1_Q", 660 [_PLL1_R] = "PLL1_R", 661 [_PLL2_P] = "PLL2_P", 662 [_PLL2_Q] = "PLL2_Q", 663 [_PLL2_R] = "PLL2_R", 664 [_PLL3_P] = "PLL3_P", 665 [_PLL3_Q] = "PLL3_Q", 666 [_PLL3_R] = "PLL3_R", 667 [_PLL4_P] = "PLL4_P", 668 [_PLL4_Q] = "PLL4_Q", 669 [_PLL4_R] = "PLL4_R", 670 [_ACLK] = "ACLK", 671 [_PCLK1] = "PCLK1", 672 [_PCLK2] = "PCLK2", 673 [_PCLK3] = "PCLK3", 674 [_PCLK4] = "PCLK4", 675 [_PCLK5] = "PCLK5", 676 [_HCLK6] = "KCLK6", 677 [_HCLK2] = "HCLK2", 678 [_CK_PER] = "CK_PER", 679 [_CK_MPU] = "CK_MPU", 680 [_CK_MCU] = "CK_MCU", 681 [_USB_PHY_48] = "USB_PHY_48" 682 }; 683 684 static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { 685 [_I2C12_SEL] = "I2C12", 686 [_I2C35_SEL] = "I2C35", 687 [_I2C46_SEL] = "I2C46", 688 [_UART6_SEL] = "UART6", 689 [_UART24_SEL] = "UART24", 690 [_UART35_SEL] = "UART35", 691 [_UART78_SEL] = "UART78", 692 [_SDMMC12_SEL] = "SDMMC12", 693 [_SDMMC3_SEL] = "SDMMC3", 694 [_ETH_SEL] = "ETH", 695 [_QSPI_SEL] = "QSPI", 696 [_FMC_SEL] = "FMC", 697 [_USBPHY_SEL] = "USBPHY", 698 [_USBO_SEL] = "USBO", 699 [_STGEN_SEL] = "STGEN" 700 }; 701 #endif 702 703 static const struct stm32mp1_clk_data stm32mp1_data = { 704 .gate = stm32mp1_clk_gate, 705 .sel = stm32mp1_clk_sel, 706 .pll = stm32mp1_clk_pll, 707 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 708 }; 709 710 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) 711 { 712 if (idx >= NB_OSC) { 713 debug("%s: clk id %d not found\n", __func__, idx); 714 return 0; 715 } 716 717 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, 718 (u32)priv->osc[idx], priv->osc[idx] / 1000); 719 720 return priv->osc[idx]; 721 } 722 723 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 724 { 725 const struct stm32mp1_clk_gate *gate = priv->data->gate; 726 int i, nb_clks = priv->data->nb_gate; 727 728 for (i = 0; i < nb_clks; i++) { 729 if (gate[i].index == id) 730 break; 731 } 732 733 if (i == nb_clks) { 734 printf("%s: clk id %d not found\n", __func__, (u32)id); 735 return -EINVAL; 736 } 737 738 return i; 739 } 740 741 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, 742 int i) 743 { 744 const struct stm32mp1_clk_gate *gate = priv->data->gate; 745 746 if (gate[i].sel > _PARENT_SEL_NB) { 747 printf("%s: parents for clk id %d not found\n", 748 __func__, i); 749 return -EINVAL; 750 } 751 752 return gate[i].sel; 753 } 754 755 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, 756 int i) 757 { 758 const struct stm32mp1_clk_gate *gate = priv->data->gate; 759 760 if (gate[i].fixed == _UNKNOWN_ID) 761 return -ENOENT; 762 763 return gate[i].fixed; 764 } 765 766 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 767 unsigned long id) 768 { 769 const struct stm32mp1_clk_sel *sel = priv->data->sel; 770 int i; 771 int s, p; 772 773 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) 774 if (stm32mp1_clks[i][0] == id) 775 return stm32mp1_clks[i][1]; 776 777 i = stm32mp1_clk_get_id(priv, id); 778 if (i < 0) 779 return i; 780 781 p = stm32mp1_clk_get_fixed_parent(priv, i); 782 if (p >= 0 && p < _PARENT_NB) 783 return p; 784 785 s = stm32mp1_clk_get_sel(priv, i); 786 if (s < 0) 787 return s; 788 789 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; 790 791 if (p < sel[s].nb_parent) { 792 #ifdef DEBUG 793 debug("%s: %s clock is the parent %s of clk id %d\n", __func__, 794 stm32mp1_clk_parent_name[sel[s].parent[p]], 795 stm32mp1_clk_parent_sel_name[s], 796 (u32)id); 797 #endif 798 return sel[s].parent[p]; 799 } 800 801 pr_err("%s: no parents defined for clk id %d\n", 802 __func__, (u32)id); 803 804 return -EINVAL; 805 } 806 807 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 808 int pll_id, int div_id) 809 { 810 const struct stm32mp1_clk_pll *pll = priv->data->pll; 811 int divm, divn, divy, src; 812 ulong refclk, dfout; 813 u32 selr, cfgr1, cfgr2, fracr; 814 const u8 shift[_DIV_NB] = { 815 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 816 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 817 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT }; 818 819 debug("%s(%d, %d)\n", __func__, pll_id, div_id); 820 if (div_id > _DIV_NB) 821 return 0; 822 823 selr = readl(priv->base + pll[pll_id].rckxselr); 824 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); 825 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); 826 fracr = readl(priv->base + pll[pll_id].pllxfracr); 827 828 debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n", 829 pll_id, selr, cfgr1, cfgr2, fracr); 830 831 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 832 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 833 divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 834 835 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy); 836 837 src = selr & RCC_SELR_SRC_MASK; 838 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 839 840 debug(" refclk = %d kHz\n", (u32)(refclk / 1000)); 841 842 /* 843 * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2 844 * So same final result than PLL2 et 4 845 * with FRACV : 846 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13) 847 * / (DIVM + 1) * (DIVy + 1) 848 * without FRACV 849 * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1) 850 */ 851 if (fracr & RCC_PLLNFRACR_FRACLE) { 852 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 853 >> RCC_PLLNFRACR_FRACV_SHIFT; 854 dfout = (ulong)lldiv((unsigned long long)refclk * 855 (((divn + 1) << 13) + fracv), 856 ((unsigned long long)(divm + 1) * 857 (divy + 1)) << 13); 858 } else { 859 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1)); 860 } 861 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); 862 863 return dfout; 864 } 865 866 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 867 { 868 u32 reg; 869 ulong clock = 0; 870 871 switch (p) { 872 case _CK_MPU: 873 /* MPU sub system */ 874 reg = readl(priv->base + RCC_MPCKSELR); 875 switch (reg & RCC_SELR_SRC_MASK) { 876 case RCC_MPCKSELR_HSI: 877 clock = stm32mp1_clk_get_fixed(priv, _HSI); 878 break; 879 case RCC_MPCKSELR_HSE: 880 clock = stm32mp1_clk_get_fixed(priv, _HSE); 881 break; 882 case RCC_MPCKSELR_PLL: 883 case RCC_MPCKSELR_PLL_MPUDIV: 884 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 885 if (p == RCC_MPCKSELR_PLL_MPUDIV) { 886 reg = readl(priv->base + RCC_MPCKDIVR); 887 clock /= stm32mp1_mpu_div[reg & 888 RCC_MPUDIV_MASK]; 889 } 890 break; 891 } 892 break; 893 /* AXI sub system */ 894 case _ACLK: 895 case _HCLK2: 896 case _HCLK6: 897 case _PCLK4: 898 case _PCLK5: 899 reg = readl(priv->base + RCC_ASSCKSELR); 900 switch (reg & RCC_SELR_SRC_MASK) { 901 case RCC_ASSCKSELR_HSI: 902 clock = stm32mp1_clk_get_fixed(priv, _HSI); 903 break; 904 case RCC_ASSCKSELR_HSE: 905 clock = stm32mp1_clk_get_fixed(priv, _HSE); 906 break; 907 case RCC_ASSCKSELR_PLL: 908 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 909 break; 910 } 911 912 /* System clock divider */ 913 reg = readl(priv->base + RCC_AXIDIVR); 914 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 915 916 switch (p) { 917 case _PCLK4: 918 reg = readl(priv->base + RCC_APB4DIVR); 919 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 920 break; 921 case _PCLK5: 922 reg = readl(priv->base + RCC_APB5DIVR); 923 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 924 break; 925 default: 926 break; 927 } 928 break; 929 /* MCU sub system */ 930 case _CK_MCU: 931 case _PCLK1: 932 case _PCLK2: 933 case _PCLK3: 934 reg = readl(priv->base + RCC_MSSCKSELR); 935 switch (reg & RCC_SELR_SRC_MASK) { 936 case RCC_MSSCKSELR_HSI: 937 clock = stm32mp1_clk_get_fixed(priv, _HSI); 938 break; 939 case RCC_MSSCKSELR_HSE: 940 clock = stm32mp1_clk_get_fixed(priv, _HSE); 941 break; 942 case RCC_MSSCKSELR_CSI: 943 clock = stm32mp1_clk_get_fixed(priv, _CSI); 944 break; 945 case RCC_MSSCKSELR_PLL: 946 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 947 break; 948 } 949 950 /* MCU clock divider */ 951 reg = readl(priv->base + RCC_MCUDIVR); 952 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 953 954 switch (p) { 955 case _PCLK1: 956 reg = readl(priv->base + RCC_APB1DIVR); 957 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 958 break; 959 case _PCLK2: 960 reg = readl(priv->base + RCC_APB2DIVR); 961 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 962 break; 963 case _PCLK3: 964 reg = readl(priv->base + RCC_APB3DIVR); 965 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 966 break; 967 case _CK_MCU: 968 default: 969 break; 970 } 971 break; 972 case _CK_PER: 973 reg = readl(priv->base + RCC_CPERCKSELR); 974 switch (reg & RCC_SELR_SRC_MASK) { 975 case RCC_CPERCKSELR_HSI: 976 clock = stm32mp1_clk_get_fixed(priv, _HSI); 977 break; 978 case RCC_CPERCKSELR_HSE: 979 clock = stm32mp1_clk_get_fixed(priv, _HSE); 980 break; 981 case RCC_CPERCKSELR_CSI: 982 clock = stm32mp1_clk_get_fixed(priv, _CSI); 983 break; 984 } 985 break; 986 case _HSI: 987 case _HSI_KER: 988 clock = stm32mp1_clk_get_fixed(priv, _HSI); 989 break; 990 case _CSI: 991 case _CSI_KER: 992 clock = stm32mp1_clk_get_fixed(priv, _CSI); 993 break; 994 case _HSE: 995 case _HSE_KER: 996 case _HSE_KER_DIV2: 997 clock = stm32mp1_clk_get_fixed(priv, _HSE); 998 if (p == _HSE_KER_DIV2) 999 clock >>= 1; 1000 break; 1001 case _LSI: 1002 clock = stm32mp1_clk_get_fixed(priv, _LSI); 1003 break; 1004 case _LSE: 1005 clock = stm32mp1_clk_get_fixed(priv, _LSE); 1006 break; 1007 /* PLL */ 1008 case _PLL1_P: 1009 case _PLL1_Q: 1010 case _PLL1_R: 1011 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); 1012 break; 1013 case _PLL2_P: 1014 case _PLL2_Q: 1015 case _PLL2_R: 1016 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); 1017 break; 1018 case _PLL3_P: 1019 case _PLL3_Q: 1020 case _PLL3_R: 1021 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); 1022 break; 1023 case _PLL4_P: 1024 case _PLL4_Q: 1025 case _PLL4_R: 1026 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); 1027 break; 1028 /* other */ 1029 case _USB_PHY_48: 1030 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); 1031 break; 1032 1033 default: 1034 break; 1035 } 1036 1037 debug("%s(%d) clock = %lx : %ld kHz\n", 1038 __func__, p, clock, clock / 1000); 1039 1040 return clock; 1041 } 1042 1043 static int stm32mp1_clk_enable(struct clk *clk) 1044 { 1045 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1046 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1047 int i = stm32mp1_clk_get_id(priv, clk->id); 1048 1049 if (i < 0) 1050 return i; 1051 1052 if (gate[i].set_clr) 1053 writel(BIT(gate[i].bit), priv->base + gate[i].offset); 1054 else 1055 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1056 1057 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); 1058 1059 return 0; 1060 } 1061 1062 static int stm32mp1_clk_disable(struct clk *clk) 1063 { 1064 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1065 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1066 int i = stm32mp1_clk_get_id(priv, clk->id); 1067 1068 if (i < 0) 1069 return i; 1070 1071 if (gate[i].set_clr) 1072 writel(BIT(gate[i].bit), 1073 priv->base + gate[i].offset 1074 + RCC_MP_ENCLRR_OFFSET); 1075 else 1076 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1077 1078 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); 1079 1080 return 0; 1081 } 1082 1083 static ulong stm32mp1_clk_get_rate(struct clk *clk) 1084 { 1085 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1086 int p = stm32mp1_clk_get_parent(priv, clk->id); 1087 ulong rate; 1088 1089 if (p < 0) 1090 return 0; 1091 1092 rate = stm32mp1_clk_get(priv, p); 1093 1094 #ifdef DEBUG 1095 debug("%s: computed rate for id clock %d is %d (parent is %s)\n", 1096 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); 1097 #endif 1098 return rate; 1099 } 1100 1101 #ifdef STM32MP1_CLOCK_TREE_INIT 1102 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, 1103 u32 mask_on) 1104 { 1105 u32 address = rcc + offset; 1106 1107 if (enable) 1108 setbits_le32(address, mask_on); 1109 else 1110 clrbits_le32(address, mask_on); 1111 } 1112 1113 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) 1114 { 1115 if (enable) 1116 setbits_le32(rcc + RCC_OCENSETR, mask_on); 1117 else 1118 setbits_le32(rcc + RCC_OCENCLRR, mask_on); 1119 } 1120 1121 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, 1122 u32 mask_rdy) 1123 { 1124 u32 mask_test = 0; 1125 u32 address = rcc + offset; 1126 u32 val; 1127 int ret; 1128 1129 if (enable) 1130 mask_test = mask_rdy; 1131 1132 ret = readl_poll_timeout(address, val, 1133 (val & mask_rdy) == mask_test, 1134 TIMEOUT_1S); 1135 1136 if (ret) 1137 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", 1138 mask_rdy, address, enable, readl(address)); 1139 1140 return ret; 1141 } 1142 1143 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv) 1144 { 1145 u32 value; 1146 1147 if (bypass) 1148 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 1149 1150 /* 1151 * warning: not recommended to switch directly from "high drive" 1152 * to "medium low drive", and vice-versa. 1153 */ 1154 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) 1155 >> RCC_BDCR_LSEDRV_SHIFT; 1156 1157 while (value != lsedrv) { 1158 if (value > lsedrv) 1159 value--; 1160 else 1161 value++; 1162 1163 clrsetbits_le32(rcc + RCC_BDCR, 1164 RCC_BDCR_LSEDRV_MASK, 1165 value << RCC_BDCR_LSEDRV_SHIFT); 1166 } 1167 1168 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 1169 } 1170 1171 static void stm32mp1_lse_wait(fdt_addr_t rcc) 1172 { 1173 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); 1174 } 1175 1176 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) 1177 { 1178 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 1179 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY); 1180 } 1181 1182 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css) 1183 { 1184 if (bypass) 1185 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1186 1187 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 1188 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); 1189 1190 if (css) 1191 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1192 } 1193 1194 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) 1195 { 1196 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); 1197 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); 1198 } 1199 1200 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable) 1201 { 1202 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 1203 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY); 1204 } 1205 1206 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) 1207 { 1208 u32 address = rcc + RCC_OCRDYR; 1209 u32 val; 1210 int ret; 1211 1212 clrsetbits_le32(rcc + RCC_HSICFGR, 1213 RCC_HSICFGR_HSIDIV_MASK, 1214 RCC_HSICFGR_HSIDIV_MASK & hsidiv); 1215 1216 ret = readl_poll_timeout(address, val, 1217 val & RCC_OCRDYR_HSIDIVRDY, 1218 TIMEOUT_200MS); 1219 if (ret) 1220 pr_err("HSIDIV failed @ 0x%x: 0x%x\n", 1221 address, readl(address)); 1222 1223 return ret; 1224 } 1225 1226 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) 1227 { 1228 u8 hsidiv; 1229 u32 hsidivfreq = MAX_HSI_HZ; 1230 1231 for (hsidiv = 0; hsidiv < 4; hsidiv++, 1232 hsidivfreq = hsidivfreq / 2) 1233 if (hsidivfreq == hsifreq) 1234 break; 1235 1236 if (hsidiv == 4) { 1237 pr_err("clk-hsi frequency invalid"); 1238 return -1; 1239 } 1240 1241 if (hsidiv > 0) 1242 return stm32mp1_set_hsidiv(rcc, hsidiv); 1243 1244 return 0; 1245 } 1246 1247 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) 1248 { 1249 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1250 1251 writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); 1252 } 1253 1254 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) 1255 { 1256 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1257 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1258 u32 val; 1259 int ret; 1260 1261 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY, 1262 TIMEOUT_200MS); 1263 1264 if (ret) { 1265 pr_err("PLL%d start failed @ 0x%x: 0x%x\n", 1266 pll_id, pllxcr, readl(pllxcr)); 1267 return ret; 1268 } 1269 1270 /* start the requested output */ 1271 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1272 1273 return 0; 1274 } 1275 1276 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id) 1277 { 1278 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1279 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1280 u32 val; 1281 1282 /* stop all output */ 1283 clrbits_le32(pllxcr, 1284 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1285 1286 /* stop PLL */ 1287 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON); 1288 1289 /* wait PLL stopped */ 1290 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0, 1291 TIMEOUT_200MS); 1292 } 1293 1294 static void pll_config_output(struct stm32mp1_clk_priv *priv, 1295 int pll_id, u32 *pllcfg) 1296 { 1297 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1298 fdt_addr_t rcc = priv->base; 1299 u32 value; 1300 1301 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) 1302 & RCC_PLLNCFGR2_DIVP_MASK; 1303 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) 1304 & RCC_PLLNCFGR2_DIVQ_MASK; 1305 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) 1306 & RCC_PLLNCFGR2_DIVR_MASK; 1307 writel(value, rcc + pll[pll_id].pllxcfgr2); 1308 } 1309 1310 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, 1311 u32 *pllcfg, u32 fracv) 1312 { 1313 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1314 fdt_addr_t rcc = priv->base; 1315 enum stm32mp1_plltype type = pll[pll_id].plltype; 1316 int src; 1317 ulong refclk; 1318 u8 ifrge = 0; 1319 u32 value; 1320 1321 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; 1322 1323 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1324 (pllcfg[PLLCFG_M] + 1); 1325 1326 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || 1327 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { 1328 debug("invalid refclk = %x\n", (u32)refclk); 1329 return -EINVAL; 1330 } 1331 if (type == PLL_800 && refclk >= 8000000) 1332 ifrge = 1; 1333 1334 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) 1335 & RCC_PLLNCFGR1_DIVN_MASK; 1336 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) 1337 & RCC_PLLNCFGR1_DIVM_MASK; 1338 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) 1339 & RCC_PLLNCFGR1_IFRGE_MASK; 1340 writel(value, rcc + pll[pll_id].pllxcfgr1); 1341 1342 /* fractional configuration: load sigma-delta modulator (SDM) */ 1343 1344 /* Write into FRACV the new fractional value , and FRACLE to 0 */ 1345 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT, 1346 rcc + pll[pll_id].pllxfracr); 1347 1348 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */ 1349 setbits_le32(rcc + pll[pll_id].pllxfracr, 1350 RCC_PLLNFRACR_FRACLE); 1351 1352 pll_config_output(priv, pll_id, pllcfg); 1353 1354 return 0; 1355 } 1356 1357 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) 1358 { 1359 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1360 u32 pllxcsg; 1361 1362 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1363 RCC_PLLNCSGR_MOD_PER_MASK) | 1364 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1365 RCC_PLLNCSGR_INC_STEP_MASK) | 1366 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1367 RCC_PLLNCSGR_SSCG_MODE_MASK); 1368 1369 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); 1370 } 1371 1372 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) 1373 { 1374 u32 address = priv->base + (clksrc >> 4); 1375 u32 val; 1376 int ret; 1377 1378 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); 1379 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, 1380 TIMEOUT_200MS); 1381 if (ret) 1382 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1383 clksrc, address, readl(address)); 1384 1385 return ret; 1386 } 1387 1388 static void stgen_config(struct stm32mp1_clk_priv *priv) 1389 { 1390 int p; 1391 u32 stgenc, cntfid0; 1392 ulong rate; 1393 1394 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); 1395 1396 cntfid0 = readl(stgenc + STGENC_CNTFID0); 1397 p = stm32mp1_clk_get_parent(priv, STGEN_K); 1398 rate = stm32mp1_clk_get(priv, p); 1399 1400 if (cntfid0 != rate) { 1401 pr_debug("System Generic Counter (STGEN) update\n"); 1402 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); 1403 writel(0x0, stgenc + STGENC_CNTCVL); 1404 writel(0x0, stgenc + STGENC_CNTCVU); 1405 writel(rate, stgenc + STGENC_CNTFID0); 1406 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); 1407 1408 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); 1409 1410 /* need to update gd->arch.timer_rate_hz with new frequency */ 1411 timer_init(); 1412 pr_debug("gd->arch.timer_rate_hz = %x\n", 1413 (u32)gd->arch.timer_rate_hz); 1414 pr_debug("Tick = %x\n", (u32)(get_ticks())); 1415 } 1416 } 1417 1418 static int set_clkdiv(unsigned int clkdiv, u32 address) 1419 { 1420 u32 val; 1421 int ret; 1422 1423 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); 1424 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, 1425 TIMEOUT_200MS); 1426 if (ret) 1427 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1428 clkdiv, address, readl(address)); 1429 1430 return ret; 1431 } 1432 1433 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1434 u32 clksrc, u32 clkdiv) 1435 { 1436 u32 address = priv->base + (clksrc >> 4); 1437 1438 /* 1439 * binding clksrc : bit15-4 offset 1440 * bit3: disable 1441 * bit2-0: MCOSEL[2:0] 1442 */ 1443 if (clksrc & 0x8) { 1444 clrbits_le32(address, RCC_MCOCFG_MCOON); 1445 } else { 1446 clrsetbits_le32(address, 1447 RCC_MCOCFG_MCOSRC_MASK, 1448 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1449 clrsetbits_le32(address, 1450 RCC_MCOCFG_MCODIV_MASK, 1451 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1452 setbits_le32(address, RCC_MCOCFG_MCOON); 1453 } 1454 } 1455 1456 static void set_rtcsrc(struct stm32mp1_clk_priv *priv, 1457 unsigned int clksrc, 1458 int lse_css) 1459 { 1460 u32 address = priv->base + RCC_BDCR; 1461 1462 if (readl(address) & RCC_BDCR_RTCCKEN) 1463 goto skip_rtc; 1464 1465 if (clksrc == CLK_RTC_DISABLED) 1466 goto skip_rtc; 1467 1468 clrsetbits_le32(address, 1469 RCC_BDCR_RTCSRC_MASK, 1470 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1471 1472 setbits_le32(address, RCC_BDCR_RTCCKEN); 1473 1474 skip_rtc: 1475 if (lse_css) 1476 setbits_le32(address, RCC_BDCR_LSECSSON); 1477 } 1478 1479 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs) 1480 { 1481 u32 address = priv->base + ((pkcs >> 4) & 0xFFF); 1482 u32 value = pkcs & 0xF; 1483 u32 mask = 0xF; 1484 1485 if (pkcs & BIT(31)) { 1486 mask <<= 4; 1487 value <<= 4; 1488 } 1489 clrsetbits_le32(address, mask, value); 1490 } 1491 1492 static int stm32mp1_clktree(struct udevice *dev) 1493 { 1494 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1495 fdt_addr_t rcc = priv->base; 1496 unsigned int clksrc[CLKSRC_NB]; 1497 unsigned int clkdiv[CLKDIV_NB]; 1498 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1499 ofnode plloff[_PLL_NB]; 1500 int ret; 1501 int i, len; 1502 int lse_css = 0; 1503 const u32 *pkcs_cell; 1504 1505 /* check mandatory field */ 1506 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); 1507 if (ret < 0) { 1508 debug("field st,clksrc invalid: error %d\n", ret); 1509 return -FDT_ERR_NOTFOUND; 1510 } 1511 1512 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); 1513 if (ret < 0) { 1514 debug("field st,clkdiv invalid: error %d\n", ret); 1515 return -FDT_ERR_NOTFOUND; 1516 } 1517 1518 /* check mandatory field in each pll */ 1519 for (i = 0; i < _PLL_NB; i++) { 1520 char name[12]; 1521 1522 sprintf(name, "st,pll@%d", i); 1523 plloff[i] = dev_read_subnode(dev, name); 1524 if (!ofnode_valid(plloff[i])) 1525 continue; 1526 ret = ofnode_read_u32_array(plloff[i], "cfg", 1527 pllcfg[i], PLLCFG_NB); 1528 if (ret < 0) { 1529 debug("field cfg invalid: error %d\n", ret); 1530 return -FDT_ERR_NOTFOUND; 1531 } 1532 } 1533 1534 debug("configuration MCO\n"); 1535 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1536 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1537 1538 debug("switch ON osillator\n"); 1539 /* 1540 * switch ON oscillator found in device-tree, 1541 * HSI already ON after bootrom 1542 */ 1543 if (priv->osc[_LSI]) 1544 stm32mp1_lsi_set(rcc, 1); 1545 1546 if (priv->osc[_LSE]) { 1547 int bypass; 1548 int lsedrv; 1549 struct udevice *dev = priv->osc_dev[_LSE]; 1550 1551 bypass = dev_read_bool(dev, "st,bypass"); 1552 lse_css = dev_read_bool(dev, "st,css"); 1553 lsedrv = dev_read_u32_default(dev, "st,drive", 1554 LSEDRV_MEDIUM_HIGH); 1555 1556 stm32mp1_lse_enable(rcc, bypass, lsedrv); 1557 } 1558 1559 if (priv->osc[_HSE]) { 1560 int bypass, css; 1561 struct udevice *dev = priv->osc_dev[_HSE]; 1562 1563 bypass = dev_read_bool(dev, "st,bypass"); 1564 css = dev_read_bool(dev, "st,css"); 1565 1566 stm32mp1_hse_enable(rcc, bypass, css); 1567 } 1568 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1569 * => switch on CSI even if node is not present in device tree 1570 */ 1571 stm32mp1_csi_set(rcc, 1); 1572 1573 /* come back to HSI */ 1574 debug("come back to HSI\n"); 1575 set_clksrc(priv, CLK_MPU_HSI); 1576 set_clksrc(priv, CLK_AXI_HSI); 1577 set_clksrc(priv, CLK_MCU_HSI); 1578 1579 debug("pll stop\n"); 1580 for (i = 0; i < _PLL_NB; i++) 1581 pll_stop(priv, i); 1582 1583 /* configure HSIDIV */ 1584 debug("configure HSIDIV\n"); 1585 if (priv->osc[_HSI]) { 1586 stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1587 stgen_config(priv); 1588 } 1589 1590 /* select DIV */ 1591 debug("select DIV\n"); 1592 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1593 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR); 1594 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1595 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1596 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1597 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR); 1598 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1599 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1600 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1601 1602 /* no ready bit for RTC */ 1603 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); 1604 1605 /* configure PLLs source */ 1606 debug("configure PLLs source\n"); 1607 set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1608 set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1609 set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1610 1611 /* configure and start PLLs */ 1612 debug("configure PLLs\n"); 1613 for (i = 0; i < _PLL_NB; i++) { 1614 u32 fracv; 1615 u32 csg[PLLCSG_NB]; 1616 1617 debug("configure PLL %d @ %d\n", i, 1618 ofnode_to_offset(plloff[i])); 1619 if (!ofnode_valid(plloff[i])) 1620 continue; 1621 1622 fracv = ofnode_read_u32_default(plloff[i], "frac", 0); 1623 pll_config(priv, i, pllcfg[i], fracv); 1624 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); 1625 if (!ret) { 1626 pll_csg(priv, i, csg); 1627 } else if (ret != -FDT_ERR_NOTFOUND) { 1628 debug("invalid csg node for pll@%d res=%d\n", i, ret); 1629 return ret; 1630 } 1631 pll_start(priv, i); 1632 } 1633 1634 /* wait and start PLLs ouptut when ready */ 1635 for (i = 0; i < _PLL_NB; i++) { 1636 if (!ofnode_valid(plloff[i])) 1637 continue; 1638 debug("output PLL %d\n", i); 1639 pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1640 } 1641 1642 /* wait LSE ready before to use it */ 1643 if (priv->osc[_LSE]) 1644 stm32mp1_lse_wait(rcc); 1645 1646 /* configure with expected clock source */ 1647 debug("CLKSRC\n"); 1648 set_clksrc(priv, clksrc[CLKSRC_MPU]); 1649 set_clksrc(priv, clksrc[CLKSRC_AXI]); 1650 set_clksrc(priv, clksrc[CLKSRC_MCU]); 1651 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1652 1653 /* configure PKCK */ 1654 debug("PKCK\n"); 1655 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); 1656 if (pkcs_cell) { 1657 bool ckper_disabled = false; 1658 1659 for (i = 0; i < len / sizeof(u32); i++) { 1660 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]); 1661 1662 if (pkcs == CLK_CKPER_DISABLED) { 1663 ckper_disabled = true; 1664 continue; 1665 } 1666 pkcs_config(priv, pkcs); 1667 } 1668 /* CKPER is source for some peripheral clock 1669 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1670 * only if previous clock is still ON 1671 * => deactivated CKPER only after switching clock 1672 */ 1673 if (ckper_disabled) 1674 pkcs_config(priv, CLK_CKPER_DISABLED); 1675 } 1676 1677 /* STGEN clock source can change with CLK_STGEN_XXX */ 1678 stgen_config(priv); 1679 1680 debug("oscillator off\n"); 1681 /* switch OFF HSI if not found in device-tree */ 1682 if (!priv->osc[_HSI]) 1683 stm32mp1_hsi_set(rcc, 0); 1684 1685 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1686 clrsetbits_le32(priv->base + RCC_DDRITFCR, 1687 RCC_DDRITFCR_DDRCKMOD_MASK, 1688 RCC_DDRITFCR_DDRCKMOD_SSR << 1689 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1690 1691 return 0; 1692 } 1693 #endif /* STM32MP1_CLOCK_TREE_INIT */ 1694 1695 static void stm32mp1_osc_clk_init(const char *name, 1696 struct stm32mp1_clk_priv *priv, 1697 int index) 1698 { 1699 struct clk clk; 1700 struct udevice *dev = NULL; 1701 1702 priv->osc[index] = 0; 1703 clk.id = 0; 1704 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { 1705 if (clk_request(dev, &clk)) 1706 pr_err("%s request", name); 1707 else 1708 priv->osc[index] = clk_get_rate(&clk); 1709 } 1710 priv->osc_dev[index] = dev; 1711 } 1712 1713 static void stm32mp1_osc_init(struct udevice *dev) 1714 { 1715 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1716 int i; 1717 const char *name[NB_OSC] = { 1718 [_LSI] = "clk-lsi", 1719 [_LSE] = "clk-lse", 1720 [_HSI] = "clk-hsi", 1721 [_HSE] = "clk-hse", 1722 [_CSI] = "clk-csi", 1723 [_I2S_CKIN] = "i2s_ckin", 1724 [_USB_PHY_48] = "ck_usbo_48m"}; 1725 1726 for (i = 0; i < NB_OSC; i++) { 1727 stm32mp1_osc_clk_init(name[i], priv, i); 1728 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); 1729 } 1730 } 1731 1732 static int stm32mp1_clk_probe(struct udevice *dev) 1733 { 1734 int result = 0; 1735 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1736 1737 priv->base = dev_read_addr(dev->parent); 1738 if (priv->base == FDT_ADDR_T_NONE) 1739 return -EINVAL; 1740 1741 priv->data = (void *)&stm32mp1_data; 1742 1743 if (!priv->data->gate || !priv->data->sel || 1744 !priv->data->pll) 1745 return -EINVAL; 1746 1747 stm32mp1_osc_init(dev); 1748 1749 #ifdef STM32MP1_CLOCK_TREE_INIT 1750 /* clock tree init is done only one time, before relocation */ 1751 if (!(gd->flags & GD_FLG_RELOC)) 1752 result = stm32mp1_clktree(dev); 1753 #endif 1754 1755 return result; 1756 } 1757 1758 static const struct clk_ops stm32mp1_clk_ops = { 1759 .enable = stm32mp1_clk_enable, 1760 .disable = stm32mp1_clk_disable, 1761 .get_rate = stm32mp1_clk_get_rate, 1762 }; 1763 1764 static const struct udevice_id stm32mp1_clk_ids[] = { 1765 { .compatible = "st,stm32mp1-rcc-clk" }, 1766 { } 1767 }; 1768 1769 U_BOOT_DRIVER(stm32mp1_clock) = { 1770 .name = "stm32mp1_clk", 1771 .id = UCLASS_CLK, 1772 .of_match = stm32mp1_clk_ids, 1773 .ops = &stm32mp1_clk_ops, 1774 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv), 1775 .probe = stm32mp1_clk_probe, 1776 }; 1777