1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <div64.h>
9 #include <dm.h>
10 #include <regmap.h>
11 #include <spl.h>
12 #include <syscon.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
17
18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
19 /* activate clock tree initialization in the driver */
20 #define STM32MP1_CLOCK_TREE_INIT
21 #endif
22
23 #define MAX_HSI_HZ 64000000
24
25 /* TIMEOUT */
26 #define TIMEOUT_200MS 200000
27 #define TIMEOUT_1S 1000000
28
29 /* STGEN registers */
30 #define STGENC_CNTCR 0x00
31 #define STGENC_CNTSR 0x04
32 #define STGENC_CNTCVL 0x08
33 #define STGENC_CNTCVU 0x0C
34 #define STGENC_CNTFID0 0x20
35
36 #define STGENC_CNTCR_EN BIT(0)
37
38 /* RCC registers */
39 #define RCC_OCENSETR 0x0C
40 #define RCC_OCENCLRR 0x10
41 #define RCC_HSICFGR 0x18
42 #define RCC_MPCKSELR 0x20
43 #define RCC_ASSCKSELR 0x24
44 #define RCC_RCK12SELR 0x28
45 #define RCC_MPCKDIVR 0x2C
46 #define RCC_AXIDIVR 0x30
47 #define RCC_APB4DIVR 0x3C
48 #define RCC_APB5DIVR 0x40
49 #define RCC_RTCDIVR 0x44
50 #define RCC_MSSCKSELR 0x48
51 #define RCC_PLL1CR 0x80
52 #define RCC_PLL1CFGR1 0x84
53 #define RCC_PLL1CFGR2 0x88
54 #define RCC_PLL1FRACR 0x8C
55 #define RCC_PLL1CSGR 0x90
56 #define RCC_PLL2CR 0x94
57 #define RCC_PLL2CFGR1 0x98
58 #define RCC_PLL2CFGR2 0x9C
59 #define RCC_PLL2FRACR 0xA0
60 #define RCC_PLL2CSGR 0xA4
61 #define RCC_I2C46CKSELR 0xC0
62 #define RCC_CPERCKSELR 0xD0
63 #define RCC_STGENCKSELR 0xD4
64 #define RCC_DDRITFCR 0xD8
65 #define RCC_BDCR 0x140
66 #define RCC_RDLSICR 0x144
67 #define RCC_MP_APB4ENSETR 0x200
68 #define RCC_MP_APB5ENSETR 0x208
69 #define RCC_MP_AHB5ENSETR 0x210
70 #define RCC_MP_AHB6ENSETR 0x218
71 #define RCC_OCRDYR 0x808
72 #define RCC_DBGCFGR 0x80C
73 #define RCC_RCK3SELR 0x820
74 #define RCC_RCK4SELR 0x824
75 #define RCC_MCUDIVR 0x830
76 #define RCC_APB1DIVR 0x834
77 #define RCC_APB2DIVR 0x838
78 #define RCC_APB3DIVR 0x83C
79 #define RCC_PLL3CR 0x880
80 #define RCC_PLL3CFGR1 0x884
81 #define RCC_PLL3CFGR2 0x888
82 #define RCC_PLL3FRACR 0x88C
83 #define RCC_PLL3CSGR 0x890
84 #define RCC_PLL4CR 0x894
85 #define RCC_PLL4CFGR1 0x898
86 #define RCC_PLL4CFGR2 0x89C
87 #define RCC_PLL4FRACR 0x8A0
88 #define RCC_PLL4CSGR 0x8A4
89 #define RCC_I2C12CKSELR 0x8C0
90 #define RCC_I2C35CKSELR 0x8C4
91 #define RCC_UART6CKSELR 0x8E4
92 #define RCC_UART24CKSELR 0x8E8
93 #define RCC_UART35CKSELR 0x8EC
94 #define RCC_UART78CKSELR 0x8F0
95 #define RCC_SDMMC12CKSELR 0x8F4
96 #define RCC_SDMMC3CKSELR 0x8F8
97 #define RCC_ETHCKSELR 0x8FC
98 #define RCC_QSPICKSELR 0x900
99 #define RCC_FMCCKSELR 0x904
100 #define RCC_USBCKSELR 0x91C
101 #define RCC_DSICKSELR 0x924
102 #define RCC_ADCCKSELR 0x928
103 #define RCC_MP_APB1ENSETR 0xA00
104 #define RCC_MP_APB2ENSETR 0XA08
105 #define RCC_MP_APB3ENSETR 0xA10
106 #define RCC_MP_AHB2ENSETR 0xA18
107 #define RCC_MP_AHB3ENSETR 0xA20
108 #define RCC_MP_AHB4ENSETR 0xA28
109
110 /* used for most of SELR register */
111 #define RCC_SELR_SRC_MASK GENMASK(2, 0)
112 #define RCC_SELR_SRCRDY BIT(31)
113
114 /* Values of RCC_MPCKSELR register */
115 #define RCC_MPCKSELR_HSI 0
116 #define RCC_MPCKSELR_HSE 1
117 #define RCC_MPCKSELR_PLL 2
118 #define RCC_MPCKSELR_PLL_MPUDIV 3
119
120 /* Values of RCC_ASSCKSELR register */
121 #define RCC_ASSCKSELR_HSI 0
122 #define RCC_ASSCKSELR_HSE 1
123 #define RCC_ASSCKSELR_PLL 2
124
125 /* Values of RCC_MSSCKSELR register */
126 #define RCC_MSSCKSELR_HSI 0
127 #define RCC_MSSCKSELR_HSE 1
128 #define RCC_MSSCKSELR_CSI 2
129 #define RCC_MSSCKSELR_PLL 3
130
131 /* Values of RCC_CPERCKSELR register */
132 #define RCC_CPERCKSELR_HSI 0
133 #define RCC_CPERCKSELR_CSI 1
134 #define RCC_CPERCKSELR_HSE 2
135
136 /* used for most of DIVR register : max div for RTC */
137 #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
138 #define RCC_DIVR_DIVRDY BIT(31)
139
140 /* Masks for specific DIVR registers */
141 #define RCC_APBXDIV_MASK GENMASK(2, 0)
142 #define RCC_MPUDIV_MASK GENMASK(2, 0)
143 #define RCC_AXIDIV_MASK GENMASK(2, 0)
144 #define RCC_MCUDIV_MASK GENMASK(3, 0)
145
146 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
147 #define RCC_MP_ENCLRR_OFFSET 4
148
149 /* Fields of RCC_BDCR register */
150 #define RCC_BDCR_LSEON BIT(0)
151 #define RCC_BDCR_LSEBYP BIT(1)
152 #define RCC_BDCR_LSERDY BIT(2)
153 #define RCC_BDCR_DIGBYP BIT(3)
154 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
155 #define RCC_BDCR_LSEDRV_SHIFT 4
156 #define RCC_BDCR_LSECSSON BIT(8)
157 #define RCC_BDCR_RTCCKEN BIT(20)
158 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
159 #define RCC_BDCR_RTCSRC_SHIFT 16
160
161 /* Fields of RCC_RDLSICR register */
162 #define RCC_RDLSICR_LSION BIT(0)
163 #define RCC_RDLSICR_LSIRDY BIT(1)
164
165 /* used for ALL PLLNCR registers */
166 #define RCC_PLLNCR_PLLON BIT(0)
167 #define RCC_PLLNCR_PLLRDY BIT(1)
168 #define RCC_PLLNCR_SSCG_CTRL BIT(2)
169 #define RCC_PLLNCR_DIVPEN BIT(4)
170 #define RCC_PLLNCR_DIVQEN BIT(5)
171 #define RCC_PLLNCR_DIVREN BIT(6)
172 #define RCC_PLLNCR_DIVEN_SHIFT 4
173
174 /* used for ALL PLLNCFGR1 registers */
175 #define RCC_PLLNCFGR1_DIVM_SHIFT 16
176 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
177 #define RCC_PLLNCFGR1_DIVN_SHIFT 0
178 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
179 /* only for PLL3 and PLL4 */
180 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
181 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
182
183 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
184 #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
185 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
186 #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
187 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
188 #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
189 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
190 #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
191 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
192
193 /* used for ALL PLLNFRACR registers */
194 #define RCC_PLLNFRACR_FRACV_SHIFT 3
195 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
196 #define RCC_PLLNFRACR_FRACLE BIT(16)
197
198 /* used for ALL PLLNCSGR registers */
199 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
200 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
201 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
202 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
203 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
204 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
205
206 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
207 #define RCC_OCENR_HSION BIT(0)
208 #define RCC_OCENR_CSION BIT(4)
209 #define RCC_OCENR_DIGBYP BIT(7)
210 #define RCC_OCENR_HSEON BIT(8)
211 #define RCC_OCENR_HSEBYP BIT(10)
212 #define RCC_OCENR_HSECSSON BIT(11)
213
214 /* Fields of RCC_OCRDYR register */
215 #define RCC_OCRDYR_HSIRDY BIT(0)
216 #define RCC_OCRDYR_HSIDIVRDY BIT(2)
217 #define RCC_OCRDYR_CSIRDY BIT(4)
218 #define RCC_OCRDYR_HSERDY BIT(8)
219
220 /* Fields of DDRITFCR register */
221 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
222 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
223 #define RCC_DDRITFCR_DDRCKMOD_SSR 0
224
225 /* Fields of RCC_HSICFGR register */
226 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
227
228 /* used for MCO related operations */
229 #define RCC_MCOCFG_MCOON BIT(12)
230 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
231 #define RCC_MCOCFG_MCODIV_SHIFT 4
232 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
233
234 enum stm32mp1_parent_id {
235 /*
236 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
237 * they are used as index in osc[] as entry point
238 */
239 _HSI,
240 _HSE,
241 _CSI,
242 _LSI,
243 _LSE,
244 _I2S_CKIN,
245 NB_OSC,
246
247 /* other parent source */
248 _HSI_KER = NB_OSC,
249 _HSE_KER,
250 _HSE_KER_DIV2,
251 _CSI_KER,
252 _PLL1_P,
253 _PLL1_Q,
254 _PLL1_R,
255 _PLL2_P,
256 _PLL2_Q,
257 _PLL2_R,
258 _PLL3_P,
259 _PLL3_Q,
260 _PLL3_R,
261 _PLL4_P,
262 _PLL4_Q,
263 _PLL4_R,
264 _ACLK,
265 _PCLK1,
266 _PCLK2,
267 _PCLK3,
268 _PCLK4,
269 _PCLK5,
270 _HCLK6,
271 _HCLK2,
272 _CK_PER,
273 _CK_MPU,
274 _CK_MCU,
275 _DSI_PHY,
276 _USB_PHY_48,
277 _PARENT_NB,
278 _UNKNOWN_ID = 0xff,
279 };
280
281 enum stm32mp1_parent_sel {
282 _I2C12_SEL,
283 _I2C35_SEL,
284 _I2C46_SEL,
285 _UART6_SEL,
286 _UART24_SEL,
287 _UART35_SEL,
288 _UART78_SEL,
289 _SDMMC12_SEL,
290 _SDMMC3_SEL,
291 _ETH_SEL,
292 _QSPI_SEL,
293 _FMC_SEL,
294 _USBPHY_SEL,
295 _USBO_SEL,
296 _STGEN_SEL,
297 _DSI_SEL,
298 _ADC12_SEL,
299 _PARENT_SEL_NB,
300 _UNKNOWN_SEL = 0xff,
301 };
302
303 enum stm32mp1_pll_id {
304 _PLL1,
305 _PLL2,
306 _PLL3,
307 _PLL4,
308 _PLL_NB
309 };
310
311 enum stm32mp1_div_id {
312 _DIV_P,
313 _DIV_Q,
314 _DIV_R,
315 _DIV_NB,
316 };
317
318 enum stm32mp1_clksrc_id {
319 CLKSRC_MPU,
320 CLKSRC_AXI,
321 CLKSRC_MCU,
322 CLKSRC_PLL12,
323 CLKSRC_PLL3,
324 CLKSRC_PLL4,
325 CLKSRC_RTC,
326 CLKSRC_MCO1,
327 CLKSRC_MCO2,
328 CLKSRC_NB
329 };
330
331 enum stm32mp1_clkdiv_id {
332 CLKDIV_MPU,
333 CLKDIV_AXI,
334 CLKDIV_MCU,
335 CLKDIV_APB1,
336 CLKDIV_APB2,
337 CLKDIV_APB3,
338 CLKDIV_APB4,
339 CLKDIV_APB5,
340 CLKDIV_RTC,
341 CLKDIV_MCO1,
342 CLKDIV_MCO2,
343 CLKDIV_NB
344 };
345
346 enum stm32mp1_pllcfg {
347 PLLCFG_M,
348 PLLCFG_N,
349 PLLCFG_P,
350 PLLCFG_Q,
351 PLLCFG_R,
352 PLLCFG_O,
353 PLLCFG_NB
354 };
355
356 enum stm32mp1_pllcsg {
357 PLLCSG_MOD_PER,
358 PLLCSG_INC_STEP,
359 PLLCSG_SSCG_MODE,
360 PLLCSG_NB
361 };
362
363 enum stm32mp1_plltype {
364 PLL_800,
365 PLL_1600,
366 PLL_TYPE_NB
367 };
368
369 struct stm32mp1_pll {
370 u8 refclk_min;
371 u8 refclk_max;
372 u8 divn_max;
373 };
374
375 struct stm32mp1_clk_gate {
376 u16 offset;
377 u8 bit;
378 u8 index;
379 u8 set_clr;
380 u8 sel;
381 u8 fixed;
382 };
383
384 struct stm32mp1_clk_sel {
385 u16 offset;
386 u8 src;
387 u8 msk;
388 u8 nb_parent;
389 const u8 *parent;
390 };
391
392 #define REFCLK_SIZE 4
393 struct stm32mp1_clk_pll {
394 enum stm32mp1_plltype plltype;
395 u16 rckxselr;
396 u16 pllxcfgr1;
397 u16 pllxcfgr2;
398 u16 pllxfracr;
399 u16 pllxcr;
400 u16 pllxcsgr;
401 u8 refclk[REFCLK_SIZE];
402 };
403
404 struct stm32mp1_clk_data {
405 const struct stm32mp1_clk_gate *gate;
406 const struct stm32mp1_clk_sel *sel;
407 const struct stm32mp1_clk_pll *pll;
408 const int nb_gate;
409 };
410
411 struct stm32mp1_clk_priv {
412 fdt_addr_t base;
413 const struct stm32mp1_clk_data *data;
414 ulong osc[NB_OSC];
415 struct udevice *osc_dev[NB_OSC];
416 };
417
418 #define STM32MP1_CLK(off, b, idx, s) \
419 { \
420 .offset = (off), \
421 .bit = (b), \
422 .index = (idx), \
423 .set_clr = 0, \
424 .sel = (s), \
425 .fixed = _UNKNOWN_ID, \
426 }
427
428 #define STM32MP1_CLK_F(off, b, idx, f) \
429 { \
430 .offset = (off), \
431 .bit = (b), \
432 .index = (idx), \
433 .set_clr = 0, \
434 .sel = _UNKNOWN_SEL, \
435 .fixed = (f), \
436 }
437
438 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
439 { \
440 .offset = (off), \
441 .bit = (b), \
442 .index = (idx), \
443 .set_clr = 1, \
444 .sel = (s), \
445 .fixed = _UNKNOWN_ID, \
446 }
447
448 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
449 { \
450 .offset = (off), \
451 .bit = (b), \
452 .index = (idx), \
453 .set_clr = 1, \
454 .sel = _UNKNOWN_SEL, \
455 .fixed = (f), \
456 }
457
458 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
459 [(idx)] = { \
460 .offset = (off), \
461 .src = (s), \
462 .msk = (m), \
463 .parent = (p), \
464 .nb_parent = ARRAY_SIZE((p)) \
465 }
466
467 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
468 p1, p2, p3, p4) \
469 [(idx)] = { \
470 .plltype = (type), \
471 .rckxselr = (off1), \
472 .pllxcfgr1 = (off2), \
473 .pllxcfgr2 = (off3), \
474 .pllxfracr = (off4), \
475 .pllxcr = (off5), \
476 .pllxcsgr = (off6), \
477 .refclk[0] = (p1), \
478 .refclk[1] = (p2), \
479 .refclk[2] = (p3), \
480 .refclk[3] = (p4), \
481 }
482
483 static const u8 stm32mp1_clks[][2] = {
484 {CK_PER, _CK_PER},
485 {CK_MPU, _CK_MPU},
486 {CK_AXI, _ACLK},
487 {CK_MCU, _CK_MCU},
488 {CK_HSE, _HSE},
489 {CK_CSI, _CSI},
490 {CK_LSI, _LSI},
491 {CK_LSE, _LSE},
492 {CK_HSI, _HSI},
493 {CK_HSE_DIV2, _HSE_KER_DIV2},
494 };
495
496 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
497 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
498 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
499 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
500 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
501 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
502 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
503 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
504 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
505 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
506 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
507 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
508
509 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
510 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
518 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
519
520 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
521
522 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
523
524 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
525 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
526 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
527 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
528 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
529 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
530
531 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
532 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
533
534 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
536 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
537 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
538
539 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
540 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
541
542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
543 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
546 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
548 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
550 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
552 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
553
554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
555
556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
559 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
560 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
561 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
562 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
563 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
564 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
565
566 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
567 };
568
569 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
570 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
571 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
572 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
573 _HSE_KER};
574 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
575 _HSE_KER};
576 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
577 _HSE_KER};
578 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
579 _HSE_KER};
580 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
581 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
582 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
583 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
584 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
585 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
586 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
587 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
588 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
589 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
590
591 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
592 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
593 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
594 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
595 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
596 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
597 uart24_parents),
598 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
599 uart35_parents),
600 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
601 uart78_parents),
602 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
603 sdmmc12_parents),
604 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
605 sdmmc3_parents),
606 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
607 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
608 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
609 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
610 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
611 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
612 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
613 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
614 };
615
616 #ifdef STM32MP1_CLOCK_TREE_INIT
617 /* define characteristic of PLL according type */
618 #define DIVN_MIN 24
619 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
620 [PLL_800] = {
621 .refclk_min = 4,
622 .refclk_max = 16,
623 .divn_max = 99,
624 },
625 [PLL_1600] = {
626 .refclk_min = 8,
627 .refclk_max = 16,
628 .divn_max = 199,
629 },
630 };
631 #endif /* STM32MP1_CLOCK_TREE_INIT */
632
633 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
634 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
635 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
636 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
637 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
638 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
639 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
640 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
641 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
642 STM32MP1_CLK_PLL(_PLL3, PLL_800,
643 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
644 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
645 _HSI, _HSE, _CSI, _UNKNOWN_ID),
646 STM32MP1_CLK_PLL(_PLL4, PLL_800,
647 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
648 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
649 _HSI, _HSE, _CSI, _I2S_CKIN),
650 };
651
652 /* Prescaler table lookups for clock computation */
653 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
654 static const u8 stm32mp1_mcu_div[16] = {
655 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
656 };
657
658 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
659 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
660 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
661 static const u8 stm32mp1_mpu_apbx_div[8] = {
662 0, 1, 2, 3, 4, 4, 4, 4
663 };
664
665 /* div = /1 /2 /3 /4 */
666 static const u8 stm32mp1_axi_div[8] = {
667 1, 2, 3, 4, 4, 4, 4, 4
668 };
669
670 static const __maybe_unused
671 char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
672 [_HSI] = "HSI",
673 [_HSE] = "HSE",
674 [_CSI] = "CSI",
675 [_LSI] = "LSI",
676 [_LSE] = "LSE",
677 [_I2S_CKIN] = "I2S_CKIN",
678 [_HSI_KER] = "HSI_KER",
679 [_HSE_KER] = "HSE_KER",
680 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
681 [_CSI_KER] = "CSI_KER",
682 [_PLL1_P] = "PLL1_P",
683 [_PLL1_Q] = "PLL1_Q",
684 [_PLL1_R] = "PLL1_R",
685 [_PLL2_P] = "PLL2_P",
686 [_PLL2_Q] = "PLL2_Q",
687 [_PLL2_R] = "PLL2_R",
688 [_PLL3_P] = "PLL3_P",
689 [_PLL3_Q] = "PLL3_Q",
690 [_PLL3_R] = "PLL3_R",
691 [_PLL4_P] = "PLL4_P",
692 [_PLL4_Q] = "PLL4_Q",
693 [_PLL4_R] = "PLL4_R",
694 [_ACLK] = "ACLK",
695 [_PCLK1] = "PCLK1",
696 [_PCLK2] = "PCLK2",
697 [_PCLK3] = "PCLK3",
698 [_PCLK4] = "PCLK4",
699 [_PCLK5] = "PCLK5",
700 [_HCLK6] = "KCLK6",
701 [_HCLK2] = "HCLK2",
702 [_CK_PER] = "CK_PER",
703 [_CK_MPU] = "CK_MPU",
704 [_CK_MCU] = "CK_MCU",
705 [_USB_PHY_48] = "USB_PHY_48",
706 [_DSI_PHY] = "DSI_PHY_PLL",
707 };
708
709 static const __maybe_unused
710 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
711 [_I2C12_SEL] = "I2C12",
712 [_I2C35_SEL] = "I2C35",
713 [_I2C46_SEL] = "I2C46",
714 [_UART6_SEL] = "UART6",
715 [_UART24_SEL] = "UART24",
716 [_UART35_SEL] = "UART35",
717 [_UART78_SEL] = "UART78",
718 [_SDMMC12_SEL] = "SDMMC12",
719 [_SDMMC3_SEL] = "SDMMC3",
720 [_ETH_SEL] = "ETH",
721 [_QSPI_SEL] = "QSPI",
722 [_FMC_SEL] = "FMC",
723 [_USBPHY_SEL] = "USBPHY",
724 [_USBO_SEL] = "USBO",
725 [_STGEN_SEL] = "STGEN",
726 [_DSI_SEL] = "DSI",
727 [_ADC12_SEL] = "ADC12",
728 };
729
730 static const struct stm32mp1_clk_data stm32mp1_data = {
731 .gate = stm32mp1_clk_gate,
732 .sel = stm32mp1_clk_sel,
733 .pll = stm32mp1_clk_pll,
734 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
735 };
736
stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv * priv,int idx)737 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
738 {
739 if (idx >= NB_OSC) {
740 debug("%s: clk id %d not found\n", __func__, idx);
741 return 0;
742 }
743
744 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
745 (u32)priv->osc[idx], priv->osc[idx] / 1000);
746
747 return priv->osc[idx];
748 }
749
stm32mp1_clk_get_id(struct stm32mp1_clk_priv * priv,unsigned long id)750 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
751 {
752 const struct stm32mp1_clk_gate *gate = priv->data->gate;
753 int i, nb_clks = priv->data->nb_gate;
754
755 for (i = 0; i < nb_clks; i++) {
756 if (gate[i].index == id)
757 break;
758 }
759
760 if (i == nb_clks) {
761 printf("%s: clk id %d not found\n", __func__, (u32)id);
762 return -EINVAL;
763 }
764
765 return i;
766 }
767
stm32mp1_clk_get_sel(struct stm32mp1_clk_priv * priv,int i)768 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
769 int i)
770 {
771 const struct stm32mp1_clk_gate *gate = priv->data->gate;
772
773 if (gate[i].sel > _PARENT_SEL_NB) {
774 printf("%s: parents for clk id %d not found\n",
775 __func__, i);
776 return -EINVAL;
777 }
778
779 return gate[i].sel;
780 }
781
stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv * priv,int i)782 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
783 int i)
784 {
785 const struct stm32mp1_clk_gate *gate = priv->data->gate;
786
787 if (gate[i].fixed == _UNKNOWN_ID)
788 return -ENOENT;
789
790 return gate[i].fixed;
791 }
792
stm32mp1_clk_get_parent(struct stm32mp1_clk_priv * priv,unsigned long id)793 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
794 unsigned long id)
795 {
796 const struct stm32mp1_clk_sel *sel = priv->data->sel;
797 int i;
798 int s, p;
799
800 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
801 if (stm32mp1_clks[i][0] == id)
802 return stm32mp1_clks[i][1];
803
804 i = stm32mp1_clk_get_id(priv, id);
805 if (i < 0)
806 return i;
807
808 p = stm32mp1_clk_get_fixed_parent(priv, i);
809 if (p >= 0 && p < _PARENT_NB)
810 return p;
811
812 s = stm32mp1_clk_get_sel(priv, i);
813 if (s < 0)
814 return s;
815
816 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
817
818 if (p < sel[s].nb_parent) {
819 #ifdef DEBUG
820 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
821 stm32mp1_clk_parent_name[sel[s].parent[p]],
822 stm32mp1_clk_parent_sel_name[s],
823 (u32)id);
824 #endif
825 return sel[s].parent[p];
826 }
827
828 pr_err("%s: no parents defined for clk id %d\n",
829 __func__, (u32)id);
830
831 return -EINVAL;
832 }
833
pll_get_fref_ck(struct stm32mp1_clk_priv * priv,int pll_id)834 static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
835 int pll_id)
836 {
837 const struct stm32mp1_clk_pll *pll = priv->data->pll;
838 u32 selr;
839 int src;
840 ulong refclk;
841
842 /* Get current refclk */
843 selr = readl(priv->base + pll[pll_id].rckxselr);
844 src = selr & RCC_SELR_SRC_MASK;
845
846 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
847 debug("PLL%d : selr=%x refclk = %d kHz\n",
848 pll_id, selr, (u32)(refclk / 1000));
849
850 return refclk;
851 }
852
853 /*
854 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
855 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
856 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
857 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
858 */
pll_get_fvco(struct stm32mp1_clk_priv * priv,int pll_id)859 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
860 int pll_id)
861 {
862 const struct stm32mp1_clk_pll *pll = priv->data->pll;
863 int divm, divn;
864 ulong refclk, fvco;
865 u32 cfgr1, fracr;
866
867 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
868 fracr = readl(priv->base + pll[pll_id].pllxfracr);
869
870 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
871 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
872
873 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
874 pll_id, cfgr1, fracr, divn, divm);
875
876 refclk = pll_get_fref_ck(priv, pll_id);
877
878 /* with FRACV :
879 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
880 * without FRACV
881 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
882 */
883 if (fracr & RCC_PLLNFRACR_FRACLE) {
884 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
885 >> RCC_PLLNFRACR_FRACV_SHIFT;
886 fvco = (ulong)lldiv((unsigned long long)refclk *
887 (((divn + 1) << 13) + fracv),
888 ((unsigned long long)(divm + 1)) << 13);
889 } else {
890 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
891 }
892 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
893
894 return fvco;
895 }
896
stm32mp1_read_pll_freq(struct stm32mp1_clk_priv * priv,int pll_id,int div_id)897 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
898 int pll_id, int div_id)
899 {
900 const struct stm32mp1_clk_pll *pll = priv->data->pll;
901 int divy;
902 ulong dfout;
903 u32 cfgr2;
904
905 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
906 if (div_id >= _DIV_NB)
907 return 0;
908
909 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
910 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
911
912 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
913
914 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
915 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
916
917 return dfout;
918 }
919
stm32mp1_clk_get(struct stm32mp1_clk_priv * priv,int p)920 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
921 {
922 u32 reg;
923 ulong clock = 0;
924
925 switch (p) {
926 case _CK_MPU:
927 /* MPU sub system */
928 reg = readl(priv->base + RCC_MPCKSELR);
929 switch (reg & RCC_SELR_SRC_MASK) {
930 case RCC_MPCKSELR_HSI:
931 clock = stm32mp1_clk_get_fixed(priv, _HSI);
932 break;
933 case RCC_MPCKSELR_HSE:
934 clock = stm32mp1_clk_get_fixed(priv, _HSE);
935 break;
936 case RCC_MPCKSELR_PLL:
937 case RCC_MPCKSELR_PLL_MPUDIV:
938 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
939 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
940 reg = readl(priv->base + RCC_MPCKDIVR);
941 clock /= stm32mp1_mpu_div[reg &
942 RCC_MPUDIV_MASK];
943 }
944 break;
945 }
946 break;
947 /* AXI sub system */
948 case _ACLK:
949 case _HCLK2:
950 case _HCLK6:
951 case _PCLK4:
952 case _PCLK5:
953 reg = readl(priv->base + RCC_ASSCKSELR);
954 switch (reg & RCC_SELR_SRC_MASK) {
955 case RCC_ASSCKSELR_HSI:
956 clock = stm32mp1_clk_get_fixed(priv, _HSI);
957 break;
958 case RCC_ASSCKSELR_HSE:
959 clock = stm32mp1_clk_get_fixed(priv, _HSE);
960 break;
961 case RCC_ASSCKSELR_PLL:
962 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
963 break;
964 }
965
966 /* System clock divider */
967 reg = readl(priv->base + RCC_AXIDIVR);
968 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
969
970 switch (p) {
971 case _PCLK4:
972 reg = readl(priv->base + RCC_APB4DIVR);
973 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
974 break;
975 case _PCLK5:
976 reg = readl(priv->base + RCC_APB5DIVR);
977 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
978 break;
979 default:
980 break;
981 }
982 break;
983 /* MCU sub system */
984 case _CK_MCU:
985 case _PCLK1:
986 case _PCLK2:
987 case _PCLK3:
988 reg = readl(priv->base + RCC_MSSCKSELR);
989 switch (reg & RCC_SELR_SRC_MASK) {
990 case RCC_MSSCKSELR_HSI:
991 clock = stm32mp1_clk_get_fixed(priv, _HSI);
992 break;
993 case RCC_MSSCKSELR_HSE:
994 clock = stm32mp1_clk_get_fixed(priv, _HSE);
995 break;
996 case RCC_MSSCKSELR_CSI:
997 clock = stm32mp1_clk_get_fixed(priv, _CSI);
998 break;
999 case RCC_MSSCKSELR_PLL:
1000 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1001 break;
1002 }
1003
1004 /* MCU clock divider */
1005 reg = readl(priv->base + RCC_MCUDIVR);
1006 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1007
1008 switch (p) {
1009 case _PCLK1:
1010 reg = readl(priv->base + RCC_APB1DIVR);
1011 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1012 break;
1013 case _PCLK2:
1014 reg = readl(priv->base + RCC_APB2DIVR);
1015 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1016 break;
1017 case _PCLK3:
1018 reg = readl(priv->base + RCC_APB3DIVR);
1019 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1020 break;
1021 case _CK_MCU:
1022 default:
1023 break;
1024 }
1025 break;
1026 case _CK_PER:
1027 reg = readl(priv->base + RCC_CPERCKSELR);
1028 switch (reg & RCC_SELR_SRC_MASK) {
1029 case RCC_CPERCKSELR_HSI:
1030 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1031 break;
1032 case RCC_CPERCKSELR_HSE:
1033 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1034 break;
1035 case RCC_CPERCKSELR_CSI:
1036 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1037 break;
1038 }
1039 break;
1040 case _HSI:
1041 case _HSI_KER:
1042 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1043 break;
1044 case _CSI:
1045 case _CSI_KER:
1046 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1047 break;
1048 case _HSE:
1049 case _HSE_KER:
1050 case _HSE_KER_DIV2:
1051 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1052 if (p == _HSE_KER_DIV2)
1053 clock >>= 1;
1054 break;
1055 case _LSI:
1056 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1057 break;
1058 case _LSE:
1059 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1060 break;
1061 /* PLL */
1062 case _PLL1_P:
1063 case _PLL1_Q:
1064 case _PLL1_R:
1065 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1066 break;
1067 case _PLL2_P:
1068 case _PLL2_Q:
1069 case _PLL2_R:
1070 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1071 break;
1072 case _PLL3_P:
1073 case _PLL3_Q:
1074 case _PLL3_R:
1075 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1076 break;
1077 case _PLL4_P:
1078 case _PLL4_Q:
1079 case _PLL4_R:
1080 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1081 break;
1082 /* other */
1083 case _USB_PHY_48:
1084 clock = 48000000;
1085 break;
1086 case _DSI_PHY:
1087 {
1088 struct clk clk;
1089 struct udevice *dev = NULL;
1090
1091 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1092 &dev)) {
1093 if (clk_request(dev, &clk)) {
1094 pr_err("ck_dsi_phy request");
1095 } else {
1096 clk.id = 0;
1097 clock = clk_get_rate(&clk);
1098 }
1099 }
1100 break;
1101 }
1102 default:
1103 break;
1104 }
1105
1106 debug("%s(%d) clock = %lx : %ld kHz\n",
1107 __func__, p, clock, clock / 1000);
1108
1109 return clock;
1110 }
1111
stm32mp1_clk_enable(struct clk * clk)1112 static int stm32mp1_clk_enable(struct clk *clk)
1113 {
1114 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1115 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1116 int i = stm32mp1_clk_get_id(priv, clk->id);
1117
1118 if (i < 0)
1119 return i;
1120
1121 if (gate[i].set_clr)
1122 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1123 else
1124 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1125
1126 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1127
1128 return 0;
1129 }
1130
stm32mp1_clk_disable(struct clk * clk)1131 static int stm32mp1_clk_disable(struct clk *clk)
1132 {
1133 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1134 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1135 int i = stm32mp1_clk_get_id(priv, clk->id);
1136
1137 if (i < 0)
1138 return i;
1139
1140 if (gate[i].set_clr)
1141 writel(BIT(gate[i].bit),
1142 priv->base + gate[i].offset
1143 + RCC_MP_ENCLRR_OFFSET);
1144 else
1145 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1146
1147 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1148
1149 return 0;
1150 }
1151
stm32mp1_clk_get_rate(struct clk * clk)1152 static ulong stm32mp1_clk_get_rate(struct clk *clk)
1153 {
1154 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1155 int p = stm32mp1_clk_get_parent(priv, clk->id);
1156 ulong rate;
1157
1158 if (p < 0)
1159 return 0;
1160
1161 rate = stm32mp1_clk_get(priv, p);
1162
1163 #ifdef DEBUG
1164 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1165 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1166 #endif
1167 return rate;
1168 }
1169
1170 #ifdef STM32MP1_CLOCK_TREE_INIT
stm32mp1_ls_osc_set(int enable,fdt_addr_t rcc,u32 offset,u32 mask_on)1171 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1172 u32 mask_on)
1173 {
1174 u32 address = rcc + offset;
1175
1176 if (enable)
1177 setbits_le32(address, mask_on);
1178 else
1179 clrbits_le32(address, mask_on);
1180 }
1181
stm32mp1_hs_ocs_set(int enable,fdt_addr_t rcc,u32 mask_on)1182 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1183 {
1184 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
1185 }
1186
stm32mp1_osc_wait(int enable,fdt_addr_t rcc,u32 offset,u32 mask_rdy)1187 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1188 u32 mask_rdy)
1189 {
1190 u32 mask_test = 0;
1191 u32 address = rcc + offset;
1192 u32 val;
1193 int ret;
1194
1195 if (enable)
1196 mask_test = mask_rdy;
1197
1198 ret = readl_poll_timeout(address, val,
1199 (val & mask_rdy) == mask_test,
1200 TIMEOUT_1S);
1201
1202 if (ret)
1203 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1204 mask_rdy, address, enable, readl(address));
1205
1206 return ret;
1207 }
1208
stm32mp1_lse_enable(fdt_addr_t rcc,int bypass,int digbyp,int lsedrv)1209 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
1210 int lsedrv)
1211 {
1212 u32 value;
1213
1214 if (digbyp)
1215 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1216
1217 if (bypass || digbyp)
1218 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1219
1220 /*
1221 * warning: not recommended to switch directly from "high drive"
1222 * to "medium low drive", and vice-versa.
1223 */
1224 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1225 >> RCC_BDCR_LSEDRV_SHIFT;
1226
1227 while (value != lsedrv) {
1228 if (value > lsedrv)
1229 value--;
1230 else
1231 value++;
1232
1233 clrsetbits_le32(rcc + RCC_BDCR,
1234 RCC_BDCR_LSEDRV_MASK,
1235 value << RCC_BDCR_LSEDRV_SHIFT);
1236 }
1237
1238 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1239 }
1240
stm32mp1_lse_wait(fdt_addr_t rcc)1241 static void stm32mp1_lse_wait(fdt_addr_t rcc)
1242 {
1243 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1244 }
1245
stm32mp1_lsi_set(fdt_addr_t rcc,int enable)1246 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1247 {
1248 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1249 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1250 }
1251
stm32mp1_hse_enable(fdt_addr_t rcc,int bypass,int digbyp,int css)1252 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
1253 {
1254 if (digbyp)
1255 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
1256 if (bypass || digbyp)
1257 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
1258
1259 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1260 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1261
1262 if (css)
1263 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
1264 }
1265
stm32mp1_csi_set(fdt_addr_t rcc,int enable)1266 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1267 {
1268 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
1269 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1270 }
1271
stm32mp1_hsi_set(fdt_addr_t rcc,int enable)1272 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1273 {
1274 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1275 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1276 }
1277
stm32mp1_set_hsidiv(fdt_addr_t rcc,u8 hsidiv)1278 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1279 {
1280 u32 address = rcc + RCC_OCRDYR;
1281 u32 val;
1282 int ret;
1283
1284 clrsetbits_le32(rcc + RCC_HSICFGR,
1285 RCC_HSICFGR_HSIDIV_MASK,
1286 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1287
1288 ret = readl_poll_timeout(address, val,
1289 val & RCC_OCRDYR_HSIDIVRDY,
1290 TIMEOUT_200MS);
1291 if (ret)
1292 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1293 address, readl(address));
1294
1295 return ret;
1296 }
1297
stm32mp1_hsidiv(fdt_addr_t rcc,ulong hsifreq)1298 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1299 {
1300 u8 hsidiv;
1301 u32 hsidivfreq = MAX_HSI_HZ;
1302
1303 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1304 hsidivfreq = hsidivfreq / 2)
1305 if (hsidivfreq == hsifreq)
1306 break;
1307
1308 if (hsidiv == 4) {
1309 pr_err("clk-hsi frequency invalid");
1310 return -1;
1311 }
1312
1313 if (hsidiv > 0)
1314 return stm32mp1_set_hsidiv(rcc, hsidiv);
1315
1316 return 0;
1317 }
1318
pll_start(struct stm32mp1_clk_priv * priv,int pll_id)1319 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1320 {
1321 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1322
1323 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1324 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1325 RCC_PLLNCR_DIVREN,
1326 RCC_PLLNCR_PLLON);
1327 }
1328
pll_output(struct stm32mp1_clk_priv * priv,int pll_id,int output)1329 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1330 {
1331 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1332 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1333 u32 val;
1334 int ret;
1335
1336 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1337 TIMEOUT_200MS);
1338
1339 if (ret) {
1340 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1341 pll_id, pllxcr, readl(pllxcr));
1342 return ret;
1343 }
1344
1345 /* start the requested output */
1346 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1347
1348 return 0;
1349 }
1350
pll_stop(struct stm32mp1_clk_priv * priv,int pll_id)1351 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1352 {
1353 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1354 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1355 u32 val;
1356
1357 /* stop all output */
1358 clrbits_le32(pllxcr,
1359 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1360
1361 /* stop PLL */
1362 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1363
1364 /* wait PLL stopped */
1365 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1366 TIMEOUT_200MS);
1367 }
1368
pll_config_output(struct stm32mp1_clk_priv * priv,int pll_id,u32 * pllcfg)1369 static void pll_config_output(struct stm32mp1_clk_priv *priv,
1370 int pll_id, u32 *pllcfg)
1371 {
1372 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1373 fdt_addr_t rcc = priv->base;
1374 u32 value;
1375
1376 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1377 & RCC_PLLNCFGR2_DIVP_MASK;
1378 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1379 & RCC_PLLNCFGR2_DIVQ_MASK;
1380 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1381 & RCC_PLLNCFGR2_DIVR_MASK;
1382 writel(value, rcc + pll[pll_id].pllxcfgr2);
1383 }
1384
pll_config(struct stm32mp1_clk_priv * priv,int pll_id,u32 * pllcfg,u32 fracv)1385 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1386 u32 *pllcfg, u32 fracv)
1387 {
1388 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1389 fdt_addr_t rcc = priv->base;
1390 enum stm32mp1_plltype type = pll[pll_id].plltype;
1391 int src;
1392 ulong refclk;
1393 u8 ifrge = 0;
1394 u32 value;
1395
1396 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1397
1398 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1399 (pllcfg[PLLCFG_M] + 1);
1400
1401 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1402 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1403 debug("invalid refclk = %x\n", (u32)refclk);
1404 return -EINVAL;
1405 }
1406 if (type == PLL_800 && refclk >= 8000000)
1407 ifrge = 1;
1408
1409 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1410 & RCC_PLLNCFGR1_DIVN_MASK;
1411 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1412 & RCC_PLLNCFGR1_DIVM_MASK;
1413 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1414 & RCC_PLLNCFGR1_IFRGE_MASK;
1415 writel(value, rcc + pll[pll_id].pllxcfgr1);
1416
1417 /* fractional configuration: load sigma-delta modulator (SDM) */
1418
1419 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1420 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1421 rcc + pll[pll_id].pllxfracr);
1422
1423 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1424 setbits_le32(rcc + pll[pll_id].pllxfracr,
1425 RCC_PLLNFRACR_FRACLE);
1426
1427 pll_config_output(priv, pll_id, pllcfg);
1428
1429 return 0;
1430 }
1431
pll_csg(struct stm32mp1_clk_priv * priv,int pll_id,u32 * csg)1432 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1433 {
1434 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1435 u32 pllxcsg;
1436
1437 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1438 RCC_PLLNCSGR_MOD_PER_MASK) |
1439 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1440 RCC_PLLNCSGR_INC_STEP_MASK) |
1441 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1442 RCC_PLLNCSGR_SSCG_MODE_MASK);
1443
1444 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1445
1446 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
1447 }
1448
set_clksrc(struct stm32mp1_clk_priv * priv,unsigned int clksrc)1449 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1450 {
1451 u32 address = priv->base + (clksrc >> 4);
1452 u32 val;
1453 int ret;
1454
1455 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1456 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1457 TIMEOUT_200MS);
1458 if (ret)
1459 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1460 clksrc, address, readl(address));
1461
1462 return ret;
1463 }
1464
stgen_config(struct stm32mp1_clk_priv * priv)1465 static void stgen_config(struct stm32mp1_clk_priv *priv)
1466 {
1467 int p;
1468 u32 stgenc, cntfid0;
1469 ulong rate;
1470
1471 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1472
1473 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1474 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1475 rate = stm32mp1_clk_get(priv, p);
1476
1477 if (cntfid0 != rate) {
1478 u64 counter;
1479
1480 pr_debug("System Generic Counter (STGEN) update\n");
1481 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1482 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1483 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1484 counter = lldiv(counter * (u64)rate, cntfid0);
1485 writel((u32)counter, stgenc + STGENC_CNTCVL);
1486 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
1487 writel(rate, stgenc + STGENC_CNTFID0);
1488 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1489
1490 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1491
1492 /* need to update gd->arch.timer_rate_hz with new frequency */
1493 timer_init();
1494 pr_debug("gd->arch.timer_rate_hz = %x\n",
1495 (u32)gd->arch.timer_rate_hz);
1496 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1497 }
1498 }
1499
set_clkdiv(unsigned int clkdiv,u32 address)1500 static int set_clkdiv(unsigned int clkdiv, u32 address)
1501 {
1502 u32 val;
1503 int ret;
1504
1505 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1506 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1507 TIMEOUT_200MS);
1508 if (ret)
1509 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1510 clkdiv, address, readl(address));
1511
1512 return ret;
1513 }
1514
stm32mp1_mco_csg(struct stm32mp1_clk_priv * priv,u32 clksrc,u32 clkdiv)1515 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1516 u32 clksrc, u32 clkdiv)
1517 {
1518 u32 address = priv->base + (clksrc >> 4);
1519
1520 /*
1521 * binding clksrc : bit15-4 offset
1522 * bit3: disable
1523 * bit2-0: MCOSEL[2:0]
1524 */
1525 if (clksrc & 0x8) {
1526 clrbits_le32(address, RCC_MCOCFG_MCOON);
1527 } else {
1528 clrsetbits_le32(address,
1529 RCC_MCOCFG_MCOSRC_MASK,
1530 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1531 clrsetbits_le32(address,
1532 RCC_MCOCFG_MCODIV_MASK,
1533 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1534 setbits_le32(address, RCC_MCOCFG_MCOON);
1535 }
1536 }
1537
set_rtcsrc(struct stm32mp1_clk_priv * priv,unsigned int clksrc,int lse_css)1538 static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1539 unsigned int clksrc,
1540 int lse_css)
1541 {
1542 u32 address = priv->base + RCC_BDCR;
1543
1544 if (readl(address) & RCC_BDCR_RTCCKEN)
1545 goto skip_rtc;
1546
1547 if (clksrc == CLK_RTC_DISABLED)
1548 goto skip_rtc;
1549
1550 clrsetbits_le32(address,
1551 RCC_BDCR_RTCSRC_MASK,
1552 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1553
1554 setbits_le32(address, RCC_BDCR_RTCCKEN);
1555
1556 skip_rtc:
1557 if (lse_css)
1558 setbits_le32(address, RCC_BDCR_LSECSSON);
1559 }
1560
pkcs_config(struct stm32mp1_clk_priv * priv,u32 pkcs)1561 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1562 {
1563 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1564 u32 value = pkcs & 0xF;
1565 u32 mask = 0xF;
1566
1567 if (pkcs & BIT(31)) {
1568 mask <<= 4;
1569 value <<= 4;
1570 }
1571 clrsetbits_le32(address, mask, value);
1572 }
1573
stm32mp1_clktree(struct udevice * dev)1574 static int stm32mp1_clktree(struct udevice *dev)
1575 {
1576 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1577 fdt_addr_t rcc = priv->base;
1578 unsigned int clksrc[CLKSRC_NB];
1579 unsigned int clkdiv[CLKDIV_NB];
1580 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1581 ofnode plloff[_PLL_NB];
1582 int ret;
1583 int i, len;
1584 int lse_css = 0;
1585 const u32 *pkcs_cell;
1586
1587 /* check mandatory field */
1588 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1589 if (ret < 0) {
1590 debug("field st,clksrc invalid: error %d\n", ret);
1591 return -FDT_ERR_NOTFOUND;
1592 }
1593
1594 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1595 if (ret < 0) {
1596 debug("field st,clkdiv invalid: error %d\n", ret);
1597 return -FDT_ERR_NOTFOUND;
1598 }
1599
1600 /* check mandatory field in each pll */
1601 for (i = 0; i < _PLL_NB; i++) {
1602 char name[12];
1603
1604 sprintf(name, "st,pll@%d", i);
1605 plloff[i] = dev_read_subnode(dev, name);
1606 if (!ofnode_valid(plloff[i]))
1607 continue;
1608 ret = ofnode_read_u32_array(plloff[i], "cfg",
1609 pllcfg[i], PLLCFG_NB);
1610 if (ret < 0) {
1611 debug("field cfg invalid: error %d\n", ret);
1612 return -FDT_ERR_NOTFOUND;
1613 }
1614 }
1615
1616 debug("configuration MCO\n");
1617 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1618 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1619
1620 debug("switch ON osillator\n");
1621 /*
1622 * switch ON oscillator found in device-tree,
1623 * HSI already ON after bootrom
1624 */
1625 if (priv->osc[_LSI])
1626 stm32mp1_lsi_set(rcc, 1);
1627
1628 if (priv->osc[_LSE]) {
1629 int bypass, digbyp, lsedrv;
1630 struct udevice *dev = priv->osc_dev[_LSE];
1631
1632 bypass = dev_read_bool(dev, "st,bypass");
1633 digbyp = dev_read_bool(dev, "st,digbypass");
1634 lse_css = dev_read_bool(dev, "st,css");
1635 lsedrv = dev_read_u32_default(dev, "st,drive",
1636 LSEDRV_MEDIUM_HIGH);
1637
1638 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
1639 }
1640
1641 if (priv->osc[_HSE]) {
1642 int bypass, digbyp, css;
1643 struct udevice *dev = priv->osc_dev[_HSE];
1644
1645 bypass = dev_read_bool(dev, "st,bypass");
1646 digbyp = dev_read_bool(dev, "st,digbypass");
1647 css = dev_read_bool(dev, "st,css");
1648
1649 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
1650 }
1651 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1652 * => switch on CSI even if node is not present in device tree
1653 */
1654 stm32mp1_csi_set(rcc, 1);
1655
1656 /* come back to HSI */
1657 debug("come back to HSI\n");
1658 set_clksrc(priv, CLK_MPU_HSI);
1659 set_clksrc(priv, CLK_AXI_HSI);
1660 set_clksrc(priv, CLK_MCU_HSI);
1661
1662 debug("pll stop\n");
1663 for (i = 0; i < _PLL_NB; i++)
1664 pll_stop(priv, i);
1665
1666 /* configure HSIDIV */
1667 debug("configure HSIDIV\n");
1668 if (priv->osc[_HSI]) {
1669 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
1670 stgen_config(priv);
1671 }
1672
1673 /* select DIV */
1674 debug("select DIV\n");
1675 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1676 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1677 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1678 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1679 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1680 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1681 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1682 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1683 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1684
1685 /* no ready bit for RTC */
1686 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1687
1688 /* configure PLLs source */
1689 debug("configure PLLs source\n");
1690 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1691 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1692 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1693
1694 /* configure and start PLLs */
1695 debug("configure PLLs\n");
1696 for (i = 0; i < _PLL_NB; i++) {
1697 u32 fracv;
1698 u32 csg[PLLCSG_NB];
1699
1700 debug("configure PLL %d @ %d\n", i,
1701 ofnode_to_offset(plloff[i]));
1702 if (!ofnode_valid(plloff[i]))
1703 continue;
1704
1705 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1706 pll_config(priv, i, pllcfg[i], fracv);
1707 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1708 if (!ret) {
1709 pll_csg(priv, i, csg);
1710 } else if (ret != -FDT_ERR_NOTFOUND) {
1711 debug("invalid csg node for pll@%d res=%d\n", i, ret);
1712 return ret;
1713 }
1714 pll_start(priv, i);
1715 }
1716
1717 /* wait and start PLLs ouptut when ready */
1718 for (i = 0; i < _PLL_NB; i++) {
1719 if (!ofnode_valid(plloff[i]))
1720 continue;
1721 debug("output PLL %d\n", i);
1722 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1723 }
1724
1725 /* wait LSE ready before to use it */
1726 if (priv->osc[_LSE])
1727 stm32mp1_lse_wait(rcc);
1728
1729 /* configure with expected clock source */
1730 debug("CLKSRC\n");
1731 set_clksrc(priv, clksrc[CLKSRC_MPU]);
1732 set_clksrc(priv, clksrc[CLKSRC_AXI]);
1733 set_clksrc(priv, clksrc[CLKSRC_MCU]);
1734 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1735
1736 /* configure PKCK */
1737 debug("PKCK\n");
1738 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1739 if (pkcs_cell) {
1740 bool ckper_disabled = false;
1741
1742 for (i = 0; i < len / sizeof(u32); i++) {
1743 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1744
1745 if (pkcs == CLK_CKPER_DISABLED) {
1746 ckper_disabled = true;
1747 continue;
1748 }
1749 pkcs_config(priv, pkcs);
1750 }
1751 /* CKPER is source for some peripheral clock
1752 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1753 * only if previous clock is still ON
1754 * => deactivated CKPER only after switching clock
1755 */
1756 if (ckper_disabled)
1757 pkcs_config(priv, CLK_CKPER_DISABLED);
1758 }
1759
1760 /* STGEN clock source can change with CLK_STGEN_XXX */
1761 stgen_config(priv);
1762
1763 debug("oscillator off\n");
1764 /* switch OFF HSI if not found in device-tree */
1765 if (!priv->osc[_HSI])
1766 stm32mp1_hsi_set(rcc, 0);
1767
1768 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1769 clrsetbits_le32(priv->base + RCC_DDRITFCR,
1770 RCC_DDRITFCR_DDRCKMOD_MASK,
1771 RCC_DDRITFCR_DDRCKMOD_SSR <<
1772 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1773
1774 return 0;
1775 }
1776 #endif /* STM32MP1_CLOCK_TREE_INIT */
1777
pll_set_output_rate(struct udevice * dev,int pll_id,int div_id,unsigned long clk_rate)1778 static int pll_set_output_rate(struct udevice *dev,
1779 int pll_id,
1780 int div_id,
1781 unsigned long clk_rate)
1782 {
1783 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1784 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1785 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1786 int div;
1787 ulong fvco;
1788
1789 if (div_id > _DIV_NB)
1790 return -EINVAL;
1791
1792 fvco = pll_get_fvco(priv, pll_id);
1793
1794 if (fvco <= clk_rate)
1795 div = 1;
1796 else
1797 div = DIV_ROUND_UP(fvco, clk_rate);
1798
1799 if (div > 128)
1800 div = 128;
1801
1802 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1803 /* stop the requested output */
1804 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1805 /* change divider */
1806 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1807 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1808 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1809 /* start the requested output */
1810 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1811
1812 return 0;
1813 }
1814
stm32mp1_clk_set_rate(struct clk * clk,unsigned long clk_rate)1815 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1816 {
1817 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1818 int p;
1819
1820 switch (clk->id) {
1821 case LTDC_PX:
1822 case DSI_PX:
1823 break;
1824 default:
1825 pr_err("not supported");
1826 return -EINVAL;
1827 }
1828
1829 p = stm32mp1_clk_get_parent(priv, clk->id);
1830 if (p < 0)
1831 return -EINVAL;
1832
1833 switch (p) {
1834 case _PLL4_Q:
1835 /* for LTDC_PX and DSI_PX case */
1836 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1837 }
1838
1839 return -EINVAL;
1840 }
1841
stm32mp1_osc_clk_init(const char * name,struct stm32mp1_clk_priv * priv,int index)1842 static void stm32mp1_osc_clk_init(const char *name,
1843 struct stm32mp1_clk_priv *priv,
1844 int index)
1845 {
1846 struct clk clk;
1847 struct udevice *dev = NULL;
1848
1849 priv->osc[index] = 0;
1850 clk.id = 0;
1851 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1852 if (clk_request(dev, &clk))
1853 pr_err("%s request", name);
1854 else
1855 priv->osc[index] = clk_get_rate(&clk);
1856 }
1857 priv->osc_dev[index] = dev;
1858 }
1859
stm32mp1_osc_init(struct udevice * dev)1860 static void stm32mp1_osc_init(struct udevice *dev)
1861 {
1862 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1863 int i;
1864 const char *name[NB_OSC] = {
1865 [_LSI] = "clk-lsi",
1866 [_LSE] = "clk-lse",
1867 [_HSI] = "clk-hsi",
1868 [_HSE] = "clk-hse",
1869 [_CSI] = "clk-csi",
1870 [_I2S_CKIN] = "i2s_ckin",
1871 };
1872
1873 for (i = 0; i < NB_OSC; i++) {
1874 stm32mp1_osc_clk_init(name[i], priv, i);
1875 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1876 }
1877 }
1878
stm32mp1_clk_dump(struct stm32mp1_clk_priv * priv)1879 static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
1880 {
1881 char buf[32];
1882 int i, s, p;
1883
1884 printf("Clocks:\n");
1885 for (i = 0; i < _PARENT_NB; i++) {
1886 printf("- %s : %s MHz\n",
1887 stm32mp1_clk_parent_name[i],
1888 strmhz(buf, stm32mp1_clk_get(priv, i)));
1889 }
1890 printf("Source Clocks:\n");
1891 for (i = 0; i < _PARENT_SEL_NB; i++) {
1892 p = (readl(priv->base + priv->data->sel[i].offset) >>
1893 priv->data->sel[i].src) & priv->data->sel[i].msk;
1894 if (p < priv->data->sel[i].nb_parent) {
1895 s = priv->data->sel[i].parent[p];
1896 printf("- %s(%d) => parent %s(%d)\n",
1897 stm32mp1_clk_parent_sel_name[i], i,
1898 stm32mp1_clk_parent_name[s], s);
1899 } else {
1900 printf("- %s(%d) => parent index %d is invalid\n",
1901 stm32mp1_clk_parent_sel_name[i], i, p);
1902 }
1903 }
1904 }
1905
1906 #ifdef CONFIG_CMD_CLK
soc_clk_dump(void)1907 int soc_clk_dump(void)
1908 {
1909 struct udevice *dev;
1910 struct stm32mp1_clk_priv *priv;
1911 int ret;
1912
1913 ret = uclass_get_device_by_driver(UCLASS_CLK,
1914 DM_GET_DRIVER(stm32mp1_clock),
1915 &dev);
1916 if (ret)
1917 return ret;
1918
1919 priv = dev_get_priv(dev);
1920
1921 stm32mp1_clk_dump(priv);
1922
1923 return 0;
1924 }
1925 #endif
1926
stm32mp1_clk_probe(struct udevice * dev)1927 static int stm32mp1_clk_probe(struct udevice *dev)
1928 {
1929 int result = 0;
1930 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1931
1932 priv->base = dev_read_addr(dev->parent);
1933 if (priv->base == FDT_ADDR_T_NONE)
1934 return -EINVAL;
1935
1936 priv->data = (void *)&stm32mp1_data;
1937
1938 if (!priv->data->gate || !priv->data->sel ||
1939 !priv->data->pll)
1940 return -EINVAL;
1941
1942 stm32mp1_osc_init(dev);
1943
1944 #ifdef STM32MP1_CLOCK_TREE_INIT
1945 /* clock tree init is done only one time, before relocation */
1946 if (!(gd->flags & GD_FLG_RELOC))
1947 result = stm32mp1_clktree(dev);
1948 #endif
1949
1950 #ifndef CONFIG_SPL_BUILD
1951 #if defined(DEBUG)
1952 /* display debug information for probe after relocation */
1953 if (gd->flags & GD_FLG_RELOC)
1954 stm32mp1_clk_dump(priv);
1955 #endif
1956
1957 #if defined(CONFIG_DISPLAY_CPUINFO)
1958 if (gd->flags & GD_FLG_RELOC) {
1959 char buf[32];
1960
1961 printf("Clocks:\n");
1962 printf("- MPU : %s MHz\n",
1963 strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
1964 printf("- MCU : %s MHz\n",
1965 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
1966 printf("- AXI : %s MHz\n",
1967 strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
1968 printf("- PER : %s MHz\n",
1969 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
1970 /* DDRPHYC father */
1971 printf("- DDR : %s MHz\n",
1972 strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
1973 }
1974 #endif /* CONFIG_DISPLAY_CPUINFO */
1975 #endif
1976
1977 return result;
1978 }
1979
1980 static const struct clk_ops stm32mp1_clk_ops = {
1981 .enable = stm32mp1_clk_enable,
1982 .disable = stm32mp1_clk_disable,
1983 .get_rate = stm32mp1_clk_get_rate,
1984 .set_rate = stm32mp1_clk_set_rate,
1985 };
1986
1987 U_BOOT_DRIVER(stm32mp1_clock) = {
1988 .name = "stm32mp1_clk",
1989 .id = UCLASS_CLK,
1990 .ops = &stm32mp1_clk_ops,
1991 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1992 .probe = stm32mp1_clk_probe,
1993 };
1994