1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <dm/root.h> 15 16 #include <dt-bindings/clock/stm32h7-clks.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* RCC CR specific definitions */ 21 #define RCC_CR_HSION BIT(0) 22 #define RCC_CR_HSIRDY BIT(2) 23 24 #define RCC_CR_HSEON BIT(16) 25 #define RCC_CR_HSERDY BIT(17) 26 #define RCC_CR_HSEBYP BIT(18) 27 #define RCC_CR_PLL1ON BIT(24) 28 #define RCC_CR_PLL1RDY BIT(25) 29 30 #define RCC_CR_HSIDIV_MASK GENMASK(4, 3) 31 #define RCC_CR_HSIDIV_SHIFT 3 32 33 #define RCC_CFGR_SW_MASK GENMASK(2, 0) 34 #define RCC_CFGR_SW_HSI 0 35 #define RCC_CFGR_SW_CSI 1 36 #define RCC_CFGR_SW_HSE 2 37 #define RCC_CFGR_SW_PLL1 3 38 #define RCC_CFGR_TIMPRE BIT(15) 39 40 #define RCC_PLLCKSELR_PLLSRC_HSI 0 41 #define RCC_PLLCKSELR_PLLSRC_CSI 1 42 #define RCC_PLLCKSELR_PLLSRC_HSE 2 43 #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3 44 45 #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0) 46 47 #define RCC_PLLCKSELR_DIVM1_SHIFT 4 48 #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4) 49 50 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0) 51 52 #define RCC_PLL1DIVR_DIVP1_SHIFT 9 53 #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9) 54 55 #define RCC_PLL1DIVR_DIVQ1_SHIFT 16 56 #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16) 57 58 #define RCC_PLL1DIVR_DIVR1_SHIFT 24 59 #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24) 60 61 #define RCC_PLL1FRACR_FRACN1_SHIFT 3 62 #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3) 63 64 #define RCC_PLLCFGR_PLL1RGE_SHIFT 2 65 #define PLL1RGE_1_2_MHZ 0 66 #define PLL1RGE_2_4_MHZ 1 67 #define PLL1RGE_4_8_MHZ 2 68 #define PLL1RGE_8_16_MHZ 3 69 #define RCC_PLLCFGR_DIVP1EN BIT(16) 70 #define RCC_PLLCFGR_DIVQ1EN BIT(17) 71 #define RCC_PLLCFGR_DIVR1EN BIT(18) 72 73 #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0) 74 #define RCC_D1CFGR_HPRE_DIVIDED BIT(3) 75 #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0) 76 77 #define RCC_D1CFGR_HPRE_DIV2 8 78 79 #define RCC_D1CFGR_D1PPRE_SHIFT 4 80 #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6) 81 #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4) 82 83 #define RCC_D1CFGR_D1CPRE_SHIFT 8 84 #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8) 85 #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11) 86 87 #define RCC_D2CFGR_D2PPRE1_SHIFT 4 88 #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6) 89 #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4) 90 91 #define RCC_D2CFGR_D2PPRE2_SHIFT 8 92 #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10) 93 #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8) 94 95 #define RCC_D3CFGR_D3PPRE_SHIFT 4 96 #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6) 97 #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4) 98 99 #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0) 100 #define FMCSRC_HCLKD1 0 101 #define FMCSRC_PLL1_Q_CK 1 102 #define FMCSRC_PLL2_R_CK 2 103 #define FMCSRC_PER_CK 3 104 105 #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4) 106 #define RCC_D1CCIPR_QSPISRC_SHIFT 4 107 #define QSPISRC_HCLKD1 0 108 #define QSPISRC_PLL1_Q_CK 1 109 #define QSPISRC_PLL2_R_CK 2 110 #define QSPISRC_PER_CK 3 111 112 #define PWR_CR3 0x0c 113 #define PWR_CR3_SCUEN BIT(2) 114 #define PWR_D3CR 0x18 115 #define PWR_D3CR_VOS_MASK GENMASK(15, 14) 116 #define PWR_D3CR_VOS_SHIFT 14 117 #define VOS_SCALE_3 1 118 #define VOS_SCALE_2 2 119 #define VOS_SCALE_1 3 120 #define PWR_D3CR_VOSREADY BIT(13) 121 122 struct stm32_rcc_regs { 123 u32 cr; /* 0x00 Source Control Register */ 124 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */ 125 u32 crrcr; /* 0x08 Clock Recovery RC Register */ 126 u32 reserved1; /* 0x0c reserved */ 127 u32 cfgr; /* 0x10 Clock Configuration Register */ 128 u32 reserved2; /* 0x14 reserved */ 129 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */ 130 u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */ 131 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */ 132 u32 reserved3; /* 0x24 reserved */ 133 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */ 134 u32 pllcfgr; /* 0x2c PLLs Configuration Register */ 135 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */ 136 u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */ 137 u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */ 138 u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */ 139 u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */ 140 u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */ 141 u32 reserved4; /* 0x48 reserved */ 142 u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */ 143 u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */ 144 u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */ 145 u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */ 146 u32 reserved5; /* 0x5c reserved */ 147 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */ 148 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */ 149 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */ 150 u32 reserved6; /* 0x6c reserved */ 151 u32 bdcr; /* 0x70 Backup Domain Control Register */ 152 u32 csr; /* 0x74 Clock Control and Status Register */ 153 u32 reserved7; /* 0x78 reserved */ 154 155 u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */ 156 u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */ 157 u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */ 158 u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */ 159 160 u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */ 161 u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */ 162 u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */ 163 u32 apb2rstr; /* 0x98 APB2 Clock Register */ 164 u32 apb4rstr; /* 0x9c APB4 Clock Register */ 165 166 u32 gcr; /* 0xa0 Global Control Register */ 167 u32 reserved8; /* 0xa4 reserved */ 168 u32 d3amr; /* 0xa8 D3 Autonomous mode Register */ 169 u32 reserved9[9];/* 0xac to 0xcc reserved */ 170 u32 rsr; /* 0xd0 Reset Status Register */ 171 u32 ahb3enr; /* 0xd4 AHB3 Clock Register */ 172 u32 ahb1enr; /* 0xd8 AHB1 Clock Register */ 173 u32 ahb2enr; /* 0xdc AHB2 Clock Register */ 174 u32 ahb4enr; /* 0xe0 AHB4 Clock Register */ 175 176 u32 apb3enr; /* 0xe4 APB3 Clock Register */ 177 u32 apb1lenr; /* 0xe8 APB1 low Clock Register */ 178 u32 apb1henr; /* 0xec APB1 high Clock Register */ 179 u32 apb2enr; /* 0xf0 APB2 Clock Register */ 180 u32 apb4enr; /* 0xf4 APB4 Clock Register */ 181 }; 182 183 #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr) 184 #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr) 185 #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr) 186 #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr) 187 #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr) 188 #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr) 189 #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr) 190 #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr) 191 #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr) 192 193 struct clk_cfg { 194 u32 gate_offset; 195 u8 gate_bit_idx; 196 const char *name; 197 }; 198 199 /* 200 * the way all these entries are sorted in this array could seem 201 * unlogical, but we are dependant of kernel DT_bindings, 202 * where clocks are separate in 2 banks, peripheral clocks and 203 * kernel clocks. 204 */ 205 206 static const struct clk_cfg clk_map[] = { 207 {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */ 208 {RCC_AHB3ENR, 30, "itcm"}, 209 {RCC_AHB3ENR, 29, "dtcm2"}, 210 {RCC_AHB3ENR, 28, "dtcm1"}, 211 {RCC_AHB3ENR, 8, "flitf"}, 212 {RCC_AHB3ENR, 5, "jpgdec"}, 213 {RCC_AHB3ENR, 4, "dma2d"}, 214 {RCC_AHB3ENR, 0, "mdma"}, 215 {RCC_AHB1ENR, 28, "usb2ulpi"}, 216 {RCC_AHB1ENR, 17, "eth1rx"}, 217 {RCC_AHB1ENR, 16, "eth1tx"}, 218 {RCC_AHB1ENR, 15, "eth1mac"}, 219 {RCC_AHB1ENR, 14, "art"}, 220 {RCC_AHB1ENR, 26, "usb1ulpi"}, 221 {RCC_AHB1ENR, 1, "dma2"}, 222 {RCC_AHB1ENR, 0, "dma1"}, 223 {RCC_AHB2ENR, 31, "d2sram3"}, 224 {RCC_AHB2ENR, 30, "d2sram2"}, 225 {RCC_AHB2ENR, 29, "d2sram1"}, 226 {RCC_AHB2ENR, 5, "hash"}, 227 {RCC_AHB2ENR, 4, "crypt"}, 228 {RCC_AHB2ENR, 0, "camitf"}, 229 {RCC_AHB4ENR, 28, "bkpram"}, 230 {RCC_AHB4ENR, 25, "hsem"}, 231 {RCC_AHB4ENR, 21, "bdma"}, 232 {RCC_AHB4ENR, 19, "crc"}, 233 {RCC_AHB4ENR, 10, "gpiok"}, 234 {RCC_AHB4ENR, 9, "gpioj"}, 235 {RCC_AHB4ENR, 8, "gpioi"}, 236 {RCC_AHB4ENR, 7, "gpioh"}, 237 {RCC_AHB4ENR, 6, "gpiog"}, 238 {RCC_AHB4ENR, 5, "gpiof"}, 239 {RCC_AHB4ENR, 4, "gpioe"}, 240 {RCC_AHB4ENR, 3, "gpiod"}, 241 {RCC_AHB4ENR, 2, "gpioc"}, 242 {RCC_AHB4ENR, 1, "gpiob"}, 243 {RCC_AHB4ENR, 0, "gpioa"}, 244 {RCC_APB3ENR, 6, "wwdg1"}, 245 {RCC_APB1LENR, 29, "dac12"}, 246 {RCC_APB1LENR, 11, "wwdg2"}, 247 {RCC_APB1LENR, 8, "tim14"}, 248 {RCC_APB1LENR, 7, "tim13"}, 249 {RCC_APB1LENR, 6, "tim12"}, 250 {RCC_APB1LENR, 5, "tim7"}, 251 {RCC_APB1LENR, 4, "tim6"}, 252 {RCC_APB1LENR, 3, "tim5"}, 253 {RCC_APB1LENR, 2, "tim4"}, 254 {RCC_APB1LENR, 1, "tim3"}, 255 {RCC_APB1LENR, 0, "tim2"}, 256 {RCC_APB1HENR, 5, "mdios"}, 257 {RCC_APB1HENR, 4, "opamp"}, 258 {RCC_APB1HENR, 1, "crs"}, 259 {RCC_APB2ENR, 18, "tim17"}, 260 {RCC_APB2ENR, 17, "tim16"}, 261 {RCC_APB2ENR, 16, "tim15"}, 262 {RCC_APB2ENR, 1, "tim8"}, 263 {RCC_APB2ENR, 0, "tim1"}, 264 {RCC_APB4ENR, 26, "tmpsens"}, 265 {RCC_APB4ENR, 16, "rtcapb"}, 266 {RCC_APB4ENR, 15, "vref"}, 267 {RCC_APB4ENR, 14, "comp12"}, 268 {RCC_APB4ENR, 1, "syscfg"}, 269 {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */ 270 {RCC_AHB3ENR, 14, "quadspi"}, 271 {RCC_AHB3ENR, 12, "fmc"}, 272 {RCC_AHB1ENR, 27, "usb2otg"}, 273 {RCC_AHB1ENR, 25, "usb1otg"}, 274 {RCC_AHB1ENR, 5, "adc12"}, 275 {RCC_AHB2ENR, 9, "sdmmc2"}, 276 {RCC_AHB2ENR, 6, "rng"}, 277 {RCC_AHB4ENR, 24, "adc3"}, 278 {RCC_APB3ENR, 4, "dsi"}, 279 {RCC_APB3ENR, 3, "ltdc"}, 280 {RCC_APB1LENR, 31, "usart8"}, 281 {RCC_APB1LENR, 30, "usart7"}, 282 {RCC_APB1LENR, 27, "hdmicec"}, 283 {RCC_APB1LENR, 23, "i2c3"}, 284 {RCC_APB1LENR, 22, "i2c2"}, 285 {RCC_APB1LENR, 21, "i2c1"}, 286 {RCC_APB1LENR, 20, "uart5"}, 287 {RCC_APB1LENR, 19, "uart4"}, 288 {RCC_APB1LENR, 18, "usart3"}, 289 {RCC_APB1LENR, 17, "usart2"}, 290 {RCC_APB1LENR, 16, "spdifrx"}, 291 {RCC_APB1LENR, 15, "spi3"}, 292 {RCC_APB1LENR, 14, "spi2"}, 293 {RCC_APB1LENR, 9, "lptim1"}, 294 {RCC_APB1HENR, 8, "fdcan"}, 295 {RCC_APB1HENR, 2, "swp"}, 296 {RCC_APB2ENR, 29, "hrtim"}, 297 {RCC_APB2ENR, 28, "dfsdm1"}, 298 {RCC_APB2ENR, 24, "sai3"}, 299 {RCC_APB2ENR, 23, "sai2"}, 300 {RCC_APB2ENR, 22, "sai1"}, 301 {RCC_APB2ENR, 20, "spi5"}, 302 {RCC_APB2ENR, 13, "spi4"}, 303 {RCC_APB2ENR, 12, "spi1"}, 304 {RCC_APB2ENR, 5, "usart6"}, 305 {RCC_APB2ENR, 4, "usart1"}, 306 {RCC_APB4ENR, 21, "sai4a"}, 307 {RCC_APB4ENR, 21, "sai4b"}, 308 {RCC_APB4ENR, 12, "lptim5"}, 309 {RCC_APB4ENR, 11, "lptim4"}, 310 {RCC_APB4ENR, 10, "lptim3"}, 311 {RCC_APB4ENR, 9, "lptim2"}, 312 {RCC_APB4ENR, 7, "i2c4"}, 313 {RCC_APB4ENR, 5, "spi6"}, 314 {RCC_APB4ENR, 3, "lpuart1"}, 315 }; 316 317 struct stm32_clk { 318 struct stm32_rcc_regs *rcc_base; 319 struct regmap *pwr_regmap; 320 }; 321 322 struct pll_psc { 323 u8 divm; 324 u16 divn; 325 u8 divp; 326 u8 divq; 327 u8 divr; 328 }; 329 330 /* 331 * OSC_HSE = 25 MHz 332 * VCO = 500MHz 333 * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz 334 */ 335 struct pll_psc sys_pll_psc = { 336 .divm = 4, 337 .divn = 80, 338 .divp = 2, 339 .divq = 2, 340 .divr = 2, 341 }; 342 343 enum apb { 344 APB1, 345 APB2, 346 }; 347 348 int configure_clocks(struct udevice *dev) 349 { 350 struct stm32_clk *priv = dev_get_priv(dev); 351 struct stm32_rcc_regs *regs = priv->rcc_base; 352 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0); 353 uint32_t pllckselr = 0; 354 uint32_t pll1divr = 0; 355 uint32_t pllcfgr = 0; 356 357 /* Switch on HSI */ 358 setbits_le32(®s->cr, RCC_CR_HSION); 359 while (!(readl(®s->cr) & RCC_CR_HSIRDY)) 360 ; 361 362 /* Reset CFGR, now HSI is the default system clock */ 363 writel(0, ®s->cfgr); 364 365 /* Set all kernel domain clock registers to reset value*/ 366 writel(0x0, ®s->d1ccipr); 367 writel(0x0, ®s->d2ccip1r); 368 writel(0x0, ®s->d2ccip2r); 369 370 /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */ 371 clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK, 372 VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT); 373 /* Lock supply configuration update */ 374 clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN); 375 while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY)) 376 ; 377 378 /* disable HSE to configure it */ 379 clrbits_le32(®s->cr, RCC_CR_HSEON); 380 while ((readl(®s->cr) & RCC_CR_HSERDY)) 381 ; 382 383 /* clear HSE bypass and set it ON */ 384 clrbits_le32(®s->cr, RCC_CR_HSEBYP); 385 /* Switch on HSE */ 386 setbits_le32(®s->cr, RCC_CR_HSEON); 387 while (!(readl(®s->cr) & RCC_CR_HSERDY)) 388 ; 389 390 /* pll setup, disable it */ 391 clrbits_le32(®s->cr, RCC_CR_PLL1ON); 392 while ((readl(®s->cr) & RCC_CR_PLL1RDY)) 393 ; 394 395 /* Select HSE as PLL clock source */ 396 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE; 397 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; 398 writel(pllckselr, ®s->pllckselr); 399 400 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; 401 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; 402 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; 403 pll1divr |= (sys_pll_psc.divn - 1); 404 writel(pll1divr, ®s->pll1divr); 405 406 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT; 407 pllcfgr |= RCC_PLLCFGR_DIVP1EN; 408 pllcfgr |= RCC_PLLCFGR_DIVQ1EN; 409 pllcfgr |= RCC_PLLCFGR_DIVR1EN; 410 writel(pllcfgr, ®s->pllcfgr); 411 412 /* pll setup, enable it */ 413 setbits_le32(®s->cr, RCC_CR_PLL1ON); 414 415 /* set HPRE (/2) DI clk --> 125MHz */ 416 clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK, 417 RCC_D1CFGR_HPRE_DIV2); 418 419 /* select PLL1 as system clock source (sys_ck)*/ 420 clrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); 421 while ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) 422 ; 423 424 /* sdram: use pll1_q as fmc_k clk */ 425 clrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK, 426 FMCSRC_PLL1_Q_CK); 427 428 return 0; 429 } 430 431 static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs) 432 { 433 u32 divider; 434 435 /* get HSI divider value */ 436 divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK; 437 divider = divider >> RCC_CR_HSIDIV_SHIFT; 438 439 return divider; 440 }; 441 442 enum pllsrc { 443 HSE, 444 LSE, 445 HSI, 446 CSI, 447 I2S, 448 TIMER, 449 PLLSRC_NB, 450 }; 451 452 static const char * const pllsrc_name[PLLSRC_NB] = { 453 [HSE] = "clk-hse", 454 [LSE] = "clk-lse", 455 [HSI] = "clk-hsi", 456 [CSI] = "clk-csi", 457 [I2S] = "clk-i2s", 458 [TIMER] = "timer-clk" 459 }; 460 461 static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc) 462 { 463 struct clk clk; 464 struct udevice *fixed_clock_dev = NULL; 465 u32 divider; 466 int ret; 467 const char *name = pllsrc_name[pllsrc]; 468 469 debug("%s name %s\n", __func__, name); 470 471 clk.id = 0; 472 ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev); 473 if (ret) { 474 pr_err("Can't find clk %s (%d)", name, ret); 475 return 0; 476 } 477 478 ret = clk_request(fixed_clock_dev, &clk); 479 if (ret) { 480 pr_err("Can't request %s clk (%d)", name, ret); 481 return 0; 482 } 483 484 divider = 0; 485 if (pllsrc == HSI) 486 divider = stm32_get_HSI_divider(regs); 487 488 debug("%s divider %d rate %ld\n", __func__, 489 divider, clk_get_rate(&clk)); 490 491 return clk_get_rate(&clk) >> divider; 492 }; 493 494 enum pll1_output { 495 PLL1_P_CK, 496 PLL1_Q_CK, 497 PLL1_R_CK, 498 }; 499 500 static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, 501 enum pll1_output output) 502 { 503 ulong pllsrc = 0; 504 u32 divm1, divn1, divp1, divq1, divr1, fracn1; 505 ulong vco, rate; 506 507 /* get the PLLSRC */ 508 switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) { 509 case RCC_PLLCKSELR_PLLSRC_HSI: 510 pllsrc = stm32_get_rate(regs, HSI); 511 break; 512 case RCC_PLLCKSELR_PLLSRC_CSI: 513 pllsrc = stm32_get_rate(regs, CSI); 514 break; 515 case RCC_PLLCKSELR_PLLSRC_HSE: 516 pllsrc = stm32_get_rate(regs, HSE); 517 break; 518 case RCC_PLLCKSELR_PLLSRC_NO_CLK: 519 /* shouldn't happen */ 520 pr_err("wrong value for RCC_PLLCKSELR register\n"); 521 pllsrc = 0; 522 break; 523 } 524 525 /* pllsrc = 0 ? no need to go ahead */ 526 if (!pllsrc) 527 return pllsrc; 528 529 /* get divm1, divp1, divn1 and divr1 */ 530 divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; 531 divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT; 532 533 divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1; 534 535 divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK; 536 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1; 537 538 divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK; 539 divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1; 540 541 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; 542 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; 543 544 fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; 545 fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; 546 547 vco = (pllsrc / divm1) * divn1; 548 rate = (pllsrc * fracn1) / (divm1 * 8192); 549 550 debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n", 551 __func__, divm1, divn1, divp1, divq1, divr1); 552 debug("%s fracn1 = %d vco = %ld rate = %ld\n", 553 __func__, fracn1, vco, rate); 554 555 switch (output) { 556 case PLL1_P_CK: 557 return (vco + rate) / divp1; 558 break; 559 case PLL1_Q_CK: 560 return (vco + rate) / divq1; 561 break; 562 563 case PLL1_R_CK: 564 return (vco + rate) / divr1; 565 break; 566 } 567 568 return -EINVAL; 569 } 570 571 static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb) 572 { 573 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; 574 u32 d2cfgr = readl(®s->d2cfgr); 575 576 if (apb == APB1) { 577 if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) 578 /* get D2 domain APB1 prescaler */ 579 return prescaler_table[ 580 ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) 581 >> RCC_D2CFGR_D2PPRE1_SHIFT)]; 582 } else { /* APB2 */ 583 if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) 584 /* get D2 domain APB2 prescaler */ 585 return prescaler_table[ 586 ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) 587 >> RCC_D2CFGR_D2PPRE2_SHIFT)]; 588 } 589 590 return 1; 591 }; 592 593 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk, 594 enum apb apb) 595 { 596 struct stm32_rcc_regs *regs = priv->rcc_base; 597 u32 psc = stm32_get_apb_psc(regs, apb); 598 599 if (readl(®s->cfgr) & RCC_CFGR_TIMPRE) 600 /* 601 * if APB prescaler is configured to a 602 * division factor of 1, 2 or 4 603 */ 604 switch (psc) { 605 case 1: 606 case 2: 607 case 4: 608 return sysclk; 609 case 8: 610 return sysclk / 2; 611 case 16: 612 return sysclk / 4; 613 default: 614 pr_err("unexpected prescaler value (%d)\n", psc); 615 return 0; 616 } 617 else 618 switch (psc) { 619 case 1: 620 return sysclk; 621 case 2: 622 case 4: 623 case 8: 624 case 16: 625 return sysclk / psc; 626 default: 627 pr_err("unexpected prescaler value (%d)\n", psc); 628 return 0; 629 } 630 }; 631 632 static ulong stm32_clk_get_rate(struct clk *clk) 633 { 634 struct stm32_clk *priv = dev_get_priv(clk->dev); 635 struct stm32_rcc_regs *regs = priv->rcc_base; 636 ulong sysclk = 0; 637 u32 gate_offset; 638 u32 d1cfgr, d3cfgr; 639 /* prescaler table lookups for clock computation */ 640 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; 641 u8 source, idx; 642 643 /* 644 * get system clock (sys_ck) source 645 * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck 646 */ 647 source = readl(®s->cfgr) & RCC_CFGR_SW_MASK; 648 switch (source) { 649 case RCC_CFGR_SW_PLL1: 650 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK); 651 break; 652 case RCC_CFGR_SW_HSE: 653 sysclk = stm32_get_rate(regs, HSE); 654 break; 655 656 case RCC_CFGR_SW_CSI: 657 sysclk = stm32_get_rate(regs, CSI); 658 break; 659 660 case RCC_CFGR_SW_HSI: 661 sysclk = stm32_get_rate(regs, HSI); 662 break; 663 } 664 665 /* sysclk = 0 ? no need to go ahead */ 666 if (!sysclk) 667 return sysclk; 668 669 debug("%s system clock: source = %d freq = %ld\n", 670 __func__, source, sysclk); 671 672 d1cfgr = readl(®s->d1cfgr); 673 674 if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) { 675 /* get D1 domain Core prescaler */ 676 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >> 677 RCC_D1CFGR_D1CPRE_SHIFT; 678 sysclk = sysclk / prescaler_table[idx]; 679 } 680 681 if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) { 682 /* get D1 domain AHB prescaler */ 683 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER; 684 sysclk = sysclk / prescaler_table[idx]; 685 } 686 687 gate_offset = clk_map[clk->id].gate_offset; 688 689 debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n", 690 __func__, clk->id, gate_offset, sysclk); 691 692 switch (gate_offset) { 693 case RCC_AHB3ENR: 694 case RCC_AHB1ENR: 695 case RCC_AHB2ENR: 696 case RCC_AHB4ENR: 697 return sysclk; 698 break; 699 700 case RCC_APB3ENR: 701 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) { 702 /* get D1 domain APB3 prescaler */ 703 idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >> 704 RCC_D1CFGR_D1PPRE_SHIFT; 705 sysclk = sysclk / prescaler_table[idx]; 706 } 707 708 debug("%s system clock: freq after APB3 prescaler = %ld\n", 709 __func__, sysclk); 710 711 return sysclk; 712 break; 713 714 case RCC_APB4ENR: 715 d3cfgr = readl(®s->d3cfgr); 716 if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { 717 /* get D3 domain APB4 prescaler */ 718 idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> 719 RCC_D3CFGR_D3PPRE_SHIFT; 720 sysclk = sysclk / prescaler_table[idx]; 721 } 722 723 debug("%s system clock: freq after APB4 prescaler = %ld\n", 724 __func__, sysclk); 725 726 return sysclk; 727 break; 728 729 case RCC_APB1LENR: 730 case RCC_APB1HENR: 731 /* special case for GPT timers */ 732 switch (clk->id) { 733 case TIM14_CK: 734 case TIM13_CK: 735 case TIM12_CK: 736 case TIM7_CK: 737 case TIM6_CK: 738 case TIM5_CK: 739 case TIM4_CK: 740 case TIM3_CK: 741 case TIM2_CK: 742 return stm32_get_timer_rate(priv, sysclk, APB1); 743 } 744 745 debug("%s system clock: freq after APB1 prescaler = %ld\n", 746 __func__, sysclk); 747 748 return (sysclk / stm32_get_apb_psc(regs, APB1)); 749 break; 750 751 case RCC_APB2ENR: 752 /* special case for timers */ 753 switch (clk->id) { 754 case TIM17_CK: 755 case TIM16_CK: 756 case TIM15_CK: 757 case TIM8_CK: 758 case TIM1_CK: 759 return stm32_get_timer_rate(priv, sysclk, APB2); 760 } 761 762 debug("%s system clock: freq after APB2 prescaler = %ld\n", 763 __func__, sysclk); 764 765 return (sysclk / stm32_get_apb_psc(regs, APB2)); 766 767 break; 768 769 default: 770 pr_err("unexpected gate_offset value (0x%x)\n", gate_offset); 771 return -EINVAL; 772 break; 773 } 774 } 775 776 static int stm32_clk_enable(struct clk *clk) 777 { 778 struct stm32_clk *priv = dev_get_priv(clk->dev); 779 struct stm32_rcc_regs *regs = priv->rcc_base; 780 u32 gate_offset; 781 u32 gate_bit_index; 782 unsigned long clk_id = clk->id; 783 784 gate_offset = clk_map[clk_id].gate_offset; 785 gate_bit_index = clk_map[clk_id].gate_bit_idx; 786 787 debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n", 788 __func__, clk->id, gate_offset, gate_bit_index, 789 clk_map[clk_id].name); 790 791 setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index)); 792 793 return 0; 794 } 795 796 static int stm32_clk_probe(struct udevice *dev) 797 { 798 struct stm32_clk *priv = dev_get_priv(dev); 799 struct udevice *syscon; 800 fdt_addr_t addr; 801 int err; 802 803 addr = dev_read_addr(dev); 804 if (addr == FDT_ADDR_T_NONE) 805 return -EINVAL; 806 807 priv->rcc_base = (struct stm32_rcc_regs *)addr; 808 809 /* get corresponding syscon phandle */ 810 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 811 "st,syscfg", &syscon); 812 813 if (err) { 814 pr_err("unable to find syscon device\n"); 815 return err; 816 } 817 818 priv->pwr_regmap = syscon_get_regmap(syscon); 819 if (!priv->pwr_regmap) { 820 pr_err("unable to find regmap\n"); 821 return -ENODEV; 822 } 823 824 configure_clocks(dev); 825 826 return 0; 827 } 828 829 static int stm32_clk_of_xlate(struct clk *clk, 830 struct ofnode_phandle_args *args) 831 { 832 if (args->args_count != 1) { 833 debug("Invaild args_count: %d\n", args->args_count); 834 return -EINVAL; 835 } 836 837 if (args->args_count) { 838 clk->id = args->args[0]; 839 /* 840 * this computation convert DT clock index which is used to 841 * point into 2 separate clock arrays (peripheral and kernel 842 * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h) 843 * into index to point into only one array where peripheral 844 * and kernel clocks are consecutive 845 */ 846 if (clk->id >= KERN_BANK) { 847 clk->id -= KERN_BANK; 848 clk->id += LAST_PERIF_BANK - PERIF_BANK + 1; 849 } else { 850 clk->id -= PERIF_BANK; 851 } 852 } else { 853 clk->id = 0; 854 } 855 856 debug("%s clk->id %ld\n", __func__, clk->id); 857 858 return 0; 859 } 860 861 static struct clk_ops stm32_clk_ops = { 862 .of_xlate = stm32_clk_of_xlate, 863 .enable = stm32_clk_enable, 864 .get_rate = stm32_clk_get_rate, 865 }; 866 867 U_BOOT_DRIVER(stm32h7_clk) = { 868 .name = "stm32h7_rcc_clock", 869 .id = UCLASS_CLK, 870 .ops = &stm32_clk_ops, 871 .probe = stm32_clk_probe, 872 .priv_auto_alloc_size = sizeof(struct stm32_clk), 873 .flags = DM_FLAG_PRE_RELOC, 874 }; 875