1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <dm/root.h> 15 16 #include <dt-bindings/clock/stm32h7-clks.h> 17 18 /* RCC CR specific definitions */ 19 #define RCC_CR_HSION BIT(0) 20 #define RCC_CR_HSIRDY BIT(2) 21 22 #define RCC_CR_HSEON BIT(16) 23 #define RCC_CR_HSERDY BIT(17) 24 #define RCC_CR_HSEBYP BIT(18) 25 #define RCC_CR_PLL1ON BIT(24) 26 #define RCC_CR_PLL1RDY BIT(25) 27 28 #define RCC_CR_HSIDIV_MASK GENMASK(4, 3) 29 #define RCC_CR_HSIDIV_SHIFT 3 30 31 #define RCC_CFGR_SW_MASK GENMASK(2, 0) 32 #define RCC_CFGR_SW_HSI 0 33 #define RCC_CFGR_SW_CSI 1 34 #define RCC_CFGR_SW_HSE 2 35 #define RCC_CFGR_SW_PLL1 3 36 #define RCC_CFGR_TIMPRE BIT(15) 37 38 #define RCC_PLLCKSELR_PLLSRC_HSI 0 39 #define RCC_PLLCKSELR_PLLSRC_CSI 1 40 #define RCC_PLLCKSELR_PLLSRC_HSE 2 41 #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3 42 43 #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0) 44 45 #define RCC_PLLCKSELR_DIVM1_SHIFT 4 46 #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4) 47 48 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0) 49 50 #define RCC_PLL1DIVR_DIVP1_SHIFT 9 51 #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9) 52 53 #define RCC_PLL1DIVR_DIVQ1_SHIFT 16 54 #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16) 55 56 #define RCC_PLL1DIVR_DIVR1_SHIFT 24 57 #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24) 58 59 #define RCC_PLL1FRACR_FRACN1_SHIFT 3 60 #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3) 61 62 #define RCC_PLLCFGR_PLL1RGE_SHIFT 2 63 #define PLL1RGE_1_2_MHZ 0 64 #define PLL1RGE_2_4_MHZ 1 65 #define PLL1RGE_4_8_MHZ 2 66 #define PLL1RGE_8_16_MHZ 3 67 #define RCC_PLLCFGR_DIVP1EN BIT(16) 68 #define RCC_PLLCFGR_DIVQ1EN BIT(17) 69 #define RCC_PLLCFGR_DIVR1EN BIT(18) 70 71 #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0) 72 #define RCC_D1CFGR_HPRE_DIVIDED BIT(3) 73 #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0) 74 75 #define RCC_D1CFGR_HPRE_DIV2 8 76 77 #define RCC_D1CFGR_D1PPRE_SHIFT 4 78 #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6) 79 #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4) 80 81 #define RCC_D1CFGR_D1CPRE_SHIFT 8 82 #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8) 83 #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11) 84 85 #define RCC_D2CFGR_D2PPRE1_SHIFT 4 86 #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6) 87 #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4) 88 89 #define RCC_D2CFGR_D2PPRE2_SHIFT 8 90 #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10) 91 #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8) 92 93 #define RCC_D3CFGR_D3PPRE_SHIFT 4 94 #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6) 95 #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4) 96 97 #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0) 98 #define FMCSRC_HCLKD1 0 99 #define FMCSRC_PLL1_Q_CK 1 100 #define FMCSRC_PLL2_R_CK 2 101 #define FMCSRC_PER_CK 3 102 103 #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4) 104 #define RCC_D1CCIPR_QSPISRC_SHIFT 4 105 #define QSPISRC_HCLKD1 0 106 #define QSPISRC_PLL1_Q_CK 1 107 #define QSPISRC_PLL2_R_CK 2 108 #define QSPISRC_PER_CK 3 109 110 #define PWR_CR3 0x0c 111 #define PWR_CR3_SCUEN BIT(2) 112 #define PWR_D3CR 0x18 113 #define PWR_D3CR_VOS_MASK GENMASK(15, 14) 114 #define PWR_D3CR_VOS_SHIFT 14 115 #define VOS_SCALE_3 1 116 #define VOS_SCALE_2 2 117 #define VOS_SCALE_1 3 118 #define PWR_D3CR_VOSREADY BIT(13) 119 120 struct stm32_rcc_regs { 121 u32 cr; /* 0x00 Source Control Register */ 122 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */ 123 u32 crrcr; /* 0x08 Clock Recovery RC Register */ 124 u32 reserved1; /* 0x0c reserved */ 125 u32 cfgr; /* 0x10 Clock Configuration Register */ 126 u32 reserved2; /* 0x14 reserved */ 127 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */ 128 u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */ 129 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */ 130 u32 reserved3; /* 0x24 reserved */ 131 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */ 132 u32 pllcfgr; /* 0x2c PLLs Configuration Register */ 133 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */ 134 u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */ 135 u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */ 136 u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */ 137 u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */ 138 u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */ 139 u32 reserved4; /* 0x48 reserved */ 140 u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */ 141 u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */ 142 u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */ 143 u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */ 144 u32 reserved5; /* 0x5c reserved */ 145 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */ 146 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */ 147 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */ 148 u32 reserved6; /* 0x6c reserved */ 149 u32 bdcr; /* 0x70 Backup Domain Control Register */ 150 u32 csr; /* 0x74 Clock Control and Status Register */ 151 u32 reserved7; /* 0x78 reserved */ 152 153 u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */ 154 u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */ 155 u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */ 156 u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */ 157 158 u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */ 159 u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */ 160 u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */ 161 u32 apb2rstr; /* 0x98 APB2 Clock Register */ 162 u32 apb4rstr; /* 0x9c APB4 Clock Register */ 163 164 u32 gcr; /* 0xa0 Global Control Register */ 165 u32 reserved8; /* 0xa4 reserved */ 166 u32 d3amr; /* 0xa8 D3 Autonomous mode Register */ 167 u32 reserved9[9];/* 0xac to 0xcc reserved */ 168 u32 rsr; /* 0xd0 Reset Status Register */ 169 u32 ahb3enr; /* 0xd4 AHB3 Clock Register */ 170 u32 ahb1enr; /* 0xd8 AHB1 Clock Register */ 171 u32 ahb2enr; /* 0xdc AHB2 Clock Register */ 172 u32 ahb4enr; /* 0xe0 AHB4 Clock Register */ 173 174 u32 apb3enr; /* 0xe4 APB3 Clock Register */ 175 u32 apb1lenr; /* 0xe8 APB1 low Clock Register */ 176 u32 apb1henr; /* 0xec APB1 high Clock Register */ 177 u32 apb2enr; /* 0xf0 APB2 Clock Register */ 178 u32 apb4enr; /* 0xf4 APB4 Clock Register */ 179 }; 180 181 #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr) 182 #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr) 183 #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr) 184 #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr) 185 #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr) 186 #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr) 187 #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr) 188 #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr) 189 #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr) 190 191 struct clk_cfg { 192 u32 gate_offset; 193 u8 gate_bit_idx; 194 const char *name; 195 }; 196 197 /* 198 * the way all these entries are sorted in this array could seem 199 * unlogical, but we are dependant of kernel DT_bindings, 200 * where clocks are separate in 2 banks, peripheral clocks and 201 * kernel clocks. 202 */ 203 204 static const struct clk_cfg clk_map[] = { 205 {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */ 206 {RCC_AHB3ENR, 30, "itcm"}, 207 {RCC_AHB3ENR, 29, "dtcm2"}, 208 {RCC_AHB3ENR, 28, "dtcm1"}, 209 {RCC_AHB3ENR, 8, "flitf"}, 210 {RCC_AHB3ENR, 5, "jpgdec"}, 211 {RCC_AHB3ENR, 4, "dma2d"}, 212 {RCC_AHB3ENR, 0, "mdma"}, 213 {RCC_AHB1ENR, 28, "usb2ulpi"}, 214 {RCC_AHB1ENR, 17, "eth1rx"}, 215 {RCC_AHB1ENR, 16, "eth1tx"}, 216 {RCC_AHB1ENR, 15, "eth1mac"}, 217 {RCC_AHB1ENR, 14, "art"}, 218 {RCC_AHB1ENR, 26, "usb1ulpi"}, 219 {RCC_AHB1ENR, 1, "dma2"}, 220 {RCC_AHB1ENR, 0, "dma1"}, 221 {RCC_AHB2ENR, 31, "d2sram3"}, 222 {RCC_AHB2ENR, 30, "d2sram2"}, 223 {RCC_AHB2ENR, 29, "d2sram1"}, 224 {RCC_AHB2ENR, 5, "hash"}, 225 {RCC_AHB2ENR, 4, "crypt"}, 226 {RCC_AHB2ENR, 0, "camitf"}, 227 {RCC_AHB4ENR, 28, "bkpram"}, 228 {RCC_AHB4ENR, 25, "hsem"}, 229 {RCC_AHB4ENR, 21, "bdma"}, 230 {RCC_AHB4ENR, 19, "crc"}, 231 {RCC_AHB4ENR, 10, "gpiok"}, 232 {RCC_AHB4ENR, 9, "gpioj"}, 233 {RCC_AHB4ENR, 8, "gpioi"}, 234 {RCC_AHB4ENR, 7, "gpioh"}, 235 {RCC_AHB4ENR, 6, "gpiog"}, 236 {RCC_AHB4ENR, 5, "gpiof"}, 237 {RCC_AHB4ENR, 4, "gpioe"}, 238 {RCC_AHB4ENR, 3, "gpiod"}, 239 {RCC_AHB4ENR, 2, "gpioc"}, 240 {RCC_AHB4ENR, 1, "gpiob"}, 241 {RCC_AHB4ENR, 0, "gpioa"}, 242 {RCC_APB3ENR, 6, "wwdg1"}, 243 {RCC_APB1LENR, 29, "dac12"}, 244 {RCC_APB1LENR, 11, "wwdg2"}, 245 {RCC_APB1LENR, 8, "tim14"}, 246 {RCC_APB1LENR, 7, "tim13"}, 247 {RCC_APB1LENR, 6, "tim12"}, 248 {RCC_APB1LENR, 5, "tim7"}, 249 {RCC_APB1LENR, 4, "tim6"}, 250 {RCC_APB1LENR, 3, "tim5"}, 251 {RCC_APB1LENR, 2, "tim4"}, 252 {RCC_APB1LENR, 1, "tim3"}, 253 {RCC_APB1LENR, 0, "tim2"}, 254 {RCC_APB1HENR, 5, "mdios"}, 255 {RCC_APB1HENR, 4, "opamp"}, 256 {RCC_APB1HENR, 1, "crs"}, 257 {RCC_APB2ENR, 18, "tim17"}, 258 {RCC_APB2ENR, 17, "tim16"}, 259 {RCC_APB2ENR, 16, "tim15"}, 260 {RCC_APB2ENR, 1, "tim8"}, 261 {RCC_APB2ENR, 0, "tim1"}, 262 {RCC_APB4ENR, 26, "tmpsens"}, 263 {RCC_APB4ENR, 16, "rtcapb"}, 264 {RCC_APB4ENR, 15, "vref"}, 265 {RCC_APB4ENR, 14, "comp12"}, 266 {RCC_APB4ENR, 1, "syscfg"}, 267 {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */ 268 {RCC_AHB3ENR, 14, "quadspi"}, 269 {RCC_AHB3ENR, 12, "fmc"}, 270 {RCC_AHB1ENR, 27, "usb2otg"}, 271 {RCC_AHB1ENR, 25, "usb1otg"}, 272 {RCC_AHB1ENR, 5, "adc12"}, 273 {RCC_AHB2ENR, 9, "sdmmc2"}, 274 {RCC_AHB2ENR, 6, "rng"}, 275 {RCC_AHB4ENR, 24, "adc3"}, 276 {RCC_APB3ENR, 4, "dsi"}, 277 {RCC_APB3ENR, 3, "ltdc"}, 278 {RCC_APB1LENR, 31, "usart8"}, 279 {RCC_APB1LENR, 30, "usart7"}, 280 {RCC_APB1LENR, 27, "hdmicec"}, 281 {RCC_APB1LENR, 23, "i2c3"}, 282 {RCC_APB1LENR, 22, "i2c2"}, 283 {RCC_APB1LENR, 21, "i2c1"}, 284 {RCC_APB1LENR, 20, "uart5"}, 285 {RCC_APB1LENR, 19, "uart4"}, 286 {RCC_APB1LENR, 18, "usart3"}, 287 {RCC_APB1LENR, 17, "usart2"}, 288 {RCC_APB1LENR, 16, "spdifrx"}, 289 {RCC_APB1LENR, 15, "spi3"}, 290 {RCC_APB1LENR, 14, "spi2"}, 291 {RCC_APB1LENR, 9, "lptim1"}, 292 {RCC_APB1HENR, 8, "fdcan"}, 293 {RCC_APB1HENR, 2, "swp"}, 294 {RCC_APB2ENR, 29, "hrtim"}, 295 {RCC_APB2ENR, 28, "dfsdm1"}, 296 {RCC_APB2ENR, 24, "sai3"}, 297 {RCC_APB2ENR, 23, "sai2"}, 298 {RCC_APB2ENR, 22, "sai1"}, 299 {RCC_APB2ENR, 20, "spi5"}, 300 {RCC_APB2ENR, 13, "spi4"}, 301 {RCC_APB2ENR, 12, "spi1"}, 302 {RCC_APB2ENR, 5, "usart6"}, 303 {RCC_APB2ENR, 4, "usart1"}, 304 {RCC_APB4ENR, 21, "sai4a"}, 305 {RCC_APB4ENR, 21, "sai4b"}, 306 {RCC_APB4ENR, 12, "lptim5"}, 307 {RCC_APB4ENR, 11, "lptim4"}, 308 {RCC_APB4ENR, 10, "lptim3"}, 309 {RCC_APB4ENR, 9, "lptim2"}, 310 {RCC_APB4ENR, 7, "i2c4"}, 311 {RCC_APB4ENR, 5, "spi6"}, 312 {RCC_APB4ENR, 3, "lpuart1"}, 313 }; 314 315 struct stm32_clk { 316 struct stm32_rcc_regs *rcc_base; 317 struct regmap *pwr_regmap; 318 }; 319 320 struct pll_psc { 321 u8 divm; 322 u16 divn; 323 u8 divp; 324 u8 divq; 325 u8 divr; 326 }; 327 328 /* 329 * OSC_HSE = 25 MHz 330 * VCO = 500MHz 331 * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz 332 */ 333 struct pll_psc sys_pll_psc = { 334 .divm = 4, 335 .divn = 80, 336 .divp = 2, 337 .divq = 2, 338 .divr = 2, 339 }; 340 341 enum apb { 342 APB1, 343 APB2, 344 }; 345 346 int configure_clocks(struct udevice *dev) 347 { 348 struct stm32_clk *priv = dev_get_priv(dev); 349 struct stm32_rcc_regs *regs = priv->rcc_base; 350 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0); 351 uint32_t pllckselr = 0; 352 uint32_t pll1divr = 0; 353 uint32_t pllcfgr = 0; 354 355 /* Switch on HSI */ 356 setbits_le32(®s->cr, RCC_CR_HSION); 357 while (!(readl(®s->cr) & RCC_CR_HSIRDY)) 358 ; 359 360 /* Reset CFGR, now HSI is the default system clock */ 361 writel(0, ®s->cfgr); 362 363 /* Set all kernel domain clock registers to reset value*/ 364 writel(0x0, ®s->d1ccipr); 365 writel(0x0, ®s->d2ccip1r); 366 writel(0x0, ®s->d2ccip2r); 367 368 /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */ 369 clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK, 370 VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT); 371 /* Lock supply configuration update */ 372 clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN); 373 while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY)) 374 ; 375 376 /* disable HSE to configure it */ 377 clrbits_le32(®s->cr, RCC_CR_HSEON); 378 while ((readl(®s->cr) & RCC_CR_HSERDY)) 379 ; 380 381 /* clear HSE bypass and set it ON */ 382 clrbits_le32(®s->cr, RCC_CR_HSEBYP); 383 /* Switch on HSE */ 384 setbits_le32(®s->cr, RCC_CR_HSEON); 385 while (!(readl(®s->cr) & RCC_CR_HSERDY)) 386 ; 387 388 /* pll setup, disable it */ 389 clrbits_le32(®s->cr, RCC_CR_PLL1ON); 390 while ((readl(®s->cr) & RCC_CR_PLL1RDY)) 391 ; 392 393 /* Select HSE as PLL clock source */ 394 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE; 395 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; 396 writel(pllckselr, ®s->pllckselr); 397 398 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; 399 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; 400 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; 401 pll1divr |= (sys_pll_psc.divn - 1); 402 writel(pll1divr, ®s->pll1divr); 403 404 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT; 405 pllcfgr |= RCC_PLLCFGR_DIVP1EN; 406 pllcfgr |= RCC_PLLCFGR_DIVQ1EN; 407 pllcfgr |= RCC_PLLCFGR_DIVR1EN; 408 writel(pllcfgr, ®s->pllcfgr); 409 410 /* pll setup, enable it */ 411 setbits_le32(®s->cr, RCC_CR_PLL1ON); 412 413 /* set HPRE (/2) DI clk --> 125MHz */ 414 clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK, 415 RCC_D1CFGR_HPRE_DIV2); 416 417 /* select PLL1 as system clock source (sys_ck)*/ 418 clrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); 419 while ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) 420 ; 421 422 /* sdram: use pll1_q as fmc_k clk */ 423 clrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK, 424 FMCSRC_PLL1_Q_CK); 425 426 return 0; 427 } 428 429 static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs) 430 { 431 u32 divider; 432 433 /* get HSI divider value */ 434 divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK; 435 divider = divider >> RCC_CR_HSIDIV_SHIFT; 436 437 return divider; 438 }; 439 440 enum pllsrc { 441 HSE, 442 LSE, 443 HSI, 444 CSI, 445 I2S, 446 TIMER, 447 PLLSRC_NB, 448 }; 449 450 static const char * const pllsrc_name[PLLSRC_NB] = { 451 [HSE] = "clk-hse", 452 [LSE] = "clk-lse", 453 [HSI] = "clk-hsi", 454 [CSI] = "clk-csi", 455 [I2S] = "clk-i2s", 456 [TIMER] = "timer-clk" 457 }; 458 459 static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc) 460 { 461 struct clk clk; 462 struct udevice *fixed_clock_dev = NULL; 463 u32 divider; 464 int ret; 465 const char *name = pllsrc_name[pllsrc]; 466 467 debug("%s name %s\n", __func__, name); 468 469 clk.id = 0; 470 ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev); 471 if (ret) { 472 pr_err("Can't find clk %s (%d)", name, ret); 473 return 0; 474 } 475 476 ret = clk_request(fixed_clock_dev, &clk); 477 if (ret) { 478 pr_err("Can't request %s clk (%d)", name, ret); 479 return 0; 480 } 481 482 divider = 0; 483 if (pllsrc == HSI) 484 divider = stm32_get_HSI_divider(regs); 485 486 debug("%s divider %d rate %ld\n", __func__, 487 divider, clk_get_rate(&clk)); 488 489 return clk_get_rate(&clk) >> divider; 490 }; 491 492 enum pll1_output { 493 PLL1_P_CK, 494 PLL1_Q_CK, 495 PLL1_R_CK, 496 }; 497 498 static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, 499 enum pll1_output output) 500 { 501 ulong pllsrc = 0; 502 u32 divm1, divn1, divp1, divq1, divr1, fracn1; 503 ulong vco, rate; 504 505 /* get the PLLSRC */ 506 switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) { 507 case RCC_PLLCKSELR_PLLSRC_HSI: 508 pllsrc = stm32_get_rate(regs, HSI); 509 break; 510 case RCC_PLLCKSELR_PLLSRC_CSI: 511 pllsrc = stm32_get_rate(regs, CSI); 512 break; 513 case RCC_PLLCKSELR_PLLSRC_HSE: 514 pllsrc = stm32_get_rate(regs, HSE); 515 break; 516 case RCC_PLLCKSELR_PLLSRC_NO_CLK: 517 /* shouldn't happen */ 518 pr_err("wrong value for RCC_PLLCKSELR register\n"); 519 pllsrc = 0; 520 break; 521 } 522 523 /* pllsrc = 0 ? no need to go ahead */ 524 if (!pllsrc) 525 return pllsrc; 526 527 /* get divm1, divp1, divn1 and divr1 */ 528 divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; 529 divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT; 530 531 divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1; 532 533 divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK; 534 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1; 535 536 divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK; 537 divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1; 538 539 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; 540 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; 541 542 fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; 543 fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; 544 545 vco = (pllsrc / divm1) * divn1; 546 rate = (pllsrc * fracn1) / (divm1 * 8192); 547 548 debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n", 549 __func__, divm1, divn1, divp1, divq1, divr1); 550 debug("%s fracn1 = %d vco = %ld rate = %ld\n", 551 __func__, fracn1, vco, rate); 552 553 switch (output) { 554 case PLL1_P_CK: 555 return (vco + rate) / divp1; 556 break; 557 case PLL1_Q_CK: 558 return (vco + rate) / divq1; 559 break; 560 561 case PLL1_R_CK: 562 return (vco + rate) / divr1; 563 break; 564 } 565 566 return -EINVAL; 567 } 568 569 static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb) 570 { 571 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; 572 u32 d2cfgr = readl(®s->d2cfgr); 573 574 if (apb == APB1) { 575 if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) 576 /* get D2 domain APB1 prescaler */ 577 return prescaler_table[ 578 ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) 579 >> RCC_D2CFGR_D2PPRE1_SHIFT)]; 580 } else { /* APB2 */ 581 if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) 582 /* get D2 domain APB2 prescaler */ 583 return prescaler_table[ 584 ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) 585 >> RCC_D2CFGR_D2PPRE2_SHIFT)]; 586 } 587 588 return 1; 589 }; 590 591 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk, 592 enum apb apb) 593 { 594 struct stm32_rcc_regs *regs = priv->rcc_base; 595 u32 psc = stm32_get_apb_psc(regs, apb); 596 597 if (readl(®s->cfgr) & RCC_CFGR_TIMPRE) 598 /* 599 * if APB prescaler is configured to a 600 * division factor of 1, 2 or 4 601 */ 602 switch (psc) { 603 case 1: 604 case 2: 605 case 4: 606 return sysclk; 607 case 8: 608 return sysclk / 2; 609 case 16: 610 return sysclk / 4; 611 default: 612 pr_err("unexpected prescaler value (%d)\n", psc); 613 return 0; 614 } 615 else 616 switch (psc) { 617 case 1: 618 return sysclk; 619 case 2: 620 case 4: 621 case 8: 622 case 16: 623 return sysclk / psc; 624 default: 625 pr_err("unexpected prescaler value (%d)\n", psc); 626 return 0; 627 } 628 }; 629 630 static ulong stm32_clk_get_rate(struct clk *clk) 631 { 632 struct stm32_clk *priv = dev_get_priv(clk->dev); 633 struct stm32_rcc_regs *regs = priv->rcc_base; 634 ulong sysclk = 0; 635 u32 gate_offset; 636 u32 d1cfgr, d3cfgr; 637 /* prescaler table lookups for clock computation */ 638 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; 639 u8 source, idx; 640 641 /* 642 * get system clock (sys_ck) source 643 * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck 644 */ 645 source = readl(®s->cfgr) & RCC_CFGR_SW_MASK; 646 switch (source) { 647 case RCC_CFGR_SW_PLL1: 648 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK); 649 break; 650 case RCC_CFGR_SW_HSE: 651 sysclk = stm32_get_rate(regs, HSE); 652 break; 653 654 case RCC_CFGR_SW_CSI: 655 sysclk = stm32_get_rate(regs, CSI); 656 break; 657 658 case RCC_CFGR_SW_HSI: 659 sysclk = stm32_get_rate(regs, HSI); 660 break; 661 } 662 663 /* sysclk = 0 ? no need to go ahead */ 664 if (!sysclk) 665 return sysclk; 666 667 debug("%s system clock: source = %d freq = %ld\n", 668 __func__, source, sysclk); 669 670 d1cfgr = readl(®s->d1cfgr); 671 672 if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) { 673 /* get D1 domain Core prescaler */ 674 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >> 675 RCC_D1CFGR_D1CPRE_SHIFT; 676 sysclk = sysclk / prescaler_table[idx]; 677 } 678 679 if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) { 680 /* get D1 domain AHB prescaler */ 681 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER; 682 sysclk = sysclk / prescaler_table[idx]; 683 } 684 685 gate_offset = clk_map[clk->id].gate_offset; 686 687 debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n", 688 __func__, clk->id, gate_offset, sysclk); 689 690 switch (gate_offset) { 691 case RCC_AHB3ENR: 692 case RCC_AHB1ENR: 693 case RCC_AHB2ENR: 694 case RCC_AHB4ENR: 695 return sysclk; 696 break; 697 698 case RCC_APB3ENR: 699 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) { 700 /* get D1 domain APB3 prescaler */ 701 idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >> 702 RCC_D1CFGR_D1PPRE_SHIFT; 703 sysclk = sysclk / prescaler_table[idx]; 704 } 705 706 debug("%s system clock: freq after APB3 prescaler = %ld\n", 707 __func__, sysclk); 708 709 return sysclk; 710 break; 711 712 case RCC_APB4ENR: 713 d3cfgr = readl(®s->d3cfgr); 714 if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { 715 /* get D3 domain APB4 prescaler */ 716 idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> 717 RCC_D3CFGR_D3PPRE_SHIFT; 718 sysclk = sysclk / prescaler_table[idx]; 719 } 720 721 debug("%s system clock: freq after APB4 prescaler = %ld\n", 722 __func__, sysclk); 723 724 return sysclk; 725 break; 726 727 case RCC_APB1LENR: 728 case RCC_APB1HENR: 729 /* special case for GPT timers */ 730 switch (clk->id) { 731 case TIM14_CK: 732 case TIM13_CK: 733 case TIM12_CK: 734 case TIM7_CK: 735 case TIM6_CK: 736 case TIM5_CK: 737 case TIM4_CK: 738 case TIM3_CK: 739 case TIM2_CK: 740 return stm32_get_timer_rate(priv, sysclk, APB1); 741 } 742 743 debug("%s system clock: freq after APB1 prescaler = %ld\n", 744 __func__, sysclk); 745 746 return (sysclk / stm32_get_apb_psc(regs, APB1)); 747 break; 748 749 case RCC_APB2ENR: 750 /* special case for timers */ 751 switch (clk->id) { 752 case TIM17_CK: 753 case TIM16_CK: 754 case TIM15_CK: 755 case TIM8_CK: 756 case TIM1_CK: 757 return stm32_get_timer_rate(priv, sysclk, APB2); 758 } 759 760 debug("%s system clock: freq after APB2 prescaler = %ld\n", 761 __func__, sysclk); 762 763 return (sysclk / stm32_get_apb_psc(regs, APB2)); 764 765 break; 766 767 default: 768 pr_err("unexpected gate_offset value (0x%x)\n", gate_offset); 769 return -EINVAL; 770 break; 771 } 772 } 773 774 static int stm32_clk_enable(struct clk *clk) 775 { 776 struct stm32_clk *priv = dev_get_priv(clk->dev); 777 struct stm32_rcc_regs *regs = priv->rcc_base; 778 u32 gate_offset; 779 u32 gate_bit_index; 780 unsigned long clk_id = clk->id; 781 782 gate_offset = clk_map[clk_id].gate_offset; 783 gate_bit_index = clk_map[clk_id].gate_bit_idx; 784 785 debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n", 786 __func__, clk->id, gate_offset, gate_bit_index, 787 clk_map[clk_id].name); 788 789 setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index)); 790 791 return 0; 792 } 793 794 static int stm32_clk_probe(struct udevice *dev) 795 { 796 struct stm32_clk *priv = dev_get_priv(dev); 797 struct udevice *syscon; 798 fdt_addr_t addr; 799 int err; 800 801 addr = dev_read_addr(dev); 802 if (addr == FDT_ADDR_T_NONE) 803 return -EINVAL; 804 805 priv->rcc_base = (struct stm32_rcc_regs *)addr; 806 807 /* get corresponding syscon phandle */ 808 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 809 "st,syscfg", &syscon); 810 811 if (err) { 812 pr_err("unable to find syscon device\n"); 813 return err; 814 } 815 816 priv->pwr_regmap = syscon_get_regmap(syscon); 817 if (!priv->pwr_regmap) { 818 pr_err("unable to find regmap\n"); 819 return -ENODEV; 820 } 821 822 configure_clocks(dev); 823 824 return 0; 825 } 826 827 static int stm32_clk_of_xlate(struct clk *clk, 828 struct ofnode_phandle_args *args) 829 { 830 if (args->args_count != 1) { 831 debug("Invaild args_count: %d\n", args->args_count); 832 return -EINVAL; 833 } 834 835 if (args->args_count) { 836 clk->id = args->args[0]; 837 /* 838 * this computation convert DT clock index which is used to 839 * point into 2 separate clock arrays (peripheral and kernel 840 * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h) 841 * into index to point into only one array where peripheral 842 * and kernel clocks are consecutive 843 */ 844 if (clk->id >= KERN_BANK) { 845 clk->id -= KERN_BANK; 846 clk->id += LAST_PERIF_BANK - PERIF_BANK + 1; 847 } else { 848 clk->id -= PERIF_BANK; 849 } 850 } else { 851 clk->id = 0; 852 } 853 854 debug("%s clk->id %ld\n", __func__, clk->id); 855 856 return 0; 857 } 858 859 static struct clk_ops stm32_clk_ops = { 860 .of_xlate = stm32_clk_of_xlate, 861 .enable = stm32_clk_enable, 862 .get_rate = stm32_clk_get_rate, 863 }; 864 865 U_BOOT_DRIVER(stm32h7_clk) = { 866 .name = "stm32h7_rcc_clock", 867 .id = UCLASS_CLK, 868 .ops = &stm32_clk_ops, 869 .probe = stm32_clk_probe, 870 .priv_auto_alloc_size = sizeof(struct stm32_clk), 871 .flags = DM_FLAG_PRE_RELOC, 872 }; 873