1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Google, Inc 4 * Written by Simon Glass <sjg@chromium.org> 5 * Copyright (c) 2016, NVIDIA CORPORATION. 6 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <clk-uclass.h> 12 #include <dm.h> 13 #include <dm/read.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 17 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev) 18 { 19 return (const struct clk_ops *)dev->driver->ops; 20 } 21 22 #if CONFIG_IS_ENABLED(OF_CONTROL) 23 # if CONFIG_IS_ENABLED(OF_PLATDATA) 24 int clk_get_by_index_platdata(struct udevice *dev, int index, 25 struct phandle_1_arg *cells, struct clk *clk) 26 { 27 int ret; 28 29 if (index != 0) 30 return -ENOSYS; 31 ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); 32 if (ret) 33 return ret; 34 clk->id = cells[0].arg[0]; 35 36 return 0; 37 } 38 # else 39 static int clk_of_xlate_default(struct clk *clk, 40 struct ofnode_phandle_args *args) 41 { 42 debug("%s(clk=%p)\n", __func__, clk); 43 44 if (args->args_count > 1) { 45 debug("Invaild args_count: %d\n", args->args_count); 46 return -EINVAL; 47 } 48 49 if (args->args_count) 50 clk->id = args->args[0]; 51 else 52 clk->id = 0; 53 54 return 0; 55 } 56 57 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, 58 int index, struct clk *clk) 59 { 60 int ret; 61 struct ofnode_phandle_args args; 62 struct udevice *dev_clk; 63 const struct clk_ops *ops; 64 65 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk); 66 67 assert(clk); 68 clk->dev = NULL; 69 70 ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0, 71 index, &args); 72 if (ret) { 73 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n", 74 __func__, ret); 75 return ret; 76 } 77 78 ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk); 79 if (ret) { 80 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", 81 __func__, ret); 82 return ret; 83 } 84 85 clk->dev = dev_clk; 86 87 ops = clk_dev_ops(dev_clk); 88 89 if (ops->of_xlate) 90 ret = ops->of_xlate(clk, &args); 91 else 92 ret = clk_of_xlate_default(clk, &args); 93 if (ret) { 94 debug("of_xlate() failed: %d\n", ret); 95 return ret; 96 } 97 98 return clk_request(dev_clk, clk); 99 } 100 101 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) 102 { 103 return clk_get_by_indexed_prop(dev, "clocks", index, clk); 104 } 105 106 int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) 107 { 108 int i, ret, err, count; 109 110 bulk->count = 0; 111 112 count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); 113 if (count < 1) 114 return count; 115 116 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL); 117 if (!bulk->clks) 118 return -ENOMEM; 119 120 for (i = 0; i < count; i++) { 121 ret = clk_get_by_index(dev, i, &bulk->clks[i]); 122 if (ret < 0) 123 goto bulk_get_err; 124 125 ++bulk->count; 126 } 127 128 return 0; 129 130 bulk_get_err: 131 err = clk_release_all(bulk->clks, bulk->count); 132 if (err) 133 debug("%s: could release all clocks for %p\n", 134 __func__, dev); 135 136 return ret; 137 } 138 139 static int clk_set_default_parents(struct udevice *dev) 140 { 141 struct clk clk, parent_clk; 142 int index; 143 int num_parents; 144 int ret; 145 146 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents", 147 "#clock-cells"); 148 if (num_parents < 0) { 149 debug("%s: could not read assigned-clock-parents for %p\n", 150 __func__, dev); 151 return 0; 152 } 153 154 for (index = 0; index < num_parents; index++) { 155 ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents", 156 index, &parent_clk); 157 /* If -ENOENT, this is a no-op entry */ 158 if (ret == -ENOENT) 159 continue; 160 161 if (ret) { 162 debug("%s: could not get parent clock %d for %s\n", 163 __func__, index, dev_read_name(dev)); 164 return ret; 165 } 166 167 ret = clk_get_by_indexed_prop(dev, "assigned-clocks", 168 index, &clk); 169 if (ret) { 170 debug("%s: could not get assigned clock %d for %s\n", 171 __func__, index, dev_read_name(dev)); 172 return ret; 173 } 174 175 ret = clk_set_parent(&clk, &parent_clk); 176 177 /* 178 * Not all drivers may support clock-reparenting (as of now). 179 * Ignore errors due to this. 180 */ 181 if (ret == -ENOSYS) 182 continue; 183 184 if (ret) { 185 debug("%s: failed to reparent clock %d for %s\n", 186 __func__, index, dev_read_name(dev)); 187 return ret; 188 } 189 } 190 191 return 0; 192 } 193 194 static int clk_set_default_rates(struct udevice *dev) 195 { 196 struct clk clk; 197 int index; 198 int num_rates; 199 int size; 200 int ret = 0; 201 u32 *rates = NULL; 202 203 size = dev_read_size(dev, "assigned-clock-rates"); 204 if (size < 0) 205 return 0; 206 207 num_rates = size / sizeof(u32); 208 rates = calloc(num_rates, sizeof(u32)); 209 if (!rates) 210 return -ENOMEM; 211 212 ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates); 213 if (ret) 214 goto fail; 215 216 for (index = 0; index < num_rates; index++) { 217 /* If 0 is passed, this is a no-op */ 218 if (!rates[index]) 219 continue; 220 221 ret = clk_get_by_indexed_prop(dev, "assigned-clocks", 222 index, &clk); 223 if (ret) { 224 debug("%s: could not get assigned clock %d for %s\n", 225 __func__, index, dev_read_name(dev)); 226 continue; 227 } 228 229 ret = clk_set_rate(&clk, rates[index]); 230 if (ret < 0) { 231 debug("%s: failed to set rate on clock %d for %s\n", 232 __func__, index, dev_read_name(dev)); 233 break; 234 } 235 } 236 237 fail: 238 free(rates); 239 return ret; 240 } 241 242 int clk_set_defaults(struct udevice *dev) 243 { 244 int ret; 245 246 /* If this not in SPL and pre-reloc state, don't take any action. */ 247 if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC))) 248 return 0; 249 250 debug("%s(%s)\n", __func__, dev_read_name(dev)); 251 252 ret = clk_set_default_parents(dev); 253 if (ret) 254 return ret; 255 256 ret = clk_set_default_rates(dev); 257 if (ret < 0) 258 return ret; 259 260 return 0; 261 } 262 # endif /* OF_PLATDATA */ 263 264 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) 265 { 266 int index; 267 268 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk); 269 clk->dev = NULL; 270 271 index = dev_read_stringlist_search(dev, "clock-names", name); 272 if (index < 0) { 273 debug("fdt_stringlist_search() failed: %d\n", index); 274 return index; 275 } 276 277 return clk_get_by_index(dev, index, clk); 278 } 279 280 int clk_release_all(struct clk *clk, int count) 281 { 282 int i, ret; 283 284 for (i = 0; i < count; i++) { 285 debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]); 286 287 /* check if clock has been previously requested */ 288 if (!clk[i].dev) 289 continue; 290 291 ret = clk_disable(&clk[i]); 292 if (ret && ret != -ENOSYS) 293 return ret; 294 295 ret = clk_free(&clk[i]); 296 if (ret && ret != -ENOSYS) 297 return ret; 298 } 299 300 return 0; 301 } 302 303 #endif /* OF_CONTROL */ 304 305 int clk_request(struct udevice *dev, struct clk *clk) 306 { 307 const struct clk_ops *ops = clk_dev_ops(dev); 308 309 debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk); 310 311 clk->dev = dev; 312 313 if (!ops->request) 314 return 0; 315 316 return ops->request(clk); 317 } 318 319 int clk_free(struct clk *clk) 320 { 321 const struct clk_ops *ops = clk_dev_ops(clk->dev); 322 323 debug("%s(clk=%p)\n", __func__, clk); 324 325 if (!ops->free) 326 return 0; 327 328 return ops->free(clk); 329 } 330 331 ulong clk_get_rate(struct clk *clk) 332 { 333 const struct clk_ops *ops = clk_dev_ops(clk->dev); 334 335 debug("%s(clk=%p)\n", __func__, clk); 336 337 if (!ops->get_rate) 338 return -ENOSYS; 339 340 return ops->get_rate(clk); 341 } 342 343 ulong clk_set_rate(struct clk *clk, ulong rate) 344 { 345 const struct clk_ops *ops = clk_dev_ops(clk->dev); 346 347 debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); 348 349 if (!ops->set_rate) 350 return -ENOSYS; 351 352 return ops->set_rate(clk, rate); 353 } 354 355 int clk_set_parent(struct clk *clk, struct clk *parent) 356 { 357 const struct clk_ops *ops = clk_dev_ops(clk->dev); 358 359 debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent); 360 361 if (!ops->set_parent) 362 return -ENOSYS; 363 364 return ops->set_parent(clk, parent); 365 } 366 367 int clk_enable(struct clk *clk) 368 { 369 const struct clk_ops *ops = clk_dev_ops(clk->dev); 370 371 debug("%s(clk=%p)\n", __func__, clk); 372 373 if (!ops->enable) 374 return -ENOSYS; 375 376 return ops->enable(clk); 377 } 378 379 int clk_enable_bulk(struct clk_bulk *bulk) 380 { 381 int i, ret; 382 383 for (i = 0; i < bulk->count; i++) { 384 ret = clk_enable(&bulk->clks[i]); 385 if (ret < 0 && ret != -ENOSYS) 386 return ret; 387 } 388 389 return 0; 390 } 391 392 int clk_disable(struct clk *clk) 393 { 394 const struct clk_ops *ops = clk_dev_ops(clk->dev); 395 396 debug("%s(clk=%p)\n", __func__, clk); 397 398 if (!ops->disable) 399 return -ENOSYS; 400 401 return ops->disable(clk); 402 } 403 404 int clk_disable_bulk(struct clk_bulk *bulk) 405 { 406 int i, ret; 407 408 for (i = 0; i < bulk->count; i++) { 409 ret = clk_disable(&bulk->clks[i]); 410 if (ret < 0 && ret != -ENOSYS) 411 return ret; 412 } 413 414 return 0; 415 } 416 417 UCLASS_DRIVER(clk) = { 418 .id = UCLASS_CLK, 419 .name = "clk", 420 }; 421