xref: /openbmc/u-boot/drivers/clk/at91/clk-utmi.c (revision a3b36c84) 
1 /*
2  * Copyright (C) 2016 Atmel Corporation
3  *               Wenyou.Yang <wenyou.yang@atmel.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <syscon.h>
12 #include <linux/io.h>
13 #include <mach/at91_pmc.h>
14 #include <mach/sama5_sfr.h>
15 #include "pmc.h"
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 /*
20  * The purpose of this clock is to generate a 480 MHz signal. A different
21  * rate can't be configured.
22  */
23 #define UTMI_RATE	480000000
24 
25 static int utmi_clk_enable(struct clk *clk)
26 {
27 	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
28 	struct at91_pmc *pmc = plat->reg_base;
29 	struct clk clk_dev;
30 	ulong clk_rate;
31 	u32 utmi_ref_clk_freq;
32 	u32 tmp;
33 	int err;
34 
35 	if (readl(&pmc->sr) & AT91_PMC_LOCKU)
36 		return 0;
37 
38 	/*
39 	 * If mainck rate is different from 12 MHz, we have to configure the
40 	 * FREQ field of the SFR_UTMICKTRIM register to generate properly
41 	 * the utmi clock.
42 	 */
43 	err = clk_get_by_index(clk->dev, 0, &clk_dev);
44 	if (err)
45 		return -EINVAL;
46 
47 	clk_rate = clk_get_rate(&clk_dev);
48 	switch (clk_rate) {
49 	case 12000000:
50 		utmi_ref_clk_freq = 0;
51 		break;
52 	case 16000000:
53 		utmi_ref_clk_freq = 1;
54 		break;
55 	case 24000000:
56 		utmi_ref_clk_freq = 2;
57 		break;
58 	/*
59 	 * Not supported on SAMA5D2 but it's not an issue since MAINCK
60 	 * maximum value is 24 MHz.
61 	 */
62 	case 48000000:
63 		utmi_ref_clk_freq = 3;
64 		break;
65 	default:
66 		printf("UTMICK: unsupported mainck rate\n");
67 		return -EINVAL;
68 	}
69 
70 	if (plat->regmap_sfr) {
71 		err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
72 		if (err)
73 			return -EINVAL;
74 
75 		tmp &= ~AT91_UTMICKTRIM_FREQ;
76 		tmp |= utmi_ref_clk_freq;
77 		err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
78 		if (err)
79 			return -EINVAL;
80 	} else if (utmi_ref_clk_freq) {
81 		printf("UTMICK: sfr node required\n");
82 		return -EINVAL;
83 	}
84 
85 	tmp = readl(&pmc->uckr);
86 	tmp |= AT91_PMC_UPLLEN |
87 	       AT91_PMC_UPLLCOUNT |
88 	       AT91_PMC_BIASEN;
89 	writel(tmp, &pmc->uckr);
90 
91 	while (!(readl(&pmc->sr) & AT91_PMC_LOCKU))
92 		;
93 
94 	return 0;
95 }
96 
97 static ulong utmi_clk_get_rate(struct clk *clk)
98 {
99 	/* UTMI clk rate is fixed. */
100 	return UTMI_RATE;
101 }
102 
103 static struct clk_ops utmi_clk_ops = {
104 	.enable = utmi_clk_enable,
105 	.get_rate = utmi_clk_get_rate,
106 };
107 
108 static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
109 {
110 	struct pmc_platdata *plat = dev_get_platdata(dev);
111 	struct udevice *syscon;
112 
113 	uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
114 				     "regmap-sfr", &syscon);
115 
116 	if (syscon)
117 		plat->regmap_sfr = syscon_get_regmap(syscon);
118 
119 	return 0;
120 }
121 
122 static int utmi_clk_probe(struct udevice *dev)
123 {
124 	return at91_pmc_core_probe(dev);
125 }
126 
127 static const struct udevice_id utmi_clk_match[] = {
128 	{ .compatible = "atmel,at91sam9x5-clk-utmi" },
129 	{}
130 };
131 
132 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
133 	.name = "at91sam9x5-utmi-clk",
134 	.id = UCLASS_CLK,
135 	.of_match = utmi_clk_match,
136 	.probe = utmi_clk_probe,
137 	.ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
138 	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
139 	.ops = &utmi_clk_ops,
140 };
141