1 /*
2  * Copyright (C) 2016 Atmel Corporation
3  *               Wenyou.Yang <wenyou.yang@atmel.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <clk-uclass.h>
10 #include <dm.h>
11 #include <linux/io.h>
12 #include <mach/at91_pmc.h>
13 #include "pmc.h"
14 
15 #define PERIPHERAL_ID_MIN	2
16 #define PERIPHERAL_ID_MAX	31
17 #define PERIPHERAL_MASK(id)	(1 << ((id) & PERIPHERAL_ID_MAX))
18 
19 enum periph_clk_type {
20 	CLK_PERIPH_AT91RM9200 = 0,
21 	CLK_PERIPH_AT91SAM9X5,
22 };
23 /**
24  * sam9x5_periph_clk_bind() - for the periph clock driver
25  * Recursively bind its children as clk devices.
26  *
27  * @return: 0 on success, or negative error code on failure
28  */
29 static int sam9x5_periph_clk_bind(struct udevice *dev)
30 {
31 	return at91_clk_sub_device_bind(dev, "periph-clk");
32 }
33 
34 static const struct udevice_id sam9x5_periph_clk_match[] = {
35 	{
36 		.compatible = "atmel,at91rm9200-clk-peripheral",
37 		.data = CLK_PERIPH_AT91RM9200,
38 	},
39 	{
40 		.compatible = "atmel,at91sam9x5-clk-peripheral",
41 		.data = CLK_PERIPH_AT91SAM9X5,
42 	},
43 	{}
44 };
45 
46 U_BOOT_DRIVER(sam9x5_periph_clk) = {
47 	.name = "sam9x5-periph-clk",
48 	.id = UCLASS_MISC,
49 	.of_match = sam9x5_periph_clk_match,
50 	.bind = sam9x5_periph_clk_bind,
51 };
52 
53 /*---------------------------------------------------------*/
54 
55 static int periph_clk_enable(struct clk *clk)
56 {
57 	struct pmc_platdata *plat = dev_get_platdata(clk->dev);
58 	struct at91_pmc *pmc = plat->reg_base;
59 	enum periph_clk_type clk_type;
60 	void *addr;
61 
62 	if (clk->id < PERIPHERAL_ID_MIN)
63 		return -1;
64 
65 	clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
66 	if (clk_type == CLK_PERIPH_AT91RM9200) {
67 		addr = &pmc->pcer;
68 		if (clk->id > PERIPHERAL_ID_MAX)
69 			addr = &pmc->pcer1;
70 
71 		setbits_le32(addr, PERIPHERAL_MASK(clk->id));
72 	} else {
73 		writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
74 		setbits_le32(&pmc->pcr,
75 			     AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
76 	}
77 
78 	return 0;
79 }
80 
81 static ulong periph_get_rate(struct clk *clk)
82 {
83 	struct udevice *dev;
84 	struct clk clk_dev;
85 	ulong clk_rate;
86 	int ret;
87 
88 	dev = dev_get_parent(clk->dev);
89 
90 	ret = clk_get_by_index(dev, 0, &clk_dev);
91 	if (ret)
92 		return ret;
93 
94 	clk_rate = clk_get_rate(&clk_dev);
95 
96 	clk_free(&clk_dev);
97 
98 	return clk_rate;
99 }
100 
101 static struct clk_ops periph_clk_ops = {
102 	.of_xlate = at91_clk_of_xlate,
103 	.enable = periph_clk_enable,
104 	.get_rate = periph_get_rate,
105 };
106 
107 U_BOOT_DRIVER(clk_periph) = {
108 	.name	= "periph-clk",
109 	.id	= UCLASS_CLK,
110 	.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
111 	.probe = at91_clk_probe,
112 	.ops	= &periph_clk_ops,
113 };
114