1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 {.in = AST2600_CLK_IN, .out = 400000000, 77 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 78 .cfg.ext_reg = 0x31, 79 }, 80 {.in = AST2600_CLK_IN, .out = 200000000, 81 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 82 .cfg.ext_reg = 0x3f 83 }, 84 {.in = AST2600_CLK_IN, .out = 334000000, 85 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 86 .cfg.ext_reg = 0x14d 87 }, 88 89 {.in = AST2600_CLK_IN, .out = 1000000000, 90 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 91 .cfg.ext_reg = 0x3d 92 }, 93 94 {.in = AST2600_CLK_IN, .out = 50000000, 95 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 96 .cfg.ext_reg = 0x31 97 }, 98 }; 99 100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 101 { 102 u32 clkin = AST2600_CLK_IN; 103 u32 pll_reg = 0; 104 unsigned int mult, div = 1; 105 106 switch(pll_idx) { 107 case ASPEED_CLK_HPLL: 108 pll_reg = readl(&scu->h_pll_param); 109 break; 110 case ASPEED_CLK_MPLL: 111 pll_reg = readl(&scu->m_pll_param); 112 break; 113 case ASPEED_CLK_DPLL: 114 pll_reg = readl(&scu->d_pll_param); 115 break; 116 case ASPEED_CLK_EPLL: 117 pll_reg = readl(&scu->e_pll_param); 118 break; 119 } 120 if (pll_reg & BIT(24)) { 121 /* Pass through mode */ 122 mult = div = 1; 123 } else { 124 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 125 union ast2600_pll_reg reg; 126 reg.w = pll_reg; 127 if(pll_idx == ASPEED_CLK_HPLL) { 128 /* 129 HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 130 fix 0xBF when SCU500[10]=0 and SCU500[8]=1 131 SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 132 HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 133 HPLL Divider (P) = SCU200[22:19] (default 0x0) 134 HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 135 fix 0x5F when SCU500[10]=0 and SCU500[8]=1 136 SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 137 */ 138 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 139 if(hwstrap1 & BIT(10)) 140 reg.b.m = 0x5F; 141 else { 142 if(hwstrap1 & BIT(8)) 143 reg.b.m = 0xBF; 144 //otherwise keep default 0x8F 145 } 146 } 147 mult = (reg.b.m + 1) / (reg.b.n + 1); 148 div = (reg.b.p + 1); 149 } 150 return ((clkin * mult)/div); 151 } 152 153 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 154 { 155 u32 clkin = AST2600_CLK_IN; 156 u32 apll_reg = readl(&scu->a_pll_param); 157 unsigned int mult, div = 1; 158 159 if (apll_reg & BIT(20)) { 160 /* Pass through mode */ 161 mult = div = 1; 162 } else { 163 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 164 u32 m = (apll_reg >> 5) & 0x3f; 165 u32 od = (apll_reg >> 4) & 0x1; 166 u32 n = apll_reg & 0xf; 167 168 mult = (2 - od) * (m + 2); 169 div = n + 1; 170 } 171 return ((clkin * mult)/div); 172 } 173 174 static u32 ast2600_a0_axi_ahb_div_table[] = { 175 2, 2, 3, 4, 176 }; 177 178 static u32 ast2600_a1_axi_ahb_div0_table[] = { 179 3, 2, 3, 4, 180 }; 181 182 static u32 ast2600_a1_axi_ahb_div1_table[] = { 183 3, 4, 6, 8, 184 }; 185 186 static u32 ast2600_a1_axi_ahb_default_table[] = { 187 3, 4, 3, 4, 2, 2, 2, 2, 188 }; 189 190 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 191 { 192 u32 hw_rev = readl(&scu->chip_id0); 193 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 194 u32 axi_div = 1; 195 u32 ahb_div = 0; 196 u32 rate = 0; 197 198 if (hw_rev & BIT(16)) { 199 //ast2600a1 200 if(hwstrap1 & BIT(16)) { 201 ast2600_a1_axi_ahb_div1_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 202 axi_div = 1; 203 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 204 } else { 205 ast2600_a1_axi_ahb_div0_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 206 axi_div = 2; 207 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 208 } 209 } else { 210 //ast2600a0 : fix axi = hpll / 2 211 axi_div = 2; 212 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 213 } 214 215 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 216 return (rate / axi_div / ahb_div); 217 } 218 219 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 220 { 221 u32 rate; 222 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 223 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 224 225 return (rate /((bclk_sel + 1) * 4)); 226 } 227 228 static u32 ast2600_hpll_pclk1_div_table[] = { 229 4, 8, 12, 16, 20, 24, 28, 32, 230 }; 231 232 static u32 ast2600_hpll_pclk2_div_table[] = { 233 2, 4, 6, 8, 10, 12, 14, 16, 234 }; 235 236 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 237 { 238 u32 clk_sel1 = readl(&scu->clk_sel1); 239 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 240 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 241 242 return (rate / apb_div); 243 } 244 245 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 246 { 247 u32 clk_sel4 = readl(&scu->clk_sel4); 248 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 249 u32 rate = ast2600_get_hclk(scu); 250 251 return (rate / apb_div); 252 } 253 254 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 255 { 256 u32 clk_in = 0; 257 u32 uxclk_sel = readl(&scu->clk_sel5); 258 259 uxclk_sel &= 0x3; 260 switch(uxclk_sel) { 261 case 0: 262 clk_in = ast2600_get_apll_rate(scu) / 4; 263 break; 264 case 1: 265 clk_in = ast2600_get_apll_rate(scu) / 2; 266 break; 267 case 2: 268 clk_in = ast2600_get_apll_rate(scu); 269 break; 270 case 3: 271 clk_in = ast2600_get_hclk(scu); 272 break; 273 } 274 275 return clk_in; 276 } 277 278 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 279 { 280 u32 clk_in = 0; 281 u32 huclk_sel = readl(&scu->clk_sel5); 282 283 huclk_sel = ((huclk_sel >> 3) & 0x3); 284 switch(huclk_sel) { 285 case 0: 286 clk_in = ast2600_get_apll_rate(scu) / 4; 287 break; 288 case 1: 289 clk_in = ast2600_get_apll_rate(scu) / 2; 290 break; 291 case 2: 292 clk_in = ast2600_get_apll_rate(scu); 293 break; 294 case 3: 295 clk_in = ast2600_get_hclk(scu); 296 break; 297 } 298 299 return clk_in; 300 } 301 302 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 303 { 304 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 305 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 306 unsigned int mult, div; 307 308 u32 n = (div_reg >> 8) & 0x3ff; 309 u32 r = div_reg & 0xff; 310 311 mult = r; 312 div = (n * 2); 313 return (clk_in * mult)/div; 314 } 315 316 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 317 { 318 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 319 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 320 321 unsigned int mult, div; 322 323 u32 n = (div_reg >> 8) & 0x3ff; 324 u32 r = div_reg & 0xff; 325 326 mult = r; 327 div = (n * 2); 328 return (clk_in * mult)/div; 329 } 330 331 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 332 { 333 u32 clkin = 0; 334 u32 clk_sel = readl(&scu->clk_sel4); 335 u32 div = (clk_sel >> 28) & 0x7; 336 337 if(clk_sel & BIT(8)) { 338 clkin = ast2600_get_apll_rate(scu); 339 } else { 340 clkin = ast2600_get_hclk(scu); 341 } 342 div = (div + 1) << 1; 343 344 return (clkin / div); 345 } 346 347 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 348 { 349 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 350 u32 clk_sel = readl(&scu->clk_sel1); 351 u32 div = (clk_sel >> 12) & 0x7; 352 353 div = (div + 1) << 2; 354 355 return (clkin / div); 356 } 357 358 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 359 { 360 u32 uart_sel = readl(&scu->clk_sel4); 361 u32 uart_sel5 = readl(&scu->clk_sel5); 362 ulong uart_clk = 0; 363 364 switch(uart_idx) { 365 case 1: 366 case 2: 367 case 3: 368 case 4: 369 case 6: 370 if(uart_sel & BIT(uart_idx - 1)) 371 uart_clk = ast2600_get_uart_huxclk_rate(scu) ; 372 else 373 uart_clk = ast2600_get_uart_uxclk_rate(scu) ; 374 break; 375 case 5: //24mhz is come form usb phy 48Mhz 376 { 377 u8 uart5_clk_sel = 0; 378 //high bit 379 if (readl(&scu->misc_ctrl1) & BIT(12)) 380 uart5_clk_sel = 0x2; 381 else 382 uart5_clk_sel = 0x0; 383 384 if (readl(&scu->clk_sel2) & BIT(14)) 385 uart5_clk_sel |= 0x1; 386 387 switch(uart5_clk_sel) { 388 case 0: 389 uart_clk = 24000000; 390 break; 391 case 1: 392 uart_clk = 192000000; 393 break; 394 case 2: 395 uart_clk = 24000000/13; 396 break; 397 case 3: 398 uart_clk = 192000000/13; 399 break; 400 } 401 } 402 break; 403 case 7: 404 case 8: 405 case 9: 406 case 10: 407 case 11: 408 case 12: 409 case 13: 410 if(uart_sel5 & BIT(uart_idx - 1)) 411 uart_clk = ast2600_get_uart_huxclk_rate(scu); 412 else 413 uart_clk = ast2600_get_uart_uxclk_rate(scu); 414 break; 415 } 416 417 return uart_clk; 418 } 419 420 static ulong ast2600_clk_get_rate(struct clk *clk) 421 { 422 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 423 ulong rate = 0; 424 425 switch (clk->id) { 426 case ASPEED_CLK_HPLL: 427 case ASPEED_CLK_EPLL: 428 case ASPEED_CLK_DPLL: 429 case ASPEED_CLK_MPLL: 430 rate = ast2600_get_pll_rate(priv->scu, clk->id); 431 break; 432 case ASPEED_CLK_AHB: 433 rate = ast2600_get_hclk(priv->scu); 434 break; 435 case ASPEED_CLK_APB1: 436 rate = ast2600_get_pclk1(priv->scu); 437 break; 438 case ASPEED_CLK_APB2: 439 rate = ast2600_get_pclk2(priv->scu); 440 break; 441 case ASPEED_CLK_APLL: 442 rate = ast2600_get_apll_rate(priv->scu); 443 break; 444 case ASPEED_CLK_GATE_UART1CLK: 445 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 446 break; 447 case ASPEED_CLK_GATE_UART2CLK: 448 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 449 break; 450 case ASPEED_CLK_GATE_UART3CLK: 451 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 452 break; 453 case ASPEED_CLK_GATE_UART4CLK: 454 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 455 break; 456 case ASPEED_CLK_GATE_UART5CLK: 457 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 458 break; 459 case ASPEED_CLK_BCLK: 460 rate = ast2600_get_bclk_rate(priv->scu); 461 break; 462 case ASPEED_CLK_SDIO: 463 rate = ast2600_get_sdio_clk_rate(priv->scu); 464 break; 465 case ASPEED_CLK_EMMC: 466 rate = ast2600_get_emmc_clk_rate(priv->scu); 467 break; 468 case ASPEED_CLK_UARTX: 469 rate = ast2600_get_uart_uxclk_rate(priv->scu); 470 break; 471 case ASPEED_CLK_HUARTX: 472 rate = ast2600_get_uart_huxclk_rate(priv->scu); 473 break; 474 default: 475 pr_debug("can't get clk rate \n"); 476 return -ENOENT; 477 break; 478 } 479 480 return rate; 481 } 482 483 /** 484 * @brief lookup PLL divider config by input/output rate 485 * @param[in] *pll - PLL descriptor 486 * @return true - if PLL divider config is found, false - else 487 * 488 * The function caller shall fill "pll->in" and "pll->out", then this function 489 * will search the lookup table to find a valid PLL divider configuration. 490 */ 491 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 492 { 493 u32 i; 494 bool is_found = false; 495 496 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 497 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 498 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 499 is_found = true; 500 pll->cfg.reg.w = def_cfg->cfg.reg.w; 501 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 502 break; 503 } 504 } 505 return is_found; 506 } 507 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 508 struct ast2600_pll_cfg *p_cfg, int pll_idx) 509 { 510 u32 addr, addr_ext; 511 u32 reg; 512 513 switch (pll_idx) { 514 case ASPEED_CLK_HPLL: 515 addr = (u32)(&scu->h_pll_param); 516 addr_ext = (u32)(&scu->h_pll_ext_param); 517 break; 518 case ASPEED_CLK_MPLL: 519 addr = (u32)(&scu->m_pll_param); 520 addr_ext = (u32)(&scu->m_pll_ext_param); 521 break; 522 case ASPEED_CLK_DPLL: 523 addr = (u32)(&scu->d_pll_param); 524 addr_ext = (u32)(&scu->d_pll_ext_param); 525 break; 526 case ASPEED_CLK_EPLL: 527 addr = (u32)(&scu->e_pll_param); 528 addr_ext = (u32)(&scu->e_pll_ext_param); 529 break; 530 default: 531 debug("unknown PLL index\n"); 532 return 1; 533 } 534 535 p_cfg->reg.b.bypass = 0; 536 p_cfg->reg.b.off = 1; 537 p_cfg->reg.b.reset = 1; 538 539 reg = readl(addr); 540 reg &= ~GENMASK(25, 0); 541 reg |= p_cfg->reg.w; 542 writel(reg, addr); 543 544 /* write extend parameter */ 545 writel(p_cfg->ext_reg, addr_ext); 546 udelay(100); 547 p_cfg->reg.b.off = 0; 548 p_cfg->reg.b.reset = 0; 549 reg &= ~GENMASK(25, 0); 550 reg |= p_cfg->reg.w; 551 writel(reg, addr); 552 553 /* polling PLL lock status */ 554 while(0 == (readl(addr_ext) & BIT(31))); 555 556 return 0; 557 } 558 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 559 { 560 struct ast2600_pll_desc mpll; 561 562 mpll.in = AST2600_CLK_IN; 563 mpll.out = rate; 564 if (false == ast2600_search_clock_config(&mpll)) { 565 printf("error!! unable to find valid DDR clock setting\n"); 566 return 0; 567 } 568 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 569 570 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 571 } 572 573 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 574 { 575 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 576 577 ulong new_rate; 578 switch (clk->id) { 579 case ASPEED_CLK_MPLL: 580 new_rate = ast2600_configure_ddr(priv->scu, rate); 581 break; 582 default: 583 return -ENOENT; 584 } 585 586 return new_rate; 587 } 588 589 #define SCU_CLKSTOP_MAC1 (20) 590 #define SCU_CLKSTOP_MAC2 (21) 591 #define SCU_CLKSTOP_MAC3 (20) 592 #define SCU_CLKSTOP_MAC4 (21) 593 594 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 595 { 596 /* scu340[25:0]: 1G default delay */ 597 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 598 MAC_DEF_DELAY_1G); 599 600 /* set 100M/10M default delay */ 601 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 602 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 603 604 /* MAC AHB = HPLL / 6 */ 605 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 606 607 return 0; 608 } 609 610 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 611 { 612 613 /* 614 * scu350[31] RGMII 125M source: 0 = from IO pin 615 * scu350[25:0] MAC 1G delay 616 */ 617 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 618 MAC34_DEF_DELAY_1G); 619 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 620 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 621 622 /* 623 * clock source seletion and divider 624 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 625 * scu310[18:16] : RMII 50M = HCLK_200M / 4 626 */ 627 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 628 ((0x0 << 24) | (0x3 << 16))); 629 630 /* 631 * set driving strength 632 * scu458[3:2] : MAC4 driving strength 633 * scu458[1:0] : MAC3 driving strength 634 */ 635 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 636 (0x3 << 2) | (0x3 << 0)); 637 638 return 0; 639 } 640 641 /** 642 * ast2600 RGMII clock source tree 643 * 644 * 125M from external PAD -------->|\ 645 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 646 * | |---->| divider |---->|/ + 647 * EPLL -->|/ | 648 * | 649 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 650 * | 651 * +--------------------------->|\ 652 * | |----> RGMII 125M for MAC#3 & MAC#4 653 * HCLK 200M ---->|divider|---->|/ 654 * 655 * To simplify the control flow: 656 * 1. RGMII 1/2 always use EPLL as the internal clock source 657 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 658 * 659 * 125M from external PAD -------->|\ 660 * | |---->RGMII 125M for MAC#1 & MAC#2 661 * EPLL---->| divider |--->|/ + 662 * | 663 * +<--------------------|RGMIICK PAD output enable|<-------------+ 664 * | 665 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 666 */ 667 #define RGMIICK_SRC_PAD 0 668 #define RGMIICK_SRC_EPLL 1 /* recommended */ 669 #define RGMIICK_SRC_HPLL 2 670 671 #define RGMIICK_DIV2 1 672 #define RGMIICK_DIV3 2 673 #define RGMIICK_DIV4 3 674 #define RGMIICK_DIV5 4 675 #define RGMIICK_DIV6 5 676 #define RGMIICK_DIV7 6 677 #define RGMIICK_DIV8 7 /* recommended */ 678 679 #define RMIICK_DIV4 0 680 #define RMIICK_DIV8 1 681 #define RMIICK_DIV12 2 682 #define RMIICK_DIV16 3 683 #define RMIICK_DIV20 4 /* recommended */ 684 #define RMIICK_DIV24 5 685 #define RMIICK_DIV28 6 686 #define RMIICK_DIV32 7 687 688 struct ast2600_mac_clk_div { 689 u32 src; /* 0=external PAD, 1=internal PLL */ 690 u32 fin; /* divider input speed */ 691 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 692 u32 fout; /* fout = fin / n */ 693 }; 694 695 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 696 .src = ASPEED_CLK_EPLL, 697 .fin = 1000000000, 698 .n = RGMIICK_DIV8, 699 .fout = 125000000, 700 }; 701 702 struct ast2600_mac_clk_div rmii_clk_defconfig = { 703 .src = ASPEED_CLK_EPLL, 704 .fin = 1000000000, 705 .n = RMIICK_DIV20, 706 .fout = 50000000, 707 }; 708 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 709 struct ast2600_mac_clk_div *p_cfg) 710 { 711 struct ast2600_pll_desc pll; 712 713 pll.in = AST2600_CLK_IN; 714 pll.out = p_cfg->fin; 715 if (false == ast2600_search_clock_config(&pll)) { 716 printf("error!! unable to find valid ETHNET MAC clock " 717 "setting\n"); 718 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 719 pll.cfg.ext_reg); 720 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 721 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 722 return; 723 } 724 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 725 } 726 727 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 728 struct ast2600_mac_clk_div *p_cfg) 729 { 730 u32 reg_304 = readl(&p_scu->clk_sel2); 731 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 732 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 733 734 reg_340 &= ~GENMASK(31, 29); 735 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 736 reg_340 |= BIT(28); 737 if ((p_cfg->src == ASPEED_CLK_EPLL) || 738 (p_cfg->src == ASPEED_CLK_HPLL)) { 739 /* 740 * re-init PLL if the current PLL output frequency doesn't match 741 * the divider setting 742 */ 743 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 744 ast2600_init_mac_pll(p_scu, p_cfg); 745 } 746 /* scu340[31]: select RGMII 125M from internal source */ 747 reg_340 |= BIT(31); 748 } 749 750 reg_304 &= ~GENMASK(23, 20); 751 752 /* set clock divider */ 753 reg_304 |= (p_cfg->n & 0x7) << 20; 754 755 /* select internal clock source */ 756 if (ASPEED_CLK_HPLL == p_cfg->src) { 757 reg_304 |= BIT(23); 758 } 759 760 /* RGMII 3/4 clock source select */ 761 reg_350 &= ~BIT(31); 762 #if 0 763 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 764 reg_350 |= BIT(31); 765 } 766 767 /* set clock divider */ 768 reg_310 &= ~GENMASK(22, 20); 769 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 770 #endif 771 772 writel(reg_304, &p_scu->clk_sel2); 773 writel(reg_340, &p_scu->mac12_clk_delay); 774 writel(reg_350, &p_scu->mac34_clk_delay); 775 } 776 777 /** 778 * ast2600 RMII/NCSI clock source tree 779 * 780 * HPLL -->|\ 781 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 782 * EPLL -->|/ 783 * 784 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 785 */ 786 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 787 struct ast2600_mac_clk_div *p_cfg) 788 { 789 u32 reg_304; 790 u32 reg_310; 791 792 if ((p_cfg->src == ASPEED_CLK_EPLL) || 793 (p_cfg->src == ASPEED_CLK_HPLL)) { 794 /* 795 * re-init PLL if the current PLL output frequency doesn't match 796 * the divider setting 797 */ 798 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 799 ast2600_init_mac_pll(p_scu, p_cfg); 800 } 801 } 802 803 reg_304 = readl(&p_scu->clk_sel2); 804 reg_310 = readl(&p_scu->clk_sel4); 805 806 reg_304 &= ~GENMASK(19, 16); 807 808 /* set RMII 1/2 clock divider */ 809 reg_304 |= (p_cfg->n & 0x7) << 16; 810 811 /* RMII clock source selection */ 812 if (ASPEED_CLK_HPLL == p_cfg->src) { 813 reg_304 |= BIT(19); 814 } 815 816 /* set RMII 3/4 clock divider */ 817 reg_310 &= ~GENMASK(18, 16); 818 reg_310 |= (0x3 << 16); 819 820 writel(reg_304, &p_scu->clk_sel2); 821 writel(reg_310, &p_scu->clk_sel4); 822 } 823 824 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 825 { 826 u32 reset_bit; 827 u32 clkstop_bit; 828 829 switch (index) { 830 case 1: 831 reset_bit = BIT(ASPEED_RESET_MAC1); 832 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 833 writel(reset_bit, &scu->sysreset_ctrl1); 834 udelay(100); 835 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 836 mdelay(10); 837 writel(reset_bit, &scu->sysreset_clr_ctrl1); 838 839 break; 840 case 2: 841 reset_bit = BIT(ASPEED_RESET_MAC2); 842 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 843 writel(reset_bit, &scu->sysreset_ctrl1); 844 udelay(100); 845 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 846 mdelay(10); 847 writel(reset_bit, &scu->sysreset_clr_ctrl1); 848 break; 849 case 3: 850 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 851 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 852 writel(reset_bit, &scu->sysreset_ctrl2); 853 udelay(100); 854 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 855 mdelay(10); 856 writel(reset_bit, &scu->sysreset_clr_ctrl2); 857 break; 858 case 4: 859 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 860 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 861 writel(reset_bit, &scu->sysreset_ctrl2); 862 udelay(100); 863 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 864 mdelay(10); 865 writel(reset_bit, &scu->sysreset_clr_ctrl2); 866 break; 867 default: 868 return -EINVAL; 869 } 870 871 return 0; 872 } 873 874 #define SCU_CLKSTOP_SDIO 4 875 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 876 { 877 u32 reset_bit; 878 u32 clkstop_bit; 879 880 reset_bit = BIT(ASPEED_RESET_SD - 32); 881 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 882 883 writel(reset_bit, &scu->sysreset_ctrl2); 884 885 udelay(100); 886 //enable clk 887 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 888 mdelay(10); 889 writel(reset_bit, &scu->sysreset_clr_ctrl2); 890 891 return 0; 892 } 893 894 #define SCU_CLKSTOP_EXTSD 31 895 #define SCU_CLK_SD_MASK (0x7 << 28) 896 #define SCU_CLK_SD_DIV(x) (x << 28) 897 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 898 899 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 900 { 901 u32 clk_sel = readl(&scu->clk_sel4); 902 u32 enableclk_bit; 903 u32 rate = 0; 904 u32 div = 0; 905 int i = 0; 906 907 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 908 909 //ast2600 sd controller max clk is 200Mhz : use apll for clock source 800/4 = 200 : controller max is 200mhz 910 rate = ast2600_get_apll_rate(scu); 911 for(i = 0; i < 8; i++) { 912 div = (i + 1) * 2; 913 if ((rate / div) <= 200000000) 914 break; 915 } 916 clk_sel &= ~SCU_CLK_SD_MASK; 917 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 918 writel(clk_sel, &scu->clk_sel4); 919 920 //enable clk 921 setbits_le32(&scu->clk_sel4, enableclk_bit); 922 923 return 0; 924 } 925 926 #define SCU_CLKSTOP_EMMC 27 927 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 928 { 929 u32 reset_bit; 930 u32 clkstop_bit; 931 932 reset_bit = BIT(ASPEED_RESET_EMMC); 933 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 934 935 writel(reset_bit, &scu->sysreset_ctrl1); 936 udelay(100); 937 //enable clk 938 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 939 mdelay(10); 940 writel(reset_bit, &scu->sysreset_clr_ctrl1); 941 942 return 0; 943 } 944 945 #define SCU_CLKSTOP_EXTEMMC 15 946 #define SCU_CLK_EMMC_MASK (0x7 << 12) 947 #define SCU_CLK_EMMC_DIV(x) (x << 12) 948 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) //AST2600A1 949 950 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 951 { 952 u32 revision_id = readl(&scu->chip_id0); 953 u32 clk_sel = readl(&scu->clk_sel1); 954 u32 enableclk_bit; 955 u32 rate = 0; 956 u32 div = 0; 957 int i = 0; 958 959 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 960 961 //ast2600 eMMC controller max clk is 200Mhz 962 /********************************************************************************************* 963 HPll -> 1/2 -- 964 \ 965 --> SCU300[11] -> SCU300[14:12] [1/N] -> EMMC12C[15:8] [1/N] --> eMMC clk 966 / 967 MPLL - ----- -> 968 *********************************************************************************************/ 969 if(((revision_id & GENMASK(23, 16)) >> 16)) { 970 //AST2600A1 : use mpll to be clk source 971 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 972 for(i = 0; i < 8; i++) { 973 div = (i + 1) * 2; 974 if ((rate / div) <= 200000000) 975 break; 976 } 977 978 clk_sel &= ~SCU_CLK_EMMC_MASK; 979 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 980 writel(clk_sel, &scu->clk_sel1); 981 982 } else { 983 //AST2600A0 : use hpll to be clk source 984 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 985 986 for(i = 0; i < 8; i++) { 987 div = (i + 1) * 4; 988 if ((rate / div) <= 200000000) 989 break; 990 } 991 992 clk_sel &= ~SCU_CLK_EMMC_MASK; 993 clk_sel |= SCU_CLK_EMMC_DIV(i); 994 writel(clk_sel, &scu->clk_sel1); 995 } 996 997 //enable clk 998 setbits_le32(&scu->clk_sel1, enableclk_bit); 999 1000 return 0; 1001 } 1002 1003 #define SCU_CLKSTOP_FSICLK 30 1004 1005 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1006 { 1007 u32 reset_bit; 1008 u32 clkstop_bit; 1009 1010 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1011 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1012 1013 /* The FSI clock is shared between masters. If it's already on 1014 * don't touch it, as that will reset the existing master. */ 1015 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1016 debug("%s: already running, not touching it\n", __func__); 1017 return 0; 1018 } 1019 1020 writel(reset_bit, &scu->sysreset_ctrl2); 1021 udelay(100); 1022 //enable clk 1023 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1024 mdelay(10); 1025 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1026 1027 return 0; 1028 } 1029 1030 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1031 { 1032 u32 reset_bit; 1033 u32 clkstop_bit; 1034 1035 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1036 clkstop_bit = BIT(14); 1037 1038 writel(reset_bit, &scu->sysreset_ctrl1); 1039 udelay(100); 1040 //enable phy clk 1041 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1042 mdelay(20); 1043 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1044 1045 return 0; 1046 } 1047 1048 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1049 { 1050 u32 reset_bit; 1051 u32 clkstop_bit; 1052 1053 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1054 clkstop_bit = BIT(7); 1055 1056 writel(reset_bit, &scu->sysreset_ctrl1); 1057 udelay(100); 1058 //enable phy clk 1059 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1060 mdelay(20); 1061 1062 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1063 1064 return 0; 1065 } 1066 1067 static int ast2600_clk_enable(struct clk *clk) 1068 { 1069 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1070 1071 switch (clk->id) { 1072 case ASPEED_CLK_GATE_MAC1CLK: 1073 ast2600_configure_mac(priv->scu, 1); 1074 break; 1075 case ASPEED_CLK_GATE_MAC2CLK: 1076 ast2600_configure_mac(priv->scu, 2); 1077 break; 1078 case ASPEED_CLK_GATE_MAC3CLK: 1079 ast2600_configure_mac(priv->scu, 3); 1080 break; 1081 case ASPEED_CLK_GATE_MAC4CLK: 1082 ast2600_configure_mac(priv->scu, 4); 1083 break; 1084 case ASPEED_CLK_GATE_SDCLK: 1085 ast2600_enable_sdclk(priv->scu); 1086 break; 1087 case ASPEED_CLK_GATE_SDEXTCLK: 1088 ast2600_enable_extsdclk(priv->scu); 1089 break; 1090 case ASPEED_CLK_GATE_EMMCCLK: 1091 ast2600_enable_emmcclk(priv->scu); 1092 break; 1093 case ASPEED_CLK_GATE_EMMCEXTCLK: 1094 ast2600_enable_extemmcclk(priv->scu); 1095 break; 1096 case ASPEED_CLK_GATE_FSICLK: 1097 ast2600_enable_fsiclk(priv->scu); 1098 break; 1099 case ASPEED_CLK_GATE_USBPORT1CLK: 1100 ast2600_enable_usbahclk(priv->scu); 1101 break; 1102 case ASPEED_CLK_GATE_USBPORT2CLK: 1103 ast2600_enable_usbbhclk(priv->scu); 1104 break; 1105 default: 1106 pr_debug("can't enable clk \n"); 1107 return -ENOENT; 1108 break; 1109 } 1110 1111 return 0; 1112 } 1113 1114 struct clk_ops ast2600_clk_ops = { 1115 .get_rate = ast2600_clk_get_rate, 1116 .set_rate = ast2600_clk_set_rate, 1117 .enable = ast2600_clk_enable, 1118 }; 1119 1120 static int ast2600_clk_probe(struct udevice *dev) 1121 { 1122 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1123 u32 uart_clk_source; 1124 1125 priv->scu = devfdt_get_addr_ptr(dev); 1126 if (IS_ERR(priv->scu)) 1127 return PTR_ERR(priv->scu); 1128 1129 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 1130 0x0); 1131 1132 if(uart_clk_source) { 1133 if(uart_clk_source & GENMASK(5, 0)) 1134 setbits_le32(&priv->scu->clk_sel4, uart_clk_source & GENMASK(5, 0)); 1135 if(uart_clk_source & GENMASK(12, 6)) 1136 setbits_le32(&priv->scu->clk_sel5, uart_clk_source & GENMASK(12, 6)); 1137 } 1138 1139 1140 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1141 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1142 ast2600_configure_mac12_clk(priv->scu); 1143 ast2600_configure_mac34_clk(priv->scu); 1144 1145 /* RSA clock = HPLL/3 */ 1146 setbits_le32(&priv->scu->clk_sel1, BIT(19)); 1147 setbits_le32(&priv->scu->clk_sel1, BIT(27)); 1148 1149 return 0; 1150 } 1151 1152 static int ast2600_clk_bind(struct udevice *dev) 1153 { 1154 int ret; 1155 1156 /* The reset driver does not have a device node, so bind it here */ 1157 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1158 if (ret) 1159 debug("Warning: No reset driver: ret=%d\n", ret); 1160 1161 return 0; 1162 } 1163 1164 #if CONFIG_IS_ENABLED(CMD_CLK) 1165 struct aspeed_clks { 1166 ulong id; 1167 const char *name; 1168 }; 1169 1170 static struct aspeed_clks aspeed_clk_names[] = { 1171 { ASPEED_CLK_HPLL, "hpll" }, 1172 { ASPEED_CLK_MPLL, "mpll" }, 1173 { ASPEED_CLK_APLL, "apll" }, 1174 { ASPEED_CLK_EPLL, "epll" }, 1175 { ASPEED_CLK_DPLL, "dpll" }, 1176 { ASPEED_CLK_AHB, "hclk" }, 1177 { ASPEED_CLK_APB1, "pclk1" }, 1178 { ASPEED_CLK_APB2, "pclk2" }, 1179 { ASPEED_CLK_BCLK, "bclk" }, 1180 { ASPEED_CLK_UARTX, "uxclk" }, 1181 { ASPEED_CLK_HUARTX, "huxclk" }, 1182 }; 1183 1184 int soc_clk_dump(void) 1185 { 1186 struct udevice *dev; 1187 struct clk clk; 1188 unsigned long rate; 1189 int i, ret; 1190 1191 ret = uclass_get_device_by_driver(UCLASS_CLK, 1192 DM_GET_DRIVER(aspeed_scu), &dev); 1193 if (ret) 1194 return ret; 1195 1196 printf("Clk\t\tHz\n"); 1197 1198 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1199 clk.id = aspeed_clk_names[i].id; 1200 ret = clk_request(dev, &clk); 1201 if (ret < 0) { 1202 debug("%s clk_request() failed: %d\n", __func__, ret); 1203 continue; 1204 } 1205 1206 ret = clk_get_rate(&clk); 1207 rate = ret; 1208 1209 clk_free(&clk); 1210 1211 if (ret == -ENOTSUPP) { 1212 printf("clk ID %lu not supported yet\n", 1213 aspeed_clk_names[i].id); 1214 continue; 1215 } 1216 if (ret < 0) { 1217 printf("%s %lu: get_rate err: %d\n", 1218 __func__, aspeed_clk_names[i].id, ret); 1219 continue; 1220 } 1221 1222 printf("%s(%3lu):\t%lu\n", 1223 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1224 } 1225 1226 return 0; 1227 } 1228 #endif 1229 1230 static const struct udevice_id ast2600_clk_ids[] = { 1231 { .compatible = "aspeed,ast2600-scu", }, 1232 { } 1233 }; 1234 1235 U_BOOT_DRIVER(aspeed_scu) = { 1236 .name = "aspeed_scu", 1237 .id = UCLASS_CLK, 1238 .of_match = ast2600_clk_ids, 1239 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1240 .ops = &ast2600_clk_ops, 1241 .bind = ast2600_clk_bind, 1242 .probe = ast2600_clk_probe, 1243 }; 1244