1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 u32 w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 u32 ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, { 84 .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f, 90 }, { 91 .in = AST2600_CLK_IN, 92 .out = 334000000, 93 .cfg.reg.b.m = 667, 94 .cfg.reg.b.n = 4, 95 .cfg.reg.b.p = 9, 96 .cfg.ext_reg = 0x14d, 97 }, { 98 .in = AST2600_CLK_IN, 99 .out = 1000000000, 100 .cfg.reg.b.m = 119, 101 .cfg.reg.b.n = 2, 102 .cfg.reg.b.p = 0, 103 .cfg.ext_reg = 0x3d, 104 }, { 105 .in = AST2600_CLK_IN, 106 .out = 50000000, 107 .cfg.reg.b.m = 95, 108 .cfg.reg.b.n = 2, 109 .cfg.reg.b.p = 15, 110 .cfg.ext_reg = 0x31, 111 }, 112 }; 113 114 union mac_delay_1g { 115 u32 w; 116 struct { 117 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 118 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 119 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 120 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 121 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 122 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 123 unsigned int rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 124 unsigned int rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 125 unsigned int rgmiick_pad_dir : 1; /* bit[28] */ 126 unsigned int rmii_50m_oe_1 : 1; /* bit[29] */ 127 unsigned int rmii_50m_oe_2 : 1; /* bit[30] */ 128 unsigned int rgmii_125m_o_sel : 1; /* bit[31] */ 129 } b; 130 }; 131 132 union mac_delay_100_10 { 133 u32 w; 134 struct { 135 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 136 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 137 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 138 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 139 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 140 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 141 unsigned int reserved_0 : 6; /* bit[31:26] */ 142 } b; 143 }; 144 145 struct mac_delay_config { 146 u32 tx_delay_1000; 147 u32 rx_delay_1000; 148 u32 tx_delay_100; 149 u32 rx_delay_100; 150 u32 tx_delay_10; 151 u32 rx_delay_10; 152 }; 153 154 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 155 { 156 u32 clkin = AST2600_CLK_IN; 157 u32 pll_reg = 0; 158 unsigned int mult, div = 1; 159 160 switch (pll_idx) { 161 case ASPEED_CLK_HPLL: 162 pll_reg = readl(&scu->h_pll_param); 163 break; 164 case ASPEED_CLK_MPLL: 165 pll_reg = readl(&scu->m_pll_param); 166 break; 167 case ASPEED_CLK_DPLL: 168 pll_reg = readl(&scu->d_pll_param); 169 break; 170 case ASPEED_CLK_EPLL: 171 pll_reg = readl(&scu->e_pll_param); 172 break; 173 } 174 if (pll_reg & BIT(24)) { 175 /* Pass through mode */ 176 mult = 1; 177 div = 1; 178 } else { 179 union ast2600_pll_reg reg; 180 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 181 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 182 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 183 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 184 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 185 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 186 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 187 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 188 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 189 */ 190 reg.w = pll_reg; 191 if (pll_idx == ASPEED_CLK_HPLL) { 192 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 193 194 if (hwstrap1 & BIT(10)) { 195 reg.b.m = 0x5F; 196 } else { 197 if (hwstrap1 & BIT(8)) 198 reg.b.m = 0xBF; 199 /* Otherwise keep default 0x8F */ 200 } 201 } 202 mult = (reg.b.m + 1) / (reg.b.n + 1); 203 div = (reg.b.p + 1); 204 } 205 206 return ((clkin * mult) / div); 207 } 208 209 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 210 { 211 u32 hw_rev = readl(&scu->chip_id1); 212 u32 clkin = AST2600_CLK_IN; 213 u32 apll_reg = readl(&scu->a_pll_param); 214 unsigned int mult, div = 1; 215 216 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 2) { 217 //after A2 version 218 if (apll_reg & BIT(24)) { 219 /* Pass through mode */ 220 mult = 1; 221 div = 1; 222 } else { 223 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 224 u32 m = apll_reg & 0x1fff; 225 u32 n = (apll_reg >> 13) & 0x3f; 226 u32 p = (apll_reg >> 19) & 0xf; 227 228 mult = (m + 1); 229 div = (n + 1) * (p + 1); 230 } 231 } else { 232 if (apll_reg & BIT(20)) { 233 /* Pass through mode */ 234 mult = 1; 235 div = 1; 236 } else { 237 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 238 u32 m = (apll_reg >> 5) & 0x3f; 239 u32 od = (apll_reg >> 4) & 0x1; 240 u32 n = apll_reg & 0xf; 241 242 mult = (2 - od) * (m + 2); 243 div = n + 1; 244 } 245 } 246 247 return ((clkin * mult) / div); 248 } 249 250 static u32 ast2600_a0_axi_ahb_div_table[] = { 251 2, 252 2, 253 3, 254 4, 255 }; 256 257 static u32 ast2600_a1_axi_ahb_div0_table[] = { 258 3, 259 2, 260 3, 261 4, 262 }; 263 264 static u32 ast2600_a1_axi_ahb_div1_table[] = { 265 3, 266 4, 267 6, 268 8, 269 }; 270 271 static u32 ast2600_a1_axi_ahb_default_table[] = { 272 3, 4, 3, 4, 2, 2, 2, 2, 273 }; 274 275 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 276 { 277 u32 hw_rev = readl(&scu->chip_id1); 278 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 279 u32 axi_div = 1; 280 u32 ahb_div = 0; 281 u32 rate = 0; 282 283 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 284 //After A0 285 if (hwstrap1 & BIT(16)) { 286 ast2600_a1_axi_ahb_div1_table[0] = 287 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 288 0x7] * 2; 289 axi_div = 1; 290 ahb_div = 291 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 292 0x3]; 293 } else { 294 ast2600_a1_axi_ahb_div0_table[0] = 295 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 296 0x7]; 297 axi_div = 2; 298 ahb_div = 299 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 300 0x3]; 301 } 302 } else { 303 //A0 : fix axi = hpll / 2 304 axi_div = 2; 305 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 306 } 307 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 308 309 return (rate / axi_div / ahb_div); 310 } 311 312 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 313 { 314 u32 rate; 315 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 316 317 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 318 319 return (rate / ((bclk_sel + 1) * 4)); 320 } 321 322 static u32 ast2600_hpll_pclk1_div_table[] = { 323 4, 8, 12, 16, 20, 24, 28, 32, 324 }; 325 326 static u32 ast2600_hpll_pclk2_div_table[] = { 327 2, 4, 6, 8, 10, 12, 14, 16, 328 }; 329 330 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 331 { 332 u32 clk_sel1 = readl(&scu->clk_sel1); 333 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 334 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 335 336 return (rate / apb_div); 337 } 338 339 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 340 { 341 u32 clk_sel4 = readl(&scu->clk_sel4); 342 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 343 u32 rate = ast2600_get_hclk(scu); 344 345 return (rate / apb_div); 346 } 347 348 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 349 { 350 u32 clk_in = 0; 351 u32 uxclk_sel = readl(&scu->clk_sel5); 352 353 uxclk_sel &= 0x3; 354 switch (uxclk_sel) { 355 case 0: 356 clk_in = ast2600_get_apll_rate(scu) / 4; 357 break; 358 case 1: 359 clk_in = ast2600_get_apll_rate(scu) / 2; 360 break; 361 case 2: 362 clk_in = ast2600_get_apll_rate(scu); 363 break; 364 case 3: 365 clk_in = ast2600_get_hclk(scu); 366 break; 367 } 368 369 return clk_in; 370 } 371 372 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 373 { 374 u32 clk_in = 0; 375 u32 huclk_sel = readl(&scu->clk_sel5); 376 377 huclk_sel = ((huclk_sel >> 3) & 0x3); 378 switch (huclk_sel) { 379 case 0: 380 clk_in = ast2600_get_apll_rate(scu) / 4; 381 break; 382 case 1: 383 clk_in = ast2600_get_apll_rate(scu) / 2; 384 break; 385 case 2: 386 clk_in = ast2600_get_apll_rate(scu); 387 break; 388 case 3: 389 clk_in = ast2600_get_hclk(scu); 390 break; 391 } 392 393 return clk_in; 394 } 395 396 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 397 { 398 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 399 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 400 unsigned int mult, div; 401 402 u32 n = (div_reg >> 8) & 0x3ff; 403 u32 r = div_reg & 0xff; 404 405 mult = r; 406 div = (n * 2); 407 return (clk_in * mult) / div; 408 } 409 410 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 411 { 412 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 413 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 414 415 unsigned int mult, div; 416 417 u32 n = (div_reg >> 8) & 0x3ff; 418 u32 r = div_reg & 0xff; 419 420 mult = r; 421 div = (n * 2); 422 return (clk_in * mult) / div; 423 } 424 425 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 426 { 427 u32 clkin = 0; 428 u32 clk_sel = readl(&scu->clk_sel4); 429 u32 div = (clk_sel >> 28) & 0x7; 430 u32 hw_rev = readl(&scu->chip_id1); 431 432 if (clk_sel & BIT(8)) 433 clkin = ast2600_get_apll_rate(scu); 434 else 435 clkin = ast2600_get_hclk(scu); 436 437 div = (1 + div) * 2; 438 if (((hw_rev & GENMASK(23, 16)) >> 16) >= 2) 439 div = (div & 0xf) ? div : 1; 440 441 return (clkin / div); 442 } 443 444 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 445 { 446 u32 mmc_clk_src = readl(&scu->clk_sel1); 447 u32 clkin; 448 u32 clk_sel = readl(&scu->clk_sel1); 449 u32 div = (clk_sel >> 12) & 0x7; 450 451 if (mmc_clk_src & BIT(11)) { 452 /* emmc clock comes from MPLL */ 453 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 454 div = (div + 1) * 2; 455 } else { 456 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 457 div = (div + 1) << 2; 458 } 459 460 return (clkin / div); 461 } 462 463 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 464 { 465 u32 uart_sel = readl(&scu->clk_sel4); 466 u32 uart_sel5 = readl(&scu->clk_sel5); 467 ulong uart_clk = 0; 468 469 switch (uart_idx) { 470 case 1: 471 case 2: 472 case 3: 473 case 4: 474 case 6: 475 if (uart_sel & BIT(uart_idx - 1)) 476 uart_clk = ast2600_get_uart_huxclk_rate(scu); 477 else 478 uart_clk = ast2600_get_uart_uxclk_rate(scu); 479 break; 480 case 5: //24mhz is come form usb phy 48Mhz 481 { 482 u8 uart5_clk_sel = 0; 483 //high bit 484 if (readl(&scu->misc_ctrl1) & BIT(12)) 485 uart5_clk_sel = 0x2; 486 else 487 uart5_clk_sel = 0x0; 488 489 if (readl(&scu->clk_sel2) & BIT(14)) 490 uart5_clk_sel |= 0x1; 491 492 switch (uart5_clk_sel) { 493 case 0: 494 uart_clk = 24000000; 495 break; 496 case 1: 497 uart_clk = 192000000; 498 break; 499 case 2: 500 uart_clk = 24000000 / 13; 501 break; 502 case 3: 503 uart_clk = 192000000 / 13; 504 break; 505 } 506 } break; 507 case 7: 508 case 8: 509 case 9: 510 case 10: 511 case 11: 512 case 12: 513 case 13: 514 if (uart_sel5 & BIT(uart_idx - 1)) 515 uart_clk = ast2600_get_uart_huxclk_rate(scu); 516 else 517 uart_clk = ast2600_get_uart_uxclk_rate(scu); 518 break; 519 } 520 521 return uart_clk; 522 } 523 524 static ulong ast2600_clk_get_rate(struct clk *clk) 525 { 526 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 527 ulong rate = 0; 528 529 switch (clk->id) { 530 case ASPEED_CLK_HPLL: 531 case ASPEED_CLK_EPLL: 532 case ASPEED_CLK_DPLL: 533 case ASPEED_CLK_MPLL: 534 rate = ast2600_get_pll_rate(priv->scu, clk->id); 535 break; 536 case ASPEED_CLK_AHB: 537 rate = ast2600_get_hclk(priv->scu); 538 break; 539 case ASPEED_CLK_APB1: 540 rate = ast2600_get_pclk1(priv->scu); 541 break; 542 case ASPEED_CLK_APB2: 543 rate = ast2600_get_pclk2(priv->scu); 544 break; 545 case ASPEED_CLK_APLL: 546 rate = ast2600_get_apll_rate(priv->scu); 547 break; 548 case ASPEED_CLK_GATE_UART1CLK: 549 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 550 break; 551 case ASPEED_CLK_GATE_UART2CLK: 552 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 553 break; 554 case ASPEED_CLK_GATE_UART3CLK: 555 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 556 break; 557 case ASPEED_CLK_GATE_UART4CLK: 558 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 559 break; 560 case ASPEED_CLK_GATE_UART5CLK: 561 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 562 break; 563 case ASPEED_CLK_BCLK: 564 rate = ast2600_get_bclk_rate(priv->scu); 565 break; 566 case ASPEED_CLK_SDIO: 567 rate = ast2600_get_sdio_clk_rate(priv->scu); 568 break; 569 case ASPEED_CLK_EMMC: 570 rate = ast2600_get_emmc_clk_rate(priv->scu); 571 break; 572 case ASPEED_CLK_UARTX: 573 rate = ast2600_get_uart_uxclk_rate(priv->scu); 574 break; 575 case ASPEED_CLK_HUARTX: 576 rate = ast2600_get_uart_huxclk_rate(priv->scu); 577 break; 578 default: 579 pr_debug("can't get clk rate\n"); 580 return -ENOENT; 581 } 582 583 return rate; 584 } 585 586 /** 587 * @brief lookup PLL divider config by input/output rate 588 * @param[in] *pll - PLL descriptor 589 * @return true - if PLL divider config is found, false - else 590 * The function caller shall fill "pll->in" and "pll->out", 591 * then this function will search the lookup table 592 * to find a valid PLL divider configuration. 593 */ 594 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 595 { 596 u32 i; 597 bool is_found = false; 598 599 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 600 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 601 602 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 603 is_found = true; 604 pll->cfg.reg.w = def_cfg->cfg.reg.w; 605 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 606 break; 607 } 608 } 609 return is_found; 610 } 611 612 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 613 struct ast2600_pll_cfg *p_cfg, int pll_idx) 614 { 615 u32 addr, addr_ext; 616 u32 reg; 617 618 switch (pll_idx) { 619 case ASPEED_CLK_HPLL: 620 addr = (u32)(&scu->h_pll_param); 621 addr_ext = (u32)(&scu->h_pll_ext_param); 622 break; 623 case ASPEED_CLK_MPLL: 624 addr = (u32)(&scu->m_pll_param); 625 addr_ext = (u32)(&scu->m_pll_ext_param); 626 break; 627 case ASPEED_CLK_DPLL: 628 addr = (u32)(&scu->d_pll_param); 629 addr_ext = (u32)(&scu->d_pll_ext_param); 630 break; 631 case ASPEED_CLK_EPLL: 632 addr = (u32)(&scu->e_pll_param); 633 addr_ext = (u32)(&scu->e_pll_ext_param); 634 break; 635 default: 636 debug("unknown PLL index\n"); 637 return 1; 638 } 639 640 p_cfg->reg.b.bypass = 0; 641 p_cfg->reg.b.off = 1; 642 p_cfg->reg.b.reset = 1; 643 644 reg = readl(addr); 645 reg &= ~GENMASK(25, 0); 646 reg |= p_cfg->reg.w; 647 writel(reg, addr); 648 649 /* write extend parameter */ 650 writel(p_cfg->ext_reg, addr_ext); 651 udelay(100); 652 p_cfg->reg.b.off = 0; 653 p_cfg->reg.b.reset = 0; 654 reg &= ~GENMASK(25, 0); 655 reg |= p_cfg->reg.w; 656 writel(reg, addr); 657 while (!(readl(addr_ext) & BIT(31))) 658 ; 659 660 return 0; 661 } 662 663 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 664 { 665 struct ast2600_pll_desc mpll; 666 667 mpll.in = AST2600_CLK_IN; 668 mpll.out = rate; 669 if (ast2600_search_clock_config(&mpll) == false) { 670 printf("error!! unable to find valid DDR clock setting\n"); 671 return 0; 672 } 673 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 674 675 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 676 } 677 678 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 679 { 680 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 681 ulong new_rate; 682 683 switch (clk->id) { 684 case ASPEED_CLK_MPLL: 685 new_rate = ast2600_configure_ddr(priv->scu, rate); 686 break; 687 default: 688 return -ENOENT; 689 } 690 691 return new_rate; 692 } 693 694 #define SCU_CLKSTOP_MAC1 (20) 695 #define SCU_CLKSTOP_MAC2 (21) 696 #define SCU_CLKSTOP_MAC3 (20) 697 #define SCU_CLKSTOP_MAC4 (21) 698 699 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu, struct udevice *dev) 700 { 701 union mac_delay_1g reg_1g; 702 union mac_delay_100_10 reg_100, reg_10; 703 struct mac_delay_config mac1_cfg, mac2_cfg; 704 int ret; 705 706 reg_1g.w = (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0)) | 707 MAC_DEF_DELAY_1G; 708 reg_100.w = MAC_DEF_DELAY_100M; 709 reg_10.w = MAC_DEF_DELAY_10M; 710 711 ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg, sizeof(mac1_cfg) / sizeof(u32)); 712 if (!ret) { 713 reg_1g.b.tx_delay_1 = mac1_cfg.tx_delay_1000; 714 reg_1g.b.rx_delay_1 = mac1_cfg.rx_delay_1000; 715 reg_100.b.tx_delay_1 = mac1_cfg.tx_delay_100; 716 reg_100.b.rx_delay_1 = mac1_cfg.rx_delay_100; 717 reg_10.b.tx_delay_1 = mac1_cfg.tx_delay_10; 718 reg_10.b.rx_delay_1 = mac1_cfg.rx_delay_10; 719 } 720 721 ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg, sizeof(mac2_cfg) / sizeof(u32)); 722 if (!ret) { 723 reg_1g.b.tx_delay_2 = mac2_cfg.tx_delay_1000; 724 reg_1g.b.rx_delay_2 = mac2_cfg.rx_delay_1000; 725 reg_100.b.tx_delay_2 = mac2_cfg.tx_delay_100; 726 reg_100.b.rx_delay_2 = mac2_cfg.rx_delay_100; 727 reg_10.b.tx_delay_2 = mac2_cfg.tx_delay_10; 728 reg_10.b.rx_delay_2 = mac2_cfg.rx_delay_10; 729 } 730 731 writel(reg_1g.w, &scu->mac12_clk_delay); 732 writel(reg_100.w, &scu->mac12_clk_delay_100M); 733 writel(reg_10.w, &scu->mac12_clk_delay_10M); 734 735 /* MAC AHB = HPLL / 6 */ 736 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 737 738 return 0; 739 } 740 741 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu, struct udevice *dev) 742 { 743 union mac_delay_1g reg_1g; 744 union mac_delay_100_10 reg_100, reg_10; 745 struct mac_delay_config mac3_cfg, mac4_cfg; 746 int ret; 747 748 /* 749 * scu350[31] RGMII 125M source: 0 = from IO pin 750 * scu350[25:0] MAC 1G delay 751 */ 752 reg_1g.w = (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0)) | 753 MAC34_DEF_DELAY_1G; 754 reg_1g.b.rgmii_125m_o_sel = 0; 755 reg_100.w = MAC34_DEF_DELAY_100M; 756 reg_10.w = MAC34_DEF_DELAY_10M; 757 758 ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32)); 759 if (!ret) { 760 reg_1g.b.tx_delay_1 = mac3_cfg.tx_delay_1000; 761 reg_1g.b.rx_delay_1 = mac3_cfg.rx_delay_1000; 762 reg_100.b.tx_delay_1 = mac3_cfg.tx_delay_100; 763 reg_100.b.rx_delay_1 = mac3_cfg.rx_delay_100; 764 reg_10.b.tx_delay_1 = mac3_cfg.tx_delay_10; 765 reg_10.b.rx_delay_1 = mac3_cfg.rx_delay_10; 766 } 767 768 ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32)); 769 if (!ret) { 770 reg_1g.b.tx_delay_2 = mac4_cfg.tx_delay_1000; 771 reg_1g.b.rx_delay_2 = mac4_cfg.rx_delay_1000; 772 reg_100.b.tx_delay_2 = mac4_cfg.tx_delay_100; 773 reg_100.b.rx_delay_2 = mac4_cfg.rx_delay_100; 774 reg_10.b.tx_delay_2 = mac4_cfg.tx_delay_10; 775 reg_10.b.rx_delay_2 = mac4_cfg.rx_delay_10; 776 } 777 778 writel(reg_1g.w, &scu->mac34_clk_delay); 779 writel(reg_100.w, &scu->mac34_clk_delay_100M); 780 writel(reg_10.w, &scu->mac34_clk_delay_10M); 781 782 /* 783 * clock source seletion and divider 784 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 785 * scu310[18:16] : RMII 50M = HCLK_200M / 4 786 */ 787 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 788 ((0x0 << 24) | (0x3 << 16))); 789 790 /* 791 * set driving strength 792 * scu458[3:2] : MAC4 driving strength 793 * scu458[1:0] : MAC3 driving strength 794 */ 795 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 796 (0x3 << 2) | (0x3 << 0)); 797 798 return 0; 799 } 800 801 /** 802 * ast2600 RGMII clock source tree 803 * 125M from external PAD -------->|\ 804 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 805 * | |---->| divider |---->|/ + 806 * EPLL -->|/ | 807 * | 808 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 809 * | 810 * +--------------------------->|\ 811 * | |----> RGMII 125M for MAC#3 & MAC#4 812 * HCLK 200M ---->|divider|---->|/ 813 * To simplify the control flow: 814 * 1. RGMII 1/2 always use EPLL as the internal clock source 815 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 816 * 125M from external PAD -------->|\ 817 * | |---->RGMII 125M for MAC#1 & MAC#2 818 * EPLL---->| divider |--->|/ + 819 * | 820 * +<--------------------|RGMIICK PAD output enable|<-------------+ 821 * | 822 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 823 */ 824 #define RGMIICK_SRC_PAD 0 825 #define RGMIICK_SRC_EPLL 1 /* recommended */ 826 #define RGMIICK_SRC_HPLL 2 827 828 #define RGMIICK_DIV2 1 829 #define RGMIICK_DIV3 2 830 #define RGMIICK_DIV4 3 831 #define RGMIICK_DIV5 4 832 #define RGMIICK_DIV6 5 833 #define RGMIICK_DIV7 6 834 #define RGMIICK_DIV8 7 /* recommended */ 835 836 #define RMIICK_DIV4 0 837 #define RMIICK_DIV8 1 838 #define RMIICK_DIV12 2 839 #define RMIICK_DIV16 3 840 #define RMIICK_DIV20 4 /* recommended */ 841 #define RMIICK_DIV24 5 842 #define RMIICK_DIV28 6 843 #define RMIICK_DIV32 7 844 845 struct ast2600_mac_clk_div { 846 u32 src; /* 0=external PAD, 1=internal PLL */ 847 u32 fin; /* divider input speed */ 848 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 849 u32 fout; /* fout = fin / n */ 850 }; 851 852 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 853 .src = ASPEED_CLK_EPLL, 854 .fin = 1000000000, 855 .n = RGMIICK_DIV8, 856 .fout = 125000000, 857 }; 858 859 struct ast2600_mac_clk_div rmii_clk_defconfig = { 860 .src = ASPEED_CLK_EPLL, 861 .fin = 1000000000, 862 .n = RMIICK_DIV20, 863 .fout = 50000000, 864 }; 865 866 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 867 struct ast2600_mac_clk_div *p_cfg) 868 { 869 struct ast2600_pll_desc pll; 870 871 pll.in = AST2600_CLK_IN; 872 pll.out = p_cfg->fin; 873 if (ast2600_search_clock_config(&pll) == false) { 874 pr_err("unable to find valid ETHNET MAC clock setting\n"); 875 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 876 pll.cfg.ext_reg); 877 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 878 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 879 return; 880 } 881 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 882 } 883 884 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 885 struct ast2600_mac_clk_div *p_cfg) 886 { 887 u32 reg_304 = readl(&p_scu->clk_sel2); 888 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 889 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 890 891 reg_340 &= ~GENMASK(31, 29); 892 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 893 reg_340 |= BIT(28); 894 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 895 /* 896 * re-init PLL if the current PLL output frequency doesn't match 897 * the divider setting 898 */ 899 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 900 ast2600_init_mac_pll(p_scu, p_cfg); 901 /* scu340[31]: select RGMII 125M from internal source */ 902 reg_340 |= BIT(31); 903 } 904 905 reg_304 &= ~GENMASK(23, 20); 906 907 /* set clock divider */ 908 reg_304 |= (p_cfg->n & 0x7) << 20; 909 910 /* select internal clock source */ 911 if (p_cfg->src == ASPEED_CLK_HPLL) 912 reg_304 |= BIT(23); 913 914 /* RGMII 3/4 clock source select */ 915 reg_350 &= ~BIT(31); 916 917 writel(reg_304, &p_scu->clk_sel2); 918 writel(reg_340, &p_scu->mac12_clk_delay); 919 writel(reg_350, &p_scu->mac34_clk_delay); 920 } 921 922 /** 923 * ast2600 RMII/NCSI clock source tree 924 * HPLL -->|\ 925 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 926 * EPLL -->|/ 927 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 928 */ 929 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 930 struct ast2600_mac_clk_div *p_cfg) 931 { 932 u32 reg_304; 933 u32 reg_310; 934 935 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 936 /* 937 * re-init PLL if the current PLL output frequency doesn't match 938 * the divider setting 939 */ 940 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 941 ast2600_init_mac_pll(p_scu, p_cfg); 942 } 943 944 reg_304 = readl(&p_scu->clk_sel2); 945 reg_310 = readl(&p_scu->clk_sel4); 946 947 reg_304 &= ~GENMASK(19, 16); 948 949 /* set RMII 1/2 clock divider */ 950 reg_304 |= (p_cfg->n & 0x7) << 16; 951 952 /* RMII clock source selection */ 953 if (p_cfg->src == ASPEED_CLK_HPLL) 954 reg_304 |= BIT(19); 955 956 /* set RMII 3/4 clock divider */ 957 reg_310 &= ~GENMASK(18, 16); 958 reg_310 |= (0x3 << 16); 959 960 writel(reg_304, &p_scu->clk_sel2); 961 writel(reg_310, &p_scu->clk_sel4); 962 } 963 964 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 965 { 966 u32 reset_bit; 967 u32 clkstop_bit; 968 969 switch (index) { 970 case 1: 971 reset_bit = BIT(ASPEED_RESET_MAC1); 972 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 973 writel(reset_bit, &scu->sysreset_ctrl1); 974 udelay(100); 975 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 976 mdelay(10); 977 writel(reset_bit, &scu->sysreset_clr_ctrl1); 978 break; 979 case 2: 980 reset_bit = BIT(ASPEED_RESET_MAC2); 981 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 982 writel(reset_bit, &scu->sysreset_ctrl1); 983 udelay(100); 984 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 985 mdelay(10); 986 writel(reset_bit, &scu->sysreset_clr_ctrl1); 987 break; 988 case 3: 989 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 990 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 991 writel(reset_bit, &scu->sysreset_ctrl2); 992 udelay(100); 993 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 994 mdelay(10); 995 writel(reset_bit, &scu->sysreset_clr_ctrl2); 996 break; 997 case 4: 998 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 999 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 1000 writel(reset_bit, &scu->sysreset_ctrl2); 1001 udelay(100); 1002 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1003 mdelay(10); 1004 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1005 break; 1006 default: 1007 return -EINVAL; 1008 } 1009 1010 return 0; 1011 } 1012 1013 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 1014 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 1015 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 1016 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 1017 { 1018 u32 clk_sel = readl(&scu->clk_sel1); 1019 1020 /* Configure RSA clock = HPLL/4 */ 1021 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 1022 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 1023 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(3); 1024 1025 writel(clk_sel, &scu->clk_sel1); 1026 } 1027 1028 #define SCU_CLKSTOP_SDIO 4 1029 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 1030 { 1031 u32 reset_bit; 1032 u32 clkstop_bit; 1033 1034 reset_bit = BIT(ASPEED_RESET_SD - 32); 1035 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 1036 1037 writel(reset_bit, &scu->sysreset_ctrl2); 1038 1039 udelay(100); 1040 //enable clk 1041 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1042 mdelay(10); 1043 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1044 1045 return 0; 1046 } 1047 1048 #define SCU_CLKSTOP_EXTSD 31 1049 #define SCU_CLK_SD_MASK (0x7 << 28) 1050 #define SCU_CLK_SD_DIV(x) ((x) << 28) 1051 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 1052 1053 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 1054 { 1055 u32 clk_sel = readl(&scu->clk_sel4); 1056 u32 enableclk_bit; 1057 u32 rate = 0; 1058 u32 div = 0; 1059 int i = 0; 1060 1061 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 1062 1063 /* ast2600 sd controller max clk is 200Mhz : 1064 * use apll for clock source 800/4 = 200 : controller max is 200mhz 1065 */ 1066 rate = ast2600_get_apll_rate(scu); 1067 for (i = 0; i < 8; i++) { 1068 div = (i + 1) * 2; 1069 if ((rate / div) <= 200000000) 1070 break; 1071 } 1072 clk_sel &= ~SCU_CLK_SD_MASK; 1073 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 1074 writel(clk_sel, &scu->clk_sel4); 1075 1076 //enable clk 1077 setbits_le32(&scu->clk_sel4, enableclk_bit); 1078 1079 return 0; 1080 } 1081 1082 #define SCU_CLKSTOP_EMMC 27 1083 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 1084 { 1085 u32 reset_bit; 1086 u32 clkstop_bit; 1087 1088 reset_bit = BIT(ASPEED_RESET_EMMC); 1089 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 1090 1091 writel(reset_bit, &scu->sysreset_ctrl1); 1092 udelay(100); 1093 //enable clk 1094 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1095 mdelay(10); 1096 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1097 1098 return 0; 1099 } 1100 1101 #define SCU_CLKSTOP_EXTEMMC 15 1102 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1103 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 1104 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1105 1106 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1107 { 1108 u32 revision_id = readl(&scu->chip_id1); 1109 u32 clk_sel = readl(&scu->clk_sel1); 1110 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1111 u32 rate = 0; 1112 u32 div = 0; 1113 int i = 0; 1114 1115 /* 1116 * ast2600 eMMC controller max clk is 200Mhz 1117 * HPll->1/2->|\ 1118 * |->SCU300[11]->SCU300[14:12][1/N] + 1119 * MPLL------>|/ | 1120 * +----------------------------------------------+ 1121 * | 1122 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1123 */ 1124 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1125 //AST2600A1 : use mpll to be clk source 1126 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1127 for (i = 0; i < 8; i++) { 1128 div = (i + 1) * 2; 1129 if ((rate / div) <= 200000000) 1130 break; 1131 } 1132 1133 clk_sel &= ~SCU_CLK_EMMC_MASK; 1134 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1135 writel(clk_sel, &scu->clk_sel1); 1136 1137 } else { 1138 //AST2600A0 : use hpll to be clk source 1139 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1140 1141 for (i = 0; i < 8; i++) { 1142 div = (i + 1) * 4; 1143 if ((rate / div) <= 200000000) 1144 break; 1145 } 1146 1147 clk_sel &= ~SCU_CLK_EMMC_MASK; 1148 clk_sel |= SCU_CLK_EMMC_DIV(i); 1149 writel(clk_sel, &scu->clk_sel1); 1150 } 1151 setbits_le32(&scu->clk_sel1, enableclk_bit); 1152 1153 return 0; 1154 } 1155 1156 #define SCU_CLKSTOP_FSICLK 30 1157 1158 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1159 { 1160 u32 reset_bit; 1161 u32 clkstop_bit; 1162 1163 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1164 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1165 1166 /* The FSI clock is shared between masters. If it's already on 1167 * don't touch it, as that will reset the existing master. 1168 */ 1169 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1170 debug("%s: already running, not touching it\n", __func__); 1171 return 0; 1172 } 1173 1174 writel(reset_bit, &scu->sysreset_ctrl2); 1175 udelay(100); 1176 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1177 mdelay(10); 1178 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1179 1180 return 0; 1181 } 1182 1183 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1184 { 1185 u32 reset_bit; 1186 u32 clkstop_bit; 1187 1188 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1189 clkstop_bit = BIT(14); 1190 1191 writel(reset_bit, &scu->sysreset_ctrl1); 1192 udelay(100); 1193 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1194 mdelay(20); 1195 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1196 1197 return 0; 1198 } 1199 1200 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1201 { 1202 u32 reset_bit; 1203 u32 clkstop_bit; 1204 1205 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1206 clkstop_bit = BIT(7); 1207 1208 writel(reset_bit, &scu->sysreset_ctrl1); 1209 udelay(100); 1210 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1211 mdelay(20); 1212 1213 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1214 1215 return 0; 1216 } 1217 1218 /* also known as yclk */ 1219 static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) 1220 { 1221 u32 reset_bit; 1222 u32 clkstop_bit; 1223 1224 reset_bit = BIT(ASPEED_RESET_HACE); 1225 clkstop_bit = BIT(13); 1226 1227 writel(reset_bit, &scu->sysreset_ctrl1); 1228 udelay(100); 1229 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1230 mdelay(20); 1231 1232 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1233 1234 return 0; 1235 } 1236 1237 static ulong ast2600_enable_rsaeccclk(struct ast2600_scu *scu) 1238 { 1239 u32 clkstop_bit; 1240 1241 clkstop_bit = BIT(24); 1242 1243 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1244 mdelay(20); 1245 1246 return 0; 1247 } 1248 1249 static int ast2600_clk_enable(struct clk *clk) 1250 { 1251 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1252 1253 switch (clk->id) { 1254 case ASPEED_CLK_GATE_MAC1CLK: 1255 ast2600_configure_mac(priv->scu, 1); 1256 break; 1257 case ASPEED_CLK_GATE_MAC2CLK: 1258 ast2600_configure_mac(priv->scu, 2); 1259 break; 1260 case ASPEED_CLK_GATE_MAC3CLK: 1261 ast2600_configure_mac(priv->scu, 3); 1262 break; 1263 case ASPEED_CLK_GATE_MAC4CLK: 1264 ast2600_configure_mac(priv->scu, 4); 1265 break; 1266 case ASPEED_CLK_GATE_SDCLK: 1267 ast2600_enable_sdclk(priv->scu); 1268 break; 1269 case ASPEED_CLK_GATE_SDEXTCLK: 1270 ast2600_enable_extsdclk(priv->scu); 1271 break; 1272 case ASPEED_CLK_GATE_EMMCCLK: 1273 ast2600_enable_emmcclk(priv->scu); 1274 break; 1275 case ASPEED_CLK_GATE_EMMCEXTCLK: 1276 ast2600_enable_extemmcclk(priv->scu); 1277 break; 1278 case ASPEED_CLK_GATE_FSICLK: 1279 ast2600_enable_fsiclk(priv->scu); 1280 break; 1281 case ASPEED_CLK_GATE_USBPORT1CLK: 1282 ast2600_enable_usbahclk(priv->scu); 1283 break; 1284 case ASPEED_CLK_GATE_USBPORT2CLK: 1285 ast2600_enable_usbbhclk(priv->scu); 1286 break; 1287 case ASPEED_CLK_GATE_YCLK: 1288 ast2600_enable_haceclk(priv->scu); 1289 break; 1290 case ASPEED_CLK_GATE_RSAECCCLK: 1291 ast2600_enable_rsaeccclk(priv->scu); 1292 break; 1293 default: 1294 pr_err("can't enable clk\n"); 1295 return -ENOENT; 1296 } 1297 1298 return 0; 1299 } 1300 1301 struct clk_ops ast2600_clk_ops = { 1302 .get_rate = ast2600_clk_get_rate, 1303 .set_rate = ast2600_clk_set_rate, 1304 .enable = ast2600_clk_enable, 1305 }; 1306 1307 static int ast2600_clk_probe(struct udevice *dev) 1308 { 1309 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1310 u32 uart_clk_source; 1311 1312 priv->scu = devfdt_get_addr_ptr(dev); 1313 if (IS_ERR(priv->scu)) 1314 return PTR_ERR(priv->scu); 1315 1316 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1317 1318 if (uart_clk_source) { 1319 if (uart_clk_source & GENMASK(5, 0)) 1320 setbits_le32(&priv->scu->clk_sel4, 1321 uart_clk_source & GENMASK(5, 0)); 1322 if (uart_clk_source & GENMASK(12, 6)) 1323 setbits_le32(&priv->scu->clk_sel5, 1324 uart_clk_source & GENMASK(12, 6)); 1325 } 1326 1327 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1328 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1329 ast2600_configure_mac12_clk(priv->scu, dev); 1330 ast2600_configure_mac34_clk(priv->scu, dev); 1331 ast2600_configure_rsa_ecc_clk(priv->scu); 1332 1333 return 0; 1334 } 1335 1336 static int ast2600_clk_bind(struct udevice *dev) 1337 { 1338 int ret; 1339 1340 /* The reset driver does not have a device node, so bind it here */ 1341 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1342 if (ret) 1343 debug("Warning: No reset driver: ret=%d\n", ret); 1344 1345 return 0; 1346 } 1347 1348 struct aspeed_clks { 1349 ulong id; 1350 const char *name; 1351 }; 1352 1353 static struct aspeed_clks aspeed_clk_names[] = { 1354 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1355 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1356 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1357 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1358 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1359 { ASPEED_CLK_HUARTX, "huxclk" }, 1360 }; 1361 1362 int soc_clk_dump(void) 1363 { 1364 struct udevice *dev; 1365 struct clk clk; 1366 unsigned long rate; 1367 int i, ret; 1368 1369 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1370 &dev); 1371 if (ret) 1372 return ret; 1373 1374 printf("Clk\t\tHz\n"); 1375 1376 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1377 clk.id = aspeed_clk_names[i].id; 1378 ret = clk_request(dev, &clk); 1379 if (ret < 0) { 1380 debug("%s clk_request() failed: %d\n", __func__, ret); 1381 continue; 1382 } 1383 1384 ret = clk_get_rate(&clk); 1385 rate = ret; 1386 1387 clk_free(&clk); 1388 1389 if (ret == -ENOTSUPP) { 1390 printf("clk ID %lu not supported yet\n", 1391 aspeed_clk_names[i].id); 1392 continue; 1393 } 1394 if (ret < 0) { 1395 printf("%s %lu: get_rate err: %d\n", __func__, 1396 aspeed_clk_names[i].id, ret); 1397 continue; 1398 } 1399 1400 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1401 aspeed_clk_names[i].id, rate); 1402 } 1403 1404 return 0; 1405 } 1406 1407 static const struct udevice_id ast2600_clk_ids[] = { 1408 { 1409 .compatible = "aspeed,ast2600-scu", 1410 }, 1411 {} 1412 }; 1413 1414 U_BOOT_DRIVER(aspeed_scu) = { 1415 .name = "aspeed_scu", 1416 .id = UCLASS_CLK, 1417 .of_match = ast2600_clk_ids, 1418 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1419 .ops = &ast2600_clk_ops, 1420 .bind = ast2600_clk_bind, 1421 .probe = ast2600_clk_probe, 1422 }; 1423