1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  * Ryan Chen <ryan_chen@aspeedtech.com>
5  */
6 
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <asm/io.h>
11 #include <asm/arch/scu_ast2600.h>
12 #include <dm/lists.h>
13 #include <dt-bindings/clock/ast2500-scu.h>
14 
15 /*
16  * MAC Clock Delay settings, taken from Aspeed SDK
17  */
18 #define RGMII_TXCLK_ODLY		8
19 #define RMII_RXCLK_IDLY		2
20 
21 /*
22  * TGMII Clock Duty constants, taken from Aspeed SDK
23  */
24 #define RGMII2_TXCK_DUTY	0x66
25 #define RGMII1_TXCK_DUTY	0x64
26 
27 #define D2PLL_DEFAULT_RATE	(250 * 1000 * 1000)
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 /*
32  * Clock divider/multiplier configuration struct.
33  * For H-PLL and M-PLL the formula is
34  * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
35  * M - Numerator
36  * N - Denumerator
37  * P - Post Divider
38  * They have the same layout in their control register.
39  *
40  * D-PLL and D2-PLL have extra divider (OD + 1), which is not
41  * yet needed and ignored by clock configurations.
42  */
43 struct ast2600_div_config {
44 	unsigned int num;
45 	unsigned int denum;
46 	unsigned int post_div;
47 };
48 
49 /*
50  * Get the rate of the M-PLL clock from input clock frequency and
51  * the value of the M-PLL Parameter Register.
52  */
53 static ulong ast2600_get_mpll_rate(ulong clkin, u32 mpll_reg)
54 {
55 	const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
56 	const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
57 			>> SCU_MPLL_DENUM_SHIFT;
58 	const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
59 			>> SCU_MPLL_POST_SHIFT;
60 
61 	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
62 }
63 
64 /*
65  * Get the rate of the H-PLL clock from input clock frequency and
66  * the value of the H-PLL Parameter Register.
67  */
68 static ulong ast2600_get_hpll_rate(ulong clkin, u32 hpll_reg)
69 {
70 	const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
71 	const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
72 			>> SCU_HPLL_DENUM_SHIFT;
73 	const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
74 			>> SCU_HPLL_POST_SHIFT;
75 
76 	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
77 }
78 
79 static ulong ast2600_get_clkin(struct ast2600_scu *scu)
80 {
81 	return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
82 			? 25 * 1000 * 1000 : 24 * 1000 * 1000;
83 }
84 
85 /**
86  * Get current rate or uart clock
87  *
88  * @scu SCU registers
89  * @uart_index UART index, 1-5
90  *
91  * @return current setting for uart clock rate
92  */
93 static ulong ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_index)
94 {
95 	/*
96 	 * ast2600 datasheet is very confusing when it comes to UART clocks,
97 	 * especially when CLKIN = 25 MHz. The settings are in
98 	 * different registers and it is unclear how they interact.
99 	 *
100 	 * This has only been tested with default settings and CLKIN = 24 MHz.
101 	 */
102 	ulong uart_clkin;
103 
104 	if (readl(&scu->misc_ctrl2) &
105 	    (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
106 		uart_clkin = 192 * 1000 * 1000;
107 	else
108 		uart_clkin = 24 * 1000 * 1000;
109 
110 	if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
111 		uart_clkin /= 13;
112 
113 	return uart_clkin;
114 }
115 
116 static ulong ast2600_clk_get_rate(struct clk *clk)
117 {
118 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
119 	ulong clkin = ast2600_get_clkin(priv->scu);
120 	ulong rate;
121 
122 	switch (clk->id) {
123 	case PLL_HPLL:
124 	case ARMCLK:
125 		/*
126 		 * This ignores dynamic/static slowdown of ARMCLK and may
127 		 * be inaccurate.
128 		 */
129 		rate = ast2600_get_hpll_rate(clkin,
130 					     readl(&priv->scu->h_pll_param));
131 		break;
132 	case MCLK_DDR:
133 		rate = ast2600_get_mpll_rate(clkin,
134 					     readl(&priv->scu->m_pll_param));
135 		break;
136 	case BCLK_PCLK:
137 		{
138 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
139 						  & SCU_PCLK_DIV_MASK)
140 						 >> SCU_PCLK_DIV_SHIFT);
141 			rate = ast2600_get_hpll_rate(clkin,
142 						     readl(&priv->
143 							   scu->h_pll_param));
144 			rate = rate / apb_div;
145 		}
146 		break;
147 	case PCLK_UART1:
148 		rate = ast2600_get_uart_clk_rate(priv->scu, 1);
149 		break;
150 	case PCLK_UART2:
151 		rate = ast2600_get_uart_clk_rate(priv->scu, 2);
152 		break;
153 	case PCLK_UART3:
154 		rate = ast2600_get_uart_clk_rate(priv->scu, 3);
155 		break;
156 	case PCLK_UART4:
157 		rate = ast2600_get_uart_clk_rate(priv->scu, 4);
158 		break;
159 	case PCLK_UART5:
160 		rate = ast2600_get_uart_clk_rate(priv->scu, 5);
161 		break;
162 	default:
163 		return -ENOENT;
164 	}
165 
166 	return rate;
167 }
168 
169 struct ast2600_clock_config {
170 	ulong input_rate;
171 	ulong rate;
172 	struct ast2600_div_config cfg;
173 };
174 
175 static const struct ast2600_clock_config ast2600_clock_config_defaults[] = {
176 	{ 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
177 };
178 
179 static bool ast2600_get_clock_config_default(ulong input_rate,
180 					     ulong requested_rate,
181 					     struct ast2600_div_config *cfg)
182 {
183 	int i;
184 
185 	for (i = 0; i < ARRAY_SIZE(ast2600_clock_config_defaults); i++) {
186 		const struct ast2600_clock_config *default_cfg =
187 			&ast2600_clock_config_defaults[i];
188 		if (default_cfg->input_rate == input_rate &&
189 		    default_cfg->rate == requested_rate) {
190 			*cfg = default_cfg->cfg;
191 			return true;
192 		}
193 	}
194 
195 	return false;
196 }
197 
198 /*
199  * @input_rate - the rate of input clock in Hz
200  * @requested_rate - desired output rate in Hz
201  * @div - this is an IN/OUT parameter, at input all fields of the config
202  * need to be set to their maximum allowed values.
203  * The result (the best config we could find), would also be returned
204  * in this structure.
205  *
206  * @return The clock rate, when the resulting div_config is used.
207  */
208 static ulong ast2600_calc_clock_config(ulong input_rate, ulong requested_rate,
209 				       struct ast2600_div_config *cfg)
210 {
211 	/*
212 	 * The assumption is that kHz precision is good enough and
213 	 * also enough to avoid overflow when multiplying.
214 	 */
215 	const ulong input_rate_khz = input_rate / 1000;
216 	const ulong rate_khz = requested_rate / 1000;
217 	const struct ast2600_div_config max_vals = *cfg;
218 	struct ast2600_div_config it = { 0, 0, 0 };
219 	ulong delta = rate_khz;
220 	ulong new_rate_khz = 0;
221 
222 	/*
223 	 * Look for a well known frequency first.
224 	 */
225 	if (ast2600_get_clock_config_default(input_rate, requested_rate, cfg))
226 		return requested_rate;
227 
228 	for (; it.denum <= max_vals.denum; ++it.denum) {
229 		for (it.post_div = 0; it.post_div <= max_vals.post_div;
230 		     ++it.post_div) {
231 			it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
232 			    * (it.denum + 1);
233 			if (it.num > max_vals.num)
234 				continue;
235 
236 			new_rate_khz = (input_rate_khz
237 					* ((it.num + 1) / (it.denum + 1)))
238 			    / (it.post_div + 1);
239 
240 			/* Keep the rate below requested one. */
241 			if (new_rate_khz > rate_khz)
242 				continue;
243 
244 			if (new_rate_khz - rate_khz < delta) {
245 				delta = new_rate_khz - rate_khz;
246 				*cfg = it;
247 				if (delta == 0)
248 					return new_rate_khz * 1000;
249 			}
250 		}
251 	}
252 
253 	return new_rate_khz * 1000;
254 }
255 
256 static ulong ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate)
257 {
258 	ulong clkin = ast2600_get_clkin(scu);
259 	u32 mpll_reg;
260 	struct ast2600_div_config div_cfg = {
261 		.num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
262 		.denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
263 		.post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
264 	};
265 
266 	ast2600_calc_clock_config(clkin, rate, &div_cfg);
267 
268 	mpll_reg = readl(&scu->m_pll_param);
269 	mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
270 		      | SCU_MPLL_DENUM_MASK);
271 	mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
272 	    | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
273 	    | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
274 
275 	writel(mpll_reg, &scu->m_pll_param);
276 
277 	return ast2600_get_mpll_rate(clkin, mpll_reg);
278 }
279 
280 static ulong ast2600_configure_mac(struct ast2600_scu *scu, int index)
281 {
282 	ulong clkin = ast2600_get_clkin(scu);
283 	ulong hpll_rate = ast2600_get_hpll_rate(clkin,
284 						readl(&scu->h_pll_param));
285 	ulong required_rate;
286 	u32 hwstrap;
287 	u32 divisor;
288 	u32 reset_bit;
289 	u32 clkstop_bit;
290 
291 	/*
292 	 * According to data sheet, for 10/100 mode the MAC clock frequency
293 	 * should be at least 25MHz and for 1000 mode at least 100MHz
294 	 */
295 	hwstrap = readl(&scu->hwstrap);
296 	if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
297 		required_rate = 100 * 1000 * 1000;
298 	else
299 		required_rate = 25 * 1000 * 1000;
300 
301 	divisor = hpll_rate / required_rate;
302 
303 	if (divisor < 4) {
304 		/* Clock can't run fast enough, but let's try anyway */
305 		debug("MAC clock too slow\n");
306 		divisor = 4;
307 	} else if (divisor > 16) {
308 		/* Can't slow down the clock enough, but let's try anyway */
309 		debug("MAC clock too fast\n");
310 		divisor = 16;
311 	}
312 
313 	switch (index) {
314 	case 1:
315 		reset_bit = SCU_SYSRESET_MAC1;
316 		clkstop_bit = SCU_CLKSTOP_MAC1;
317 		break;
318 	case 2:
319 		reset_bit = SCU_SYSRESET_MAC2;
320 		clkstop_bit = SCU_CLKSTOP_MAC2;
321 		break;
322 	default:
323 		return -EINVAL;
324 	}
325 
326 	clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
327 			((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
328 
329 	/*
330 	 * Disable MAC, start its clock and re-enable it.
331 	 * The procedure and the delays (100us & 10ms) are
332 	 * specified in the datasheet.
333 	 */
334 	setbits_le32(&scu->sysreset_ctrl1, reset_bit);
335 	udelay(100);
336 	clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
337 	mdelay(10);
338 	clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
339 
340 	writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
341 	       | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
342 	       &scu->clk_duty_sel);
343 
344 	return required_rate;
345 }
346 
347 static ulong ast2600_configure_d2pll(struct ast2600_scu *scu, ulong rate)
348 {
349 	/*
350 	 * The values and the meaning of the next three
351 	 * parameters are undocumented. Taken from Aspeed SDK.
352 	 *
353 	 * TODO(clg@kaod.org): the SIP and SIC values depend on the
354 	 * Numerator value
355 	 */
356 	const u32 d2_pll_ext_param = 0x2c;
357 	const u32 d2_pll_sip = 0x11;
358 	const u32 d2_pll_sic = 0x18;
359 	u32 clk_delay_settings =
360 	    (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
361 	    | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
362 	    | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
363 	    | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
364 	struct ast2600_div_config div_cfg = {
365 		.num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
366 		.denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
367 		.post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
368 	};
369 	ulong clkin = ast2600_get_clkin(scu);
370 	ulong new_rate;
371 
372 	writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
373 	       | SCU_D2PLL_EXT1_OFF
374 	       | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
375 
376 	/*
377 	 * Select USB2.0 port1 PHY clock as a clock source for GCRT.
378 	 * This would disconnect it from D2-PLL.
379 	 */
380 	clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
381 			SCU_MISC_GCRT_USB20CLK);
382 
383 	new_rate = ast2600_calc_clock_config(clkin, rate, &div_cfg);
384 	writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
385 	       | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
386 	       | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
387 	       | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
388 	       | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
389 	       &scu->d2_pll_param);
390 
391 	clrbits_le32(&scu->d2_pll_ext_param[0],
392 		     SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
393 
394 	clrsetbits_le32(&scu->misc_ctrl2,
395 			SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
396 			| SCU_MISC2_RGMII_CLKDIV_MASK |
397 			SCU_MISC2_RMII_CLKDIV_MASK,
398 			(4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
399 
400 	writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
401 	writel(clk_delay_settings, &scu->mac_clk_delay_100M);
402 	writel(clk_delay_settings, &scu->mac_clk_delay_10M);
403 
404 	return new_rate;
405 }
406 
407 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate)
408 {
409 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
410 
411 	ulong new_rate;
412 	switch (clk->id) {
413 	case PLL_MPLL:
414 	case MCLK_DDR:
415 		new_rate = ast2600_configure_ddr(priv->scu, rate);
416 		break;
417 	case PLL_D2PLL:
418 		new_rate = ast2600_configure_d2pll(priv->scu, rate);
419 		break;
420 	default:
421 		return -ENOENT;
422 	}
423 
424 	return new_rate;
425 }
426 
427 static int ast2600_clk_enable(struct clk *clk)
428 {
429 	struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
430 
431 	switch (clk->id) {
432 	/*
433 	 * For MAC clocks the clock rate is
434 	 * configured based on whether RGMII or RMII mode has been selected
435 	 * through hardware strapping.
436 	 */
437 	case PCLK_MAC1:
438 		ast2600_configure_mac(priv->scu, 1);
439 		break;
440 	case PCLK_MAC2:
441 		ast2600_configure_mac(priv->scu, 2);
442 		break;
443 	case PLL_D2PLL:
444 		ast2600_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
445 		break;
446 	default:
447 		return -ENOENT;
448 	}
449 
450 	return 0;
451 }
452 
453 struct clk_ops ast2600_clk_ops = {
454 	.get_rate = ast2600_clk_get_rate,
455 	.set_rate = ast2600_clk_set_rate,
456 	.enable = ast2600_clk_enable,
457 };
458 
459 static int ast2600_clk_probe(struct udevice *dev)
460 {
461 	struct ast2600_clk_priv *priv = dev_get_priv(dev);
462 
463 	priv->scu = devfdt_get_addr_ptr(dev);
464 	if (IS_ERR(priv->scu))
465 		return PTR_ERR(priv->scu);
466 
467 	return 0;
468 }
469 
470 static int ast2600_clk_bind(struct udevice *dev)
471 {
472 	int ret;
473 
474 	/* The reset driver does not have a device node, so bind it here */
475 	ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
476 	if (ret)
477 		debug("Warning: No reset driver: ret=%d\n", ret);
478 
479 	return 0;
480 }
481 
482 static const struct udevice_id ast2600_clk_ids[] = {
483 	{ .compatible = "aspeed,ast2600-scu" },
484 	{ }
485 };
486 
487 U_BOOT_DRIVER(aspeed_ast2600_scu) = {
488 	.name		= "aspeed_ast2600_scu",
489 	.id		= UCLASS_CLK,
490 	.of_match	= ast2600_clk_ids,
491 	.priv_auto_alloc_size = sizeof(struct ast2600_clk_priv),
492 	.ops		= &ast2600_clk_ops,
493 	.bind		= ast2600_clk_bind,
494 	.probe		= ast2600_clk_probe,
495 };
496