1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041d410 22 #define MAC_DEF_DELAY_100M 0x00410410 23 #define MAC_DEF_DELAY_10M 0x00410410 24 25 #define MAC34_DEF_DELAY_1G 0x00104208 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 {.in = AST2600_CLK_IN, .out = 400000000, 77 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 78 .cfg.ext_reg = 0x31, 79 }, 80 {.in = AST2600_CLK_IN, .out = 200000000, 81 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 82 .cfg.ext_reg = 0x3f 83 }, 84 {.in = AST2600_CLK_IN, .out = 334000000, 85 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 86 .cfg.ext_reg = 0x14d 87 }, 88 89 {.in = AST2600_CLK_IN, .out = 1000000000, 90 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 91 .cfg.ext_reg = 0x3d 92 }, 93 94 {.in = AST2600_CLK_IN, .out = 50000000, 95 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 96 .cfg.ext_reg = 0x31 97 }, 98 }; 99 100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 101 { 102 u32 clkin = AST2600_CLK_IN; 103 u32 pll_reg = 0; 104 unsigned int mult, div = 1; 105 106 switch(pll_idx) { 107 case ASPEED_CLK_HPLL: 108 pll_reg = readl(&scu->h_pll_param); 109 break; 110 case ASPEED_CLK_MPLL: 111 pll_reg = readl(&scu->m_pll_param); 112 break; 113 case ASPEED_CLK_DPLL: 114 pll_reg = readl(&scu->d_pll_param); 115 break; 116 case ASPEED_CLK_EPLL: 117 pll_reg = readl(&scu->e_pll_param); 118 break; 119 120 } 121 if (pll_reg & BIT(24)) { 122 /* Pass through mode */ 123 mult = div = 1; 124 } else { 125 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 126 union ast2600_pll_reg reg; 127 reg.w = pll_reg; 128 mult = (reg.b.m + 1) / (reg.b.n + 1); 129 div = (reg.b.p + 1); 130 } 131 return ((clkin * mult)/div); 132 133 } 134 135 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 136 { 137 u32 clkin = AST2600_CLK_IN; 138 u32 apll_reg = readl(&scu->a_pll_param); 139 unsigned int mult, div = 1; 140 141 if (apll_reg & BIT(20)) { 142 /* Pass through mode */ 143 mult = div = 1; 144 } else { 145 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 146 u32 m = (apll_reg >> 5) & 0x3f; 147 u32 od = (apll_reg >> 4) & 0x1; 148 u32 n = apll_reg & 0xf; 149 150 mult = (2 - od) * (m + 2); 151 div = n + 1; 152 } 153 return ((clkin * mult)/div); 154 } 155 156 static u32 ast2600_a0_axi_ahb_div_table[] = { 157 2, 2, 3, 4, 158 }; 159 160 static u32 ast2600_a1_axi_ahb_div0_table[] = { 161 3, 2, 3, 4, 162 }; 163 164 static u32 ast2600_a1_axi_ahb_div1_table[] = { 165 3, 4, 6, 8, 166 }; 167 168 static u32 ast2600_a1_axi_ahb_default_table[] = { 169 3, 4, 3, 4, 2, 2, 2, 2, 170 }; 171 172 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 173 { 174 u32 hw_rev = readl(&scu->chip_id0); 175 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 176 u32 axi_div = 1; 177 u32 ahb_div = 0; 178 u32 rate = 0; 179 180 if (hw_rev & BIT(16)) { 181 if(hwstrap1 & BIT(16)) { 182 ast2600_a1_axi_ahb_div1_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 183 axi_div = 1; 184 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 185 } else { 186 ast2600_a1_axi_ahb_div0_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 187 axi_div = 2; 188 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 189 } 190 } else { 191 //a0 : fix axi = hpll / 2 192 axi_div = 2; 193 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 194 } 195 196 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 197 return (rate / axi_div / ahb_div); 198 } 199 200 static u32 ast2600_hpll_pclk1_div_table[] = { 201 4, 8, 12, 16, 20, 24, 28, 32, 202 }; 203 204 static u32 ast2600_hpll_pclk2_div_table[] = { 205 2, 4, 6, 8, 10, 12, 14, 16, 206 }; 207 208 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 209 { 210 u32 clk_sel1 = readl(&scu->clk_sel1); 211 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 212 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 213 214 return (rate / apb_div); 215 } 216 217 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 218 { 219 u32 clk_sel4 = readl(&scu->clk_sel4); 220 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 221 u32 rate = ast2600_get_hclk(scu); 222 223 return (rate / apb_div); 224 } 225 226 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 227 { 228 u32 clk_in = 0; 229 u32 uxclk_sel = readl(&scu->clk_sel5); 230 231 uxclk_sel &= 0x3; 232 switch(uxclk_sel) { 233 case 0: 234 clk_in = ast2600_get_apll_rate(scu) / 4; 235 break; 236 case 1: 237 clk_in = ast2600_get_apll_rate(scu) / 2; 238 break; 239 case 2: 240 clk_in = ast2600_get_apll_rate(scu); 241 break; 242 case 3: 243 clk_in = ast2600_get_hclk(scu); 244 break; 245 } 246 247 return clk_in; 248 } 249 250 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 251 { 252 u32 clk_in = 0; 253 u32 huclk_sel = readl(&scu->clk_sel5); 254 255 huclk_sel = ((huclk_sel >> 3) & 0x3); 256 switch(huclk_sel) { 257 case 0: 258 clk_in = ast2600_get_apll_rate(scu) / 4; 259 break; 260 case 1: 261 clk_in = ast2600_get_apll_rate(scu) / 2; 262 break; 263 case 2: 264 clk_in = ast2600_get_apll_rate(scu); 265 break; 266 case 3: 267 clk_in = ast2600_get_hclk(scu); 268 break; 269 } 270 271 return clk_in; 272 } 273 274 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 275 { 276 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 277 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 278 unsigned int mult, div; 279 280 u32 n = (div_reg >> 8) & 0x3ff; 281 u32 r = div_reg & 0xff; 282 283 mult = r; 284 div = (n * 2); 285 return (clk_in * mult)/div; 286 } 287 288 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 289 { 290 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 291 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 292 293 unsigned int mult, div; 294 295 u32 n = (div_reg >> 8) & 0x3ff; 296 u32 r = div_reg & 0xff; 297 298 mult = r; 299 div = (n * 2); 300 return (clk_in * mult)/div; 301 } 302 303 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 304 { 305 u32 clkin = 0; 306 u32 clk_sel = readl(&scu->clk_sel4); 307 u32 div = (clk_sel >> 28) & 0x7; 308 309 if(clk_sel & BIT(8)) { 310 clkin = ast2600_get_apll_rate(scu); 311 } else { 312 clkin = ast2600_get_hclk(scu); 313 } 314 div = (div + 1) << 1; 315 316 return (clkin / div); 317 } 318 319 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 320 { 321 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 322 u32 clk_sel = readl(&scu->clk_sel1); 323 u32 div = (clk_sel >> 12) & 0x7; 324 325 div = (div + 1) << 2; 326 327 return (clkin / div); 328 } 329 330 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 331 { 332 u32 uart_sel = readl(&scu->clk_sel4); 333 u32 uart_sel5 = readl(&scu->clk_sel5); 334 ulong uart_clk = 0; 335 336 switch(uart_idx) { 337 case 1: 338 case 2: 339 case 3: 340 case 4: 341 case 6: 342 if(uart_sel & BIT(uart_idx - 1)) 343 uart_clk = ast2600_get_uart_huxclk_rate(scu) ; 344 else 345 uart_clk = ast2600_get_uart_uxclk_rate(scu) ; 346 break; 347 case 5: //24mhz is come form usb phy 48Mhz 348 { 349 u8 uart5_clk_sel = 0; 350 //high bit 351 if (readl(&scu->misc_ctrl1) & BIT(12)) 352 uart5_clk_sel = 0x2; 353 else 354 uart5_clk_sel = 0x0; 355 356 if (readl(&scu->clk_sel2) & BIT(14)) 357 uart5_clk_sel |= 0x1; 358 359 switch(uart5_clk_sel) { 360 case 0: 361 uart_clk = 24000000; 362 break; 363 case 1: 364 uart_clk = 192000000; 365 break; 366 case 2: 367 uart_clk = 24000000/13; 368 break; 369 case 3: 370 uart_clk = 192000000/13; 371 break; 372 } 373 } 374 break; 375 case 7: 376 case 8: 377 case 9: 378 case 10: 379 case 11: 380 case 12: 381 case 13: 382 if(uart_sel5 & BIT(uart_idx - 1)) 383 uart_clk = ast2600_get_uart_huxclk_rate(scu); 384 else 385 uart_clk = ast2600_get_uart_uxclk_rate(scu); 386 break; 387 } 388 389 return uart_clk; 390 } 391 392 static ulong ast2600_clk_get_rate(struct clk *clk) 393 { 394 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 395 ulong rate = 0; 396 397 switch (clk->id) { 398 case ASPEED_CLK_HPLL: 399 case ASPEED_CLK_EPLL: 400 case ASPEED_CLK_DPLL: 401 case ASPEED_CLK_MPLL: 402 rate = ast2600_get_pll_rate(priv->scu, clk->id); 403 break; 404 case ASPEED_CLK_AHB: 405 rate = ast2600_get_hclk(priv->scu); 406 break; 407 case ASPEED_CLK_APB1: 408 rate = ast2600_get_pclk1(priv->scu); 409 break; 410 case ASPEED_CLK_APB2: 411 rate = ast2600_get_pclk2(priv->scu); 412 break; 413 case ASPEED_CLK_APLL: 414 rate = ast2600_get_apll_rate(priv->scu); 415 break; 416 case ASPEED_CLK_GATE_UART1CLK: 417 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 418 break; 419 case ASPEED_CLK_GATE_UART2CLK: 420 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 421 break; 422 case ASPEED_CLK_GATE_UART3CLK: 423 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 424 break; 425 case ASPEED_CLK_GATE_UART4CLK: 426 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 427 break; 428 case ASPEED_CLK_GATE_UART5CLK: 429 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 430 break; 431 case ASPEED_CLK_SDIO: 432 rate = ast2600_get_sdio_clk_rate(priv->scu); 433 break; 434 case ASPEED_CLK_EMMC: 435 rate = ast2600_get_emmc_clk_rate(priv->scu); 436 break; 437 case ASPEED_CLK_UARTX: 438 rate = ast2600_get_uart_uxclk_rate(priv->scu); 439 break; 440 case ASPEED_CLK_HUARTX: 441 rate = ast2600_get_uart_huxclk_rate(priv->scu); 442 break; 443 default: 444 pr_debug("can't get clk rate \n"); 445 return -ENOENT; 446 break; 447 } 448 449 return rate; 450 } 451 452 /** 453 * @brief lookup PLL divider config by input/output rate 454 * @param[in] *pll - PLL descriptor 455 * @return true - if PLL divider config is found, false - else 456 * 457 * The function caller shall fill "pll->in" and "pll->out", then this function 458 * will search the lookup table to find a valid PLL divider configuration. 459 */ 460 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 461 { 462 u32 i; 463 bool is_found = false; 464 465 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 466 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 467 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 468 is_found = true; 469 pll->cfg.reg.w = def_cfg->cfg.reg.w; 470 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 471 break; 472 } 473 } 474 return is_found; 475 } 476 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 477 struct ast2600_pll_cfg *p_cfg, int pll_idx) 478 { 479 u32 addr, addr_ext; 480 u32 reg; 481 482 switch (pll_idx) { 483 case ASPEED_CLK_HPLL: 484 addr = (u32)(&scu->h_pll_param); 485 addr_ext = (u32)(&scu->h_pll_ext_param); 486 break; 487 case ASPEED_CLK_MPLL: 488 addr = (u32)(&scu->m_pll_param); 489 addr_ext = (u32)(&scu->m_pll_ext_param); 490 break; 491 case ASPEED_CLK_DPLL: 492 addr = (u32)(&scu->d_pll_param); 493 addr_ext = (u32)(&scu->d_pll_ext_param); 494 break; 495 case ASPEED_CLK_EPLL: 496 addr = (u32)(&scu->e_pll_param); 497 addr_ext = (u32)(&scu->e_pll_ext_param); 498 break; 499 default: 500 debug("unknown PLL index\n"); 501 return 1; 502 } 503 504 p_cfg->reg.b.bypass = 0; 505 p_cfg->reg.b.off = 1; 506 p_cfg->reg.b.reset = 1; 507 508 reg = readl(addr); 509 reg &= ~GENMASK(25, 0); 510 reg |= p_cfg->reg.w; 511 writel(reg, addr); 512 513 /* write extend parameter */ 514 writel(p_cfg->ext_reg, addr_ext); 515 udelay(100); 516 p_cfg->reg.b.off = 0; 517 p_cfg->reg.b.reset = 0; 518 reg &= ~GENMASK(25, 0); 519 reg |= p_cfg->reg.w; 520 writel(reg, addr); 521 522 /* polling PLL lock status */ 523 while(0 == (readl(addr_ext) & BIT(31))); 524 525 return 0; 526 } 527 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 528 { 529 struct ast2600_pll_desc mpll; 530 531 mpll.in = AST2600_CLK_IN; 532 mpll.out = rate; 533 if (false == ast2600_search_clock_config(&mpll)) { 534 printf("error!! unable to find valid DDR clock setting\n"); 535 return 0; 536 } 537 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 538 539 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 540 } 541 542 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 543 { 544 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 545 546 ulong new_rate; 547 switch (clk->id) { 548 case ASPEED_CLK_MPLL: 549 new_rate = ast2600_configure_ddr(priv->scu, rate); 550 break; 551 default: 552 return -ENOENT; 553 } 554 555 return new_rate; 556 } 557 558 #define SCU_CLKSTOP_MAC1 (20) 559 #define SCU_CLKSTOP_MAC2 (21) 560 #define SCU_CLKSTOP_MAC3 (20) 561 #define SCU_CLKSTOP_MAC4 (21) 562 563 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 564 { 565 #if 0 566 struct ast2600_pll_desc epll; 567 568 epll.in = AST2600_CLK_IN; 569 epll.out = 1000000000; 570 if (false == ast2600_search_clock_config(&epll)) { 571 printf( 572 "error!! unable to find valid ETHNET MAC clock setting\n"); 573 debug("%s: epll cfg = 0x%08x 0x%08x\n", __func__, 574 epll.cfg.reg.w, epll.cfg.ext_reg); 575 debug("%s: epll cfg = %02x %02x %02x\n", __func__, 576 epll.cfg.reg.b.m, epll.cfg.reg.b.n, epll.cfg.reg.b.p); 577 return 0; 578 } 579 ast2600_configure_pll(scu, &(epll.cfg), ASPEED_CLK_EPLL); 580 581 /* select MAC#1 and MAC#2 clock source = EPLL / 8 */ 582 clksel = readl(&scu->clk_sel2); 583 clksel &= ~BIT(23); 584 clksel |= 0x7 << 20; 585 writel(clksel, &scu->clk_sel2); 586 #endif 587 /* scu340[25:0]: 1G default delay */ 588 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 589 MAC_DEF_DELAY_1G); 590 591 /* set 100M/10M default delay */ 592 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 593 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 594 595 /* MAC AHB = HPLL / 6 */ 596 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 597 598 return 0; 599 } 600 601 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 602 { 603 604 /* 605 * scu350[31] RGMII 125M source: 0 = from IO pin 606 * scu350[25:0] MAC 1G delay 607 */ 608 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 609 MAC34_DEF_DELAY_1G); 610 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 611 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 612 613 /* 614 * clock source seletion and divider 615 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 616 * scu310[18:16] : RMII 50M = HCLK_200M / 4 617 */ 618 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 619 ((0x0 << 24) | (0x3 << 16))); 620 621 /* 622 * set driving strength 623 * scu458[3:2] : MAC4 driving strength 624 * scu458[1:0] : MAC3 driving strength 625 */ 626 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 627 (0x2 << 2) | (0x2 << 0)); 628 629 return 0; 630 } 631 632 /** 633 * ast2600 RGMII clock source tree 634 * 635 * 125M from external PAD -------->|\ 636 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 637 * | |---->| divider |---->|/ + 638 * EPLL -->|/ | 639 * | 640 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 641 * | 642 * +--------------------------->|\ 643 * | |----> RGMII 125M for MAC#3 & MAC#4 644 * HCLK 200M ---->|divider|---->|/ 645 * 646 * To simplify the control flow: 647 * 1. RGMII 1/2 always use EPLL as the internal clock source 648 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 649 * 650 * 125M from external PAD -------->|\ 651 * | |---->RGMII 125M for MAC#1 & MAC#2 652 * EPLL---->| divider |--->|/ + 653 * | 654 * +<--------------------|RGMIICK PAD output enable|<-------------+ 655 * | 656 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 657 */ 658 #define RGMIICK_SRC_PAD 0 659 #define RGMIICK_SRC_EPLL 1 /* recommended */ 660 #define RGMIICK_SRC_HPLL 2 661 662 #define RGMIICK_DIV2 1 663 #define RGMIICK_DIV3 2 664 #define RGMIICK_DIV4 3 665 #define RGMIICK_DIV5 4 666 #define RGMIICK_DIV6 5 667 #define RGMIICK_DIV7 6 668 #define RGMIICK_DIV8 7 /* recommended */ 669 670 #define RMIICK_DIV4 0 671 #define RMIICK_DIV8 1 672 #define RMIICK_DIV12 2 673 #define RMIICK_DIV16 3 674 #define RMIICK_DIV20 4 /* recommended */ 675 #define RMIICK_DIV24 5 676 #define RMIICK_DIV28 6 677 #define RMIICK_DIV32 7 678 679 struct ast2600_mac_clk_div { 680 u32 src; /* 0=external PAD, 1=internal PLL */ 681 u32 fin; /* divider input speed */ 682 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 683 u32 fout; /* fout = fin / n */ 684 }; 685 686 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 687 .src = ASPEED_CLK_EPLL, 688 .fin = 1000000000, 689 .n = RGMIICK_DIV8, 690 .fout = 125000000, 691 }; 692 693 struct ast2600_mac_clk_div rmii_clk_defconfig = { 694 .src = ASPEED_CLK_EPLL, 695 .fin = 1000000000, 696 .n = RMIICK_DIV20, 697 .fout = 50000000, 698 }; 699 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 700 struct ast2600_mac_clk_div *p_cfg) 701 { 702 struct ast2600_pll_desc pll; 703 704 pll.in = AST2600_CLK_IN; 705 pll.out = p_cfg->fin; 706 if (false == ast2600_search_clock_config(&pll)) { 707 printf("error!! unable to find valid ETHNET MAC clock " 708 "setting\n"); 709 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 710 pll.cfg.ext_reg); 711 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 712 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 713 return; 714 } 715 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 716 } 717 718 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 719 struct ast2600_mac_clk_div *p_cfg) 720 { 721 u32 reg_304 = readl(&p_scu->clk_sel2); 722 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 723 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 724 725 reg_340 &= ~GENMASK(31, 29); 726 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 727 reg_340 |= BIT(28); 728 if ((p_cfg->src == ASPEED_CLK_EPLL) || 729 (p_cfg->src == ASPEED_CLK_HPLL)) { 730 /* 731 * re-init PLL if the current PLL output frequency doesn't match 732 * the divider setting 733 */ 734 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 735 ast2600_init_mac_pll(p_scu, p_cfg); 736 } 737 /* scu340[31]: select RGMII 125M from internal source */ 738 reg_340 |= BIT(31); 739 } 740 741 reg_304 &= ~GENMASK(23, 20); 742 743 /* set clock divider */ 744 reg_304 |= (p_cfg->n & 0x7) << 20; 745 746 /* select internal clock source */ 747 if (ASPEED_CLK_HPLL == p_cfg->src) { 748 reg_304 |= BIT(23); 749 } 750 751 /* RGMII 3/4 clock source select */ 752 reg_350 &= ~BIT(31); 753 #if 0 754 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 755 reg_350 |= BIT(31); 756 } 757 758 /* set clock divider */ 759 reg_310 &= ~GENMASK(22, 20); 760 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 761 #endif 762 763 writel(reg_304, &p_scu->clk_sel2); 764 writel(reg_340, &p_scu->mac12_clk_delay); 765 writel(reg_350, &p_scu->mac34_clk_delay); 766 } 767 768 /** 769 * ast2600 RMII/NCSI clock source tree 770 * 771 * HPLL -->|\ 772 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 773 * EPLL -->|/ 774 * 775 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 776 */ 777 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 778 struct ast2600_mac_clk_div *p_cfg) 779 { 780 u32 reg_304; 781 u32 reg_310; 782 783 if ((p_cfg->src == ASPEED_CLK_EPLL) || 784 (p_cfg->src == ASPEED_CLK_HPLL)) { 785 /* 786 * re-init PLL if the current PLL output frequency doesn't match 787 * the divider setting 788 */ 789 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 790 ast2600_init_mac_pll(p_scu, p_cfg); 791 } 792 } 793 794 reg_304 = readl(&p_scu->clk_sel2); 795 reg_310 = readl(&p_scu->clk_sel4); 796 797 reg_304 &= ~GENMASK(19, 16); 798 799 /* set RMII 1/2 clock divider */ 800 reg_304 |= (p_cfg->n & 0x7) << 16; 801 802 /* RMII clock source selection */ 803 if (ASPEED_CLK_HPLL == p_cfg->src) { 804 reg_304 |= BIT(19); 805 } 806 807 /* set RMII 3/4 clock divider */ 808 reg_310 &= ~GENMASK(18, 16); 809 reg_310 |= (0x3 << 16); 810 811 writel(reg_304, &p_scu->clk_sel2); 812 writel(reg_310, &p_scu->clk_sel4); 813 } 814 815 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 816 { 817 u32 reset_bit; 818 u32 clkstop_bit; 819 820 switch (index) { 821 case 1: 822 reset_bit = BIT(ASPEED_RESET_MAC1); 823 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 824 writel(reset_bit, &scu->sysreset_ctrl1); 825 udelay(100); 826 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 827 mdelay(10); 828 writel(reset_bit, &scu->sysreset_clr_ctrl1); 829 830 break; 831 case 2: 832 reset_bit = BIT(ASPEED_RESET_MAC2); 833 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 834 writel(reset_bit, &scu->sysreset_ctrl1); 835 udelay(100); 836 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 837 mdelay(10); 838 writel(reset_bit, &scu->sysreset_clr_ctrl1); 839 break; 840 case 3: 841 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 842 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 843 writel(reset_bit, &scu->sysreset_ctrl2); 844 udelay(100); 845 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 846 mdelay(10); 847 writel(reset_bit, &scu->sysreset_clr_ctrl2); 848 break; 849 case 4: 850 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 851 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 852 writel(reset_bit, &scu->sysreset_ctrl2); 853 udelay(100); 854 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 855 mdelay(10); 856 writel(reset_bit, &scu->sysreset_clr_ctrl2); 857 break; 858 default: 859 return -EINVAL; 860 } 861 862 return 0; 863 } 864 865 #define SCU_CLKSTOP_SDIO 4 866 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 867 { 868 u32 reset_bit; 869 u32 clkstop_bit; 870 871 reset_bit = BIT(ASPEED_RESET_SD - 32); 872 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 873 874 writel(reset_bit, &scu->sysreset_ctrl2); 875 876 udelay(100); 877 //enable clk 878 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 879 mdelay(10); 880 writel(reset_bit, &scu->sysreset_clr_ctrl2); 881 882 return 0; 883 } 884 885 #define SCU_CLKSTOP_EXTSD 31 886 #define SCU_CLK_SD_MASK (0x7 << 28) 887 #define SCU_CLK_SD_DIV(x) (x << 28) 888 889 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 890 { 891 u32 clk_sel = readl(&scu->clk_sel4); 892 u32 enableclk_bit; 893 894 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 895 896 //default use apll for clock source 800/4 = 200 : controller max is 200mhz 897 clk_sel &= ~SCU_CLK_SD_MASK; 898 clk_sel |= SCU_CLK_SD_DIV(1) | BIT(8); 899 writel(clk_sel, &scu->clk_sel4); 900 901 //enable clk 902 setbits_le32(&scu->clk_sel4, enableclk_bit); 903 904 return 0; 905 } 906 907 #define SCU_CLKSTOP_EMMC 27 908 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 909 { 910 u32 reset_bit; 911 u32 clkstop_bit; 912 913 reset_bit = BIT(ASPEED_RESET_EMMC); 914 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 915 916 writel(reset_bit, &scu->sysreset_ctrl1); 917 udelay(100); 918 //enable clk 919 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 920 mdelay(10); 921 writel(reset_bit, &scu->sysreset_clr_ctrl1); 922 923 return 0; 924 } 925 926 #define SCU_CLKSTOP_EXTEMMC 15 927 #define SCU_CLK_EMMC_MASK (0x7 << 12) 928 #define SCU_CLK_EMMC_DIV(x) (x << 12) 929 930 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 931 { 932 u32 clk_sel = readl(&scu->clk_sel1); 933 u32 enableclk_bit; 934 u32 rate = 0; 935 u32 div = 0; 936 int i = 0; 937 938 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 939 940 //ast2600 eMMC controller max clk is 200Mhz 941 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 942 943 for(i = 0; i < 8; i++) { 944 div = (i + 1) * 4; 945 if ((rate / div) <= 200000000) 946 break; 947 } 948 949 clk_sel &= ~SCU_CLK_EMMC_MASK; 950 clk_sel |= SCU_CLK_EMMC_DIV(i); 951 writel(clk_sel, &scu->clk_sel1); 952 953 //enable clk 954 setbits_le32(&scu->clk_sel1, enableclk_bit); 955 956 return 0; 957 } 958 959 #define SCU_CLKSTOP_FSICLK 30 960 961 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 962 { 963 u32 reset_bit; 964 u32 clkstop_bit; 965 966 reset_bit = BIT(ASPEED_RESET_FSI % 32); 967 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 968 969 /* The FSI clock is shared between masters. If it's already on 970 * don't touch it, as that will reset the existing master. */ 971 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 972 debug("%s: already running, not touching it\n", __func__); 973 return 0; 974 } 975 976 writel(reset_bit, &scu->sysreset_ctrl2); 977 udelay(100); 978 //enable clk 979 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 980 mdelay(10); 981 writel(reset_bit, &scu->sysreset_clr_ctrl2); 982 983 return 0; 984 } 985 986 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 987 { 988 u32 reset_bit; 989 u32 clkstop_bit; 990 991 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 992 clkstop_bit = BIT(14); 993 994 writel(reset_bit, &scu->sysreset_ctrl1); 995 udelay(100); 996 //enable phy clk 997 writel(clkstop_bit, &scu->clk_stop_ctrl1); 998 mdelay(20); 999 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1000 1001 return 0; 1002 } 1003 1004 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1005 { 1006 u32 reset_bit; 1007 u32 clkstop_bit; 1008 1009 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1010 clkstop_bit = BIT(7); 1011 1012 writel(reset_bit, &scu->sysreset_ctrl1); 1013 udelay(100); 1014 //enable phy clk 1015 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1016 mdelay(20); 1017 1018 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1019 1020 return 0; 1021 } 1022 1023 static int ast2600_clk_enable(struct clk *clk) 1024 { 1025 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1026 1027 switch (clk->id) { 1028 case ASPEED_CLK_GATE_MAC1CLK: 1029 ast2600_configure_mac(priv->scu, 1); 1030 break; 1031 case ASPEED_CLK_GATE_MAC2CLK: 1032 ast2600_configure_mac(priv->scu, 2); 1033 break; 1034 case ASPEED_CLK_GATE_MAC3CLK: 1035 ast2600_configure_mac(priv->scu, 3); 1036 break; 1037 case ASPEED_CLK_GATE_MAC4CLK: 1038 ast2600_configure_mac(priv->scu, 4); 1039 break; 1040 case ASPEED_CLK_GATE_SDCLK: 1041 ast2600_enable_sdclk(priv->scu); 1042 break; 1043 case ASPEED_CLK_GATE_SDEXTCLK: 1044 ast2600_enable_extsdclk(priv->scu); 1045 break; 1046 case ASPEED_CLK_GATE_EMMCCLK: 1047 ast2600_enable_emmcclk(priv->scu); 1048 break; 1049 case ASPEED_CLK_GATE_EMMCEXTCLK: 1050 ast2600_enable_extemmcclk(priv->scu); 1051 break; 1052 case ASPEED_CLK_GATE_FSICLK: 1053 ast2600_enable_fsiclk(priv->scu); 1054 break; 1055 case ASPEED_CLK_GATE_USBPORT1CLK: 1056 ast2600_enable_usbahclk(priv->scu); 1057 break; 1058 case ASPEED_CLK_GATE_USBPORT2CLK: 1059 ast2600_enable_usbbhclk(priv->scu); 1060 break; 1061 default: 1062 pr_debug("can't enable clk \n"); 1063 return -ENOENT; 1064 break; 1065 } 1066 1067 return 0; 1068 } 1069 1070 struct clk_ops ast2600_clk_ops = { 1071 .get_rate = ast2600_clk_get_rate, 1072 .set_rate = ast2600_clk_set_rate, 1073 .enable = ast2600_clk_enable, 1074 }; 1075 1076 static int ast2600_clk_probe(struct udevice *dev) 1077 { 1078 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1079 u32 uart_clk_source; 1080 1081 priv->scu = devfdt_get_addr_ptr(dev); 1082 if (IS_ERR(priv->scu)) 1083 return PTR_ERR(priv->scu); 1084 1085 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 1086 0x0); 1087 1088 if(uart_clk_source) { 1089 if(uart_clk_source & GENMASK(5, 0)) 1090 setbits_le32(&priv->scu->clk_sel4, uart_clk_source & GENMASK(5, 0)); 1091 if(uart_clk_source & GENMASK(12, 6)) 1092 setbits_le32(&priv->scu->clk_sel5, uart_clk_source & GENMASK(12, 6)); 1093 } 1094 1095 1096 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1097 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1098 ast2600_configure_mac12_clk(priv->scu); 1099 ast2600_configure_mac34_clk(priv->scu); 1100 1101 return 0; 1102 } 1103 1104 static int ast2600_clk_bind(struct udevice *dev) 1105 { 1106 int ret; 1107 1108 /* The reset driver does not have a device node, so bind it here */ 1109 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1110 if (ret) 1111 debug("Warning: No reset driver: ret=%d\n", ret); 1112 1113 return 0; 1114 } 1115 1116 #if CONFIG_IS_ENABLED(CMD_CLK) 1117 struct aspeed_clks { 1118 ulong id; 1119 const char *name; 1120 }; 1121 1122 static struct aspeed_clks aspeed_clk_names[] = { 1123 { ASPEED_CLK_HPLL, "hpll" }, 1124 { ASPEED_CLK_MPLL, "mpll" }, 1125 { ASPEED_CLK_APLL, "apll" }, 1126 { ASPEED_CLK_EPLL, "epll" }, 1127 { ASPEED_CLK_DPLL, "dpll" }, 1128 { ASPEED_CLK_AHB, "hclk" }, 1129 { ASPEED_CLK_APB1, "pclk1" }, 1130 { ASPEED_CLK_APB2, "pclk2" }, 1131 { ASPEED_CLK_UARTX, "uxclk" }, 1132 { ASPEED_CLK_HUARTX, "huxclk" }, 1133 }; 1134 1135 int soc_clk_dump(void) 1136 { 1137 struct udevice *dev; 1138 struct clk clk; 1139 unsigned long rate; 1140 int i, ret; 1141 1142 ret = uclass_get_device_by_driver(UCLASS_CLK, 1143 DM_GET_DRIVER(aspeed_scu), &dev); 1144 if (ret) 1145 return ret; 1146 1147 printf("Clk\t\tHz\n"); 1148 1149 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1150 clk.id = aspeed_clk_names[i].id; 1151 ret = clk_request(dev, &clk); 1152 if (ret < 0) { 1153 debug("%s clk_request() failed: %d\n", __func__, ret); 1154 continue; 1155 } 1156 1157 ret = clk_get_rate(&clk); 1158 rate = ret; 1159 1160 clk_free(&clk); 1161 1162 if (ret == -ENOTSUPP) { 1163 printf("clk ID %lu not supported yet\n", 1164 aspeed_clk_names[i].id); 1165 continue; 1166 } 1167 if (ret < 0) { 1168 printf("%s %lu: get_rate err: %d\n", 1169 __func__, aspeed_clk_names[i].id, ret); 1170 continue; 1171 } 1172 1173 printf("%s(%3lu):\t%lu\n", 1174 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1175 } 1176 1177 return 0; 1178 } 1179 #endif 1180 1181 static const struct udevice_id ast2600_clk_ids[] = { 1182 { .compatible = "aspeed,ast2600-scu", }, 1183 { } 1184 }; 1185 1186 U_BOOT_DRIVER(aspeed_scu) = { 1187 .name = "aspeed_scu", 1188 .id = UCLASS_CLK, 1189 .of_match = ast2600_clk_ids, 1190 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1191 .ops = &ast2600_clk_ops, 1192 .bind = ast2600_clk_bind, 1193 .probe = ast2600_clk_probe, 1194 }; 1195