1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 {.in = AST2600_CLK_IN, .out = 400000000, 77 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 78 .cfg.ext_reg = 0x31, 79 }, 80 {.in = AST2600_CLK_IN, .out = 200000000, 81 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 82 .cfg.ext_reg = 0x3f 83 }, 84 {.in = AST2600_CLK_IN, .out = 334000000, 85 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 86 .cfg.ext_reg = 0x14d 87 }, 88 89 {.in = AST2600_CLK_IN, .out = 1000000000, 90 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 91 .cfg.ext_reg = 0x3d 92 }, 93 94 {.in = AST2600_CLK_IN, .out = 50000000, 95 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 96 .cfg.ext_reg = 0x31 97 }, 98 }; 99 100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 101 { 102 u32 clkin = AST2600_CLK_IN; 103 u32 pll_reg = 0; 104 unsigned int mult, div = 1; 105 106 switch(pll_idx) { 107 case ASPEED_CLK_HPLL: 108 pll_reg = readl(&scu->h_pll_param); 109 break; 110 case ASPEED_CLK_MPLL: 111 pll_reg = readl(&scu->m_pll_param); 112 break; 113 case ASPEED_CLK_DPLL: 114 pll_reg = readl(&scu->d_pll_param); 115 break; 116 case ASPEED_CLK_EPLL: 117 pll_reg = readl(&scu->e_pll_param); 118 break; 119 120 } 121 if (pll_reg & BIT(24)) { 122 /* Pass through mode */ 123 mult = div = 1; 124 } else { 125 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 126 union ast2600_pll_reg reg; 127 reg.w = pll_reg; 128 mult = (reg.b.m + 1) / (reg.b.n + 1); 129 div = (reg.b.p + 1); 130 } 131 return ((clkin * mult)/div); 132 133 } 134 135 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 136 { 137 u32 clkin = AST2600_CLK_IN; 138 u32 apll_reg = readl(&scu->a_pll_param); 139 unsigned int mult, div = 1; 140 141 if (apll_reg & BIT(20)) { 142 /* Pass through mode */ 143 mult = div = 1; 144 } else { 145 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 146 u32 m = (apll_reg >> 5) & 0x3f; 147 u32 od = (apll_reg >> 4) & 0x1; 148 u32 n = apll_reg & 0xf; 149 150 mult = (2 - od) * (m + 2); 151 div = n + 1; 152 } 153 return ((clkin * mult)/div); 154 } 155 156 static u32 ast2600_a0_axi_ahb_div_table[] = { 157 2, 2, 3, 4, 158 }; 159 160 static u32 ast2600_a1_axi_ahb_div0_table[] = { 161 3, 2, 3, 4, 162 }; 163 164 static u32 ast2600_a1_axi_ahb_div1_table[] = { 165 3, 4, 6, 8, 166 }; 167 168 static u32 ast2600_a1_axi_ahb_default_table[] = { 169 3, 4, 3, 4, 2, 2, 2, 2, 170 }; 171 172 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 173 { 174 u32 hw_rev = readl(&scu->chip_id0); 175 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 176 u32 axi_div = 1; 177 u32 ahb_div = 0; 178 u32 rate = 0; 179 180 if (hw_rev & BIT(16)) { 181 if(hwstrap1 & BIT(16)) { 182 ast2600_a1_axi_ahb_div1_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 183 axi_div = 1; 184 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 185 } else { 186 ast2600_a1_axi_ahb_div0_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 187 axi_div = 2; 188 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 189 } 190 } else { 191 //a0 : fix axi = hpll / 2 192 axi_div = 2; 193 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 194 } 195 196 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 197 return (rate / axi_div / ahb_div); 198 } 199 200 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 201 { 202 u32 rate; 203 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 204 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 205 206 return (rate /((bclk_sel + 1) * 4)); 207 } 208 209 static u32 ast2600_hpll_pclk1_div_table[] = { 210 4, 8, 12, 16, 20, 24, 28, 32, 211 }; 212 213 static u32 ast2600_hpll_pclk2_div_table[] = { 214 2, 4, 6, 8, 10, 12, 14, 16, 215 }; 216 217 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 218 { 219 u32 clk_sel1 = readl(&scu->clk_sel1); 220 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 221 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 222 223 return (rate / apb_div); 224 } 225 226 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 227 { 228 u32 clk_sel4 = readl(&scu->clk_sel4); 229 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 230 u32 rate = ast2600_get_hclk(scu); 231 232 return (rate / apb_div); 233 } 234 235 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 236 { 237 u32 clk_in = 0; 238 u32 uxclk_sel = readl(&scu->clk_sel5); 239 240 uxclk_sel &= 0x3; 241 switch(uxclk_sel) { 242 case 0: 243 clk_in = ast2600_get_apll_rate(scu) / 4; 244 break; 245 case 1: 246 clk_in = ast2600_get_apll_rate(scu) / 2; 247 break; 248 case 2: 249 clk_in = ast2600_get_apll_rate(scu); 250 break; 251 case 3: 252 clk_in = ast2600_get_hclk(scu); 253 break; 254 } 255 256 return clk_in; 257 } 258 259 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 260 { 261 u32 clk_in = 0; 262 u32 huclk_sel = readl(&scu->clk_sel5); 263 264 huclk_sel = ((huclk_sel >> 3) & 0x3); 265 switch(huclk_sel) { 266 case 0: 267 clk_in = ast2600_get_apll_rate(scu) / 4; 268 break; 269 case 1: 270 clk_in = ast2600_get_apll_rate(scu) / 2; 271 break; 272 case 2: 273 clk_in = ast2600_get_apll_rate(scu); 274 break; 275 case 3: 276 clk_in = ast2600_get_hclk(scu); 277 break; 278 } 279 280 return clk_in; 281 } 282 283 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 284 { 285 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 286 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 287 unsigned int mult, div; 288 289 u32 n = (div_reg >> 8) & 0x3ff; 290 u32 r = div_reg & 0xff; 291 292 mult = r; 293 div = (n * 2); 294 return (clk_in * mult)/div; 295 } 296 297 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 298 { 299 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 300 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 301 302 unsigned int mult, div; 303 304 u32 n = (div_reg >> 8) & 0x3ff; 305 u32 r = div_reg & 0xff; 306 307 mult = r; 308 div = (n * 2); 309 return (clk_in * mult)/div; 310 } 311 312 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 313 { 314 u32 clkin = 0; 315 u32 clk_sel = readl(&scu->clk_sel4); 316 u32 div = (clk_sel >> 28) & 0x7; 317 318 if(clk_sel & BIT(8)) { 319 clkin = ast2600_get_apll_rate(scu); 320 } else { 321 clkin = ast2600_get_hclk(scu); 322 } 323 div = (div + 1) << 1; 324 325 return (clkin / div); 326 } 327 328 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 329 { 330 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 331 u32 clk_sel = readl(&scu->clk_sel1); 332 u32 div = (clk_sel >> 12) & 0x7; 333 334 div = (div + 1) << 2; 335 336 return (clkin / div); 337 } 338 339 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 340 { 341 u32 uart_sel = readl(&scu->clk_sel4); 342 u32 uart_sel5 = readl(&scu->clk_sel5); 343 ulong uart_clk = 0; 344 345 switch(uart_idx) { 346 case 1: 347 case 2: 348 case 3: 349 case 4: 350 case 6: 351 if(uart_sel & BIT(uart_idx - 1)) 352 uart_clk = ast2600_get_uart_huxclk_rate(scu) ; 353 else 354 uart_clk = ast2600_get_uart_uxclk_rate(scu) ; 355 break; 356 case 5: //24mhz is come form usb phy 48Mhz 357 { 358 u8 uart5_clk_sel = 0; 359 //high bit 360 if (readl(&scu->misc_ctrl1) & BIT(12)) 361 uart5_clk_sel = 0x2; 362 else 363 uart5_clk_sel = 0x0; 364 365 if (readl(&scu->clk_sel2) & BIT(14)) 366 uart5_clk_sel |= 0x1; 367 368 switch(uart5_clk_sel) { 369 case 0: 370 uart_clk = 24000000; 371 break; 372 case 1: 373 uart_clk = 192000000; 374 break; 375 case 2: 376 uart_clk = 24000000/13; 377 break; 378 case 3: 379 uart_clk = 192000000/13; 380 break; 381 } 382 } 383 break; 384 case 7: 385 case 8: 386 case 9: 387 case 10: 388 case 11: 389 case 12: 390 case 13: 391 if(uart_sel5 & BIT(uart_idx - 1)) 392 uart_clk = ast2600_get_uart_huxclk_rate(scu); 393 else 394 uart_clk = ast2600_get_uart_uxclk_rate(scu); 395 break; 396 } 397 398 return uart_clk; 399 } 400 401 static ulong ast2600_clk_get_rate(struct clk *clk) 402 { 403 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 404 ulong rate = 0; 405 406 switch (clk->id) { 407 case ASPEED_CLK_HPLL: 408 case ASPEED_CLK_EPLL: 409 case ASPEED_CLK_DPLL: 410 case ASPEED_CLK_MPLL: 411 rate = ast2600_get_pll_rate(priv->scu, clk->id); 412 break; 413 case ASPEED_CLK_AHB: 414 rate = ast2600_get_hclk(priv->scu); 415 break; 416 case ASPEED_CLK_APB1: 417 rate = ast2600_get_pclk1(priv->scu); 418 break; 419 case ASPEED_CLK_APB2: 420 rate = ast2600_get_pclk2(priv->scu); 421 break; 422 case ASPEED_CLK_APLL: 423 rate = ast2600_get_apll_rate(priv->scu); 424 break; 425 case ASPEED_CLK_GATE_UART1CLK: 426 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 427 break; 428 case ASPEED_CLK_GATE_UART2CLK: 429 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 430 break; 431 case ASPEED_CLK_GATE_UART3CLK: 432 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 433 break; 434 case ASPEED_CLK_GATE_UART4CLK: 435 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 436 break; 437 case ASPEED_CLK_GATE_UART5CLK: 438 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 439 break; 440 case ASPEED_CLK_BCLK: 441 rate = ast2600_get_bclk_rate(priv->scu); 442 break; 443 case ASPEED_CLK_SDIO: 444 rate = ast2600_get_sdio_clk_rate(priv->scu); 445 break; 446 case ASPEED_CLK_EMMC: 447 rate = ast2600_get_emmc_clk_rate(priv->scu); 448 break; 449 case ASPEED_CLK_UARTX: 450 rate = ast2600_get_uart_uxclk_rate(priv->scu); 451 break; 452 case ASPEED_CLK_HUARTX: 453 rate = ast2600_get_uart_huxclk_rate(priv->scu); 454 break; 455 default: 456 pr_debug("can't get clk rate \n"); 457 return -ENOENT; 458 break; 459 } 460 461 return rate; 462 } 463 464 /** 465 * @brief lookup PLL divider config by input/output rate 466 * @param[in] *pll - PLL descriptor 467 * @return true - if PLL divider config is found, false - else 468 * 469 * The function caller shall fill "pll->in" and "pll->out", then this function 470 * will search the lookup table to find a valid PLL divider configuration. 471 */ 472 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 473 { 474 u32 i; 475 bool is_found = false; 476 477 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 478 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 479 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 480 is_found = true; 481 pll->cfg.reg.w = def_cfg->cfg.reg.w; 482 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 483 break; 484 } 485 } 486 return is_found; 487 } 488 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 489 struct ast2600_pll_cfg *p_cfg, int pll_idx) 490 { 491 u32 addr, addr_ext; 492 u32 reg; 493 494 switch (pll_idx) { 495 case ASPEED_CLK_HPLL: 496 addr = (u32)(&scu->h_pll_param); 497 addr_ext = (u32)(&scu->h_pll_ext_param); 498 break; 499 case ASPEED_CLK_MPLL: 500 addr = (u32)(&scu->m_pll_param); 501 addr_ext = (u32)(&scu->m_pll_ext_param); 502 break; 503 case ASPEED_CLK_DPLL: 504 addr = (u32)(&scu->d_pll_param); 505 addr_ext = (u32)(&scu->d_pll_ext_param); 506 break; 507 case ASPEED_CLK_EPLL: 508 addr = (u32)(&scu->e_pll_param); 509 addr_ext = (u32)(&scu->e_pll_ext_param); 510 break; 511 default: 512 debug("unknown PLL index\n"); 513 return 1; 514 } 515 516 p_cfg->reg.b.bypass = 0; 517 p_cfg->reg.b.off = 1; 518 p_cfg->reg.b.reset = 1; 519 520 reg = readl(addr); 521 reg &= ~GENMASK(25, 0); 522 reg |= p_cfg->reg.w; 523 writel(reg, addr); 524 525 /* write extend parameter */ 526 writel(p_cfg->ext_reg, addr_ext); 527 udelay(100); 528 p_cfg->reg.b.off = 0; 529 p_cfg->reg.b.reset = 0; 530 reg &= ~GENMASK(25, 0); 531 reg |= p_cfg->reg.w; 532 writel(reg, addr); 533 534 /* polling PLL lock status */ 535 while(0 == (readl(addr_ext) & BIT(31))); 536 537 return 0; 538 } 539 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 540 { 541 struct ast2600_pll_desc mpll; 542 543 mpll.in = AST2600_CLK_IN; 544 mpll.out = rate; 545 if (false == ast2600_search_clock_config(&mpll)) { 546 printf("error!! unable to find valid DDR clock setting\n"); 547 return 0; 548 } 549 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 550 551 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 552 } 553 554 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 555 { 556 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 557 558 ulong new_rate; 559 switch (clk->id) { 560 case ASPEED_CLK_MPLL: 561 new_rate = ast2600_configure_ddr(priv->scu, rate); 562 break; 563 default: 564 return -ENOENT; 565 } 566 567 return new_rate; 568 } 569 570 #define SCU_CLKSTOP_MAC1 (20) 571 #define SCU_CLKSTOP_MAC2 (21) 572 #define SCU_CLKSTOP_MAC3 (20) 573 #define SCU_CLKSTOP_MAC4 (21) 574 575 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 576 { 577 /* scu340[25:0]: 1G default delay */ 578 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 579 MAC_DEF_DELAY_1G); 580 581 /* set 100M/10M default delay */ 582 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 583 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 584 585 /* MAC AHB = HPLL / 6 */ 586 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 587 588 return 0; 589 } 590 591 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 592 { 593 594 /* 595 * scu350[31] RGMII 125M source: 0 = from IO pin 596 * scu350[25:0] MAC 1G delay 597 */ 598 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 599 MAC34_DEF_DELAY_1G); 600 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 601 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 602 603 /* 604 * clock source seletion and divider 605 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 606 * scu310[18:16] : RMII 50M = HCLK_200M / 4 607 */ 608 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 609 ((0x0 << 24) | (0x3 << 16))); 610 611 /* 612 * set driving strength 613 * scu458[3:2] : MAC4 driving strength 614 * scu458[1:0] : MAC3 driving strength 615 */ 616 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 617 (0x3 << 2) | (0x3 << 0)); 618 619 return 0; 620 } 621 622 /** 623 * ast2600 RGMII clock source tree 624 * 625 * 125M from external PAD -------->|\ 626 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 627 * | |---->| divider |---->|/ + 628 * EPLL -->|/ | 629 * | 630 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 631 * | 632 * +--------------------------->|\ 633 * | |----> RGMII 125M for MAC#3 & MAC#4 634 * HCLK 200M ---->|divider|---->|/ 635 * 636 * To simplify the control flow: 637 * 1. RGMII 1/2 always use EPLL as the internal clock source 638 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 639 * 640 * 125M from external PAD -------->|\ 641 * | |---->RGMII 125M for MAC#1 & MAC#2 642 * EPLL---->| divider |--->|/ + 643 * | 644 * +<--------------------|RGMIICK PAD output enable|<-------------+ 645 * | 646 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 647 */ 648 #define RGMIICK_SRC_PAD 0 649 #define RGMIICK_SRC_EPLL 1 /* recommended */ 650 #define RGMIICK_SRC_HPLL 2 651 652 #define RGMIICK_DIV2 1 653 #define RGMIICK_DIV3 2 654 #define RGMIICK_DIV4 3 655 #define RGMIICK_DIV5 4 656 #define RGMIICK_DIV6 5 657 #define RGMIICK_DIV7 6 658 #define RGMIICK_DIV8 7 /* recommended */ 659 660 #define RMIICK_DIV4 0 661 #define RMIICK_DIV8 1 662 #define RMIICK_DIV12 2 663 #define RMIICK_DIV16 3 664 #define RMIICK_DIV20 4 /* recommended */ 665 #define RMIICK_DIV24 5 666 #define RMIICK_DIV28 6 667 #define RMIICK_DIV32 7 668 669 struct ast2600_mac_clk_div { 670 u32 src; /* 0=external PAD, 1=internal PLL */ 671 u32 fin; /* divider input speed */ 672 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 673 u32 fout; /* fout = fin / n */ 674 }; 675 676 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 677 .src = ASPEED_CLK_EPLL, 678 .fin = 1000000000, 679 .n = RGMIICK_DIV8, 680 .fout = 125000000, 681 }; 682 683 struct ast2600_mac_clk_div rmii_clk_defconfig = { 684 .src = ASPEED_CLK_EPLL, 685 .fin = 1000000000, 686 .n = RMIICK_DIV20, 687 .fout = 50000000, 688 }; 689 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 690 struct ast2600_mac_clk_div *p_cfg) 691 { 692 struct ast2600_pll_desc pll; 693 694 pll.in = AST2600_CLK_IN; 695 pll.out = p_cfg->fin; 696 if (false == ast2600_search_clock_config(&pll)) { 697 printf("error!! unable to find valid ETHNET MAC clock " 698 "setting\n"); 699 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 700 pll.cfg.ext_reg); 701 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 702 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 703 return; 704 } 705 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 706 } 707 708 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 709 struct ast2600_mac_clk_div *p_cfg) 710 { 711 u32 reg_304 = readl(&p_scu->clk_sel2); 712 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 713 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 714 715 reg_340 &= ~GENMASK(31, 29); 716 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 717 reg_340 |= BIT(28); 718 if ((p_cfg->src == ASPEED_CLK_EPLL) || 719 (p_cfg->src == ASPEED_CLK_HPLL)) { 720 /* 721 * re-init PLL if the current PLL output frequency doesn't match 722 * the divider setting 723 */ 724 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 725 ast2600_init_mac_pll(p_scu, p_cfg); 726 } 727 /* scu340[31]: select RGMII 125M from internal source */ 728 reg_340 |= BIT(31); 729 } 730 731 reg_304 &= ~GENMASK(23, 20); 732 733 /* set clock divider */ 734 reg_304 |= (p_cfg->n & 0x7) << 20; 735 736 /* select internal clock source */ 737 if (ASPEED_CLK_HPLL == p_cfg->src) { 738 reg_304 |= BIT(23); 739 } 740 741 /* RGMII 3/4 clock source select */ 742 reg_350 &= ~BIT(31); 743 #if 0 744 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 745 reg_350 |= BIT(31); 746 } 747 748 /* set clock divider */ 749 reg_310 &= ~GENMASK(22, 20); 750 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 751 #endif 752 753 writel(reg_304, &p_scu->clk_sel2); 754 writel(reg_340, &p_scu->mac12_clk_delay); 755 writel(reg_350, &p_scu->mac34_clk_delay); 756 } 757 758 /** 759 * ast2600 RMII/NCSI clock source tree 760 * 761 * HPLL -->|\ 762 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 763 * EPLL -->|/ 764 * 765 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 766 */ 767 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 768 struct ast2600_mac_clk_div *p_cfg) 769 { 770 u32 reg_304; 771 u32 reg_310; 772 773 if ((p_cfg->src == ASPEED_CLK_EPLL) || 774 (p_cfg->src == ASPEED_CLK_HPLL)) { 775 /* 776 * re-init PLL if the current PLL output frequency doesn't match 777 * the divider setting 778 */ 779 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 780 ast2600_init_mac_pll(p_scu, p_cfg); 781 } 782 } 783 784 reg_304 = readl(&p_scu->clk_sel2); 785 reg_310 = readl(&p_scu->clk_sel4); 786 787 reg_304 &= ~GENMASK(19, 16); 788 789 /* set RMII 1/2 clock divider */ 790 reg_304 |= (p_cfg->n & 0x7) << 16; 791 792 /* RMII clock source selection */ 793 if (ASPEED_CLK_HPLL == p_cfg->src) { 794 reg_304 |= BIT(19); 795 } 796 797 /* set RMII 3/4 clock divider */ 798 reg_310 &= ~GENMASK(18, 16); 799 reg_310 |= (0x3 << 16); 800 801 writel(reg_304, &p_scu->clk_sel2); 802 writel(reg_310, &p_scu->clk_sel4); 803 } 804 805 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 806 { 807 u32 reset_bit; 808 u32 clkstop_bit; 809 810 switch (index) { 811 case 1: 812 reset_bit = BIT(ASPEED_RESET_MAC1); 813 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 814 writel(reset_bit, &scu->sysreset_ctrl1); 815 udelay(100); 816 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 817 mdelay(10); 818 writel(reset_bit, &scu->sysreset_clr_ctrl1); 819 820 break; 821 case 2: 822 reset_bit = BIT(ASPEED_RESET_MAC2); 823 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 824 writel(reset_bit, &scu->sysreset_ctrl1); 825 udelay(100); 826 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 827 mdelay(10); 828 writel(reset_bit, &scu->sysreset_clr_ctrl1); 829 break; 830 case 3: 831 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 832 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 833 writel(reset_bit, &scu->sysreset_ctrl2); 834 udelay(100); 835 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 836 mdelay(10); 837 writel(reset_bit, &scu->sysreset_clr_ctrl2); 838 break; 839 case 4: 840 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 841 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 842 writel(reset_bit, &scu->sysreset_ctrl2); 843 udelay(100); 844 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 845 mdelay(10); 846 writel(reset_bit, &scu->sysreset_clr_ctrl2); 847 break; 848 default: 849 return -EINVAL; 850 } 851 852 return 0; 853 } 854 855 #define SCU_CLKSTOP_SDIO 4 856 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 857 { 858 u32 reset_bit; 859 u32 clkstop_bit; 860 861 reset_bit = BIT(ASPEED_RESET_SD - 32); 862 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 863 864 writel(reset_bit, &scu->sysreset_ctrl2); 865 866 udelay(100); 867 //enable clk 868 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 869 mdelay(10); 870 writel(reset_bit, &scu->sysreset_clr_ctrl2); 871 872 return 0; 873 } 874 875 #define SCU_CLKSTOP_EXTSD 31 876 #define SCU_CLK_SD_MASK (0x7 << 28) 877 #define SCU_CLK_SD_DIV(x) (x << 28) 878 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 879 880 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 881 { 882 u32 clk_sel = readl(&scu->clk_sel4); 883 u32 enableclk_bit; 884 u32 rate = 0; 885 u32 div = 0; 886 int i = 0; 887 888 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 889 890 //ast2600 sd controller max clk is 200Mhz : use apll for clock source 800/4 = 200 : controller max is 200mhz 891 rate = ast2600_get_apll_rate(scu); 892 for(i = 0; i < 8; i++) { 893 div = (i + 1) * 2; 894 if ((rate / div) <= 200000000) 895 break; 896 } 897 clk_sel &= ~SCU_CLK_SD_MASK; 898 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 899 writel(clk_sel, &scu->clk_sel4); 900 901 //enable clk 902 setbits_le32(&scu->clk_sel4, enableclk_bit); 903 904 return 0; 905 } 906 907 #define SCU_CLKSTOP_EMMC 27 908 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 909 { 910 u32 reset_bit; 911 u32 clkstop_bit; 912 913 reset_bit = BIT(ASPEED_RESET_EMMC); 914 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 915 916 writel(reset_bit, &scu->sysreset_ctrl1); 917 udelay(100); 918 //enable clk 919 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 920 mdelay(10); 921 writel(reset_bit, &scu->sysreset_clr_ctrl1); 922 923 return 0; 924 } 925 926 #define SCU_CLKSTOP_EXTEMMC 15 927 #define SCU_CLK_EMMC_MASK (0x7 << 12) 928 #define SCU_CLK_EMMC_DIV(x) (x << 12) 929 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) //AST2600A1 930 931 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 932 { 933 u32 revision_id = readl(&scu->chip_id0); 934 u32 clk_sel = readl(&scu->clk_sel1); 935 u32 enableclk_bit; 936 u32 rate = 0; 937 u32 div = 0; 938 int i = 0; 939 940 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 941 942 //ast2600 eMMC controller max clk is 200Mhz 943 if(((revision_id & GENMASK(23, 16)) >> 16)) { 944 //AST2600A1 ~ : use mpll to be clk source 945 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 946 for(i = 0; i < 8; i++) { 947 div = (i + 1) * 2; 948 if ((rate / div) <= 200000000) 949 break; 950 } 951 952 clk_sel &= ~SCU_CLK_EMMC_MASK; 953 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 954 writel(clk_sel, &scu->clk_sel1); 955 956 } else { 957 //AST2600A0 : use hpll to be clk source 958 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 959 960 for(i = 0; i < 8; i++) { 961 div = (i + 1) * 4; 962 if ((rate / div) <= 200000000) 963 break; 964 } 965 966 clk_sel &= ~SCU_CLK_EMMC_MASK; 967 clk_sel |= SCU_CLK_EMMC_DIV(i); 968 writel(clk_sel, &scu->clk_sel1); 969 } 970 971 //enable clk 972 setbits_le32(&scu->clk_sel1, enableclk_bit); 973 974 return 0; 975 } 976 977 #define SCU_CLKSTOP_FSICLK 30 978 979 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 980 { 981 u32 reset_bit; 982 u32 clkstop_bit; 983 984 reset_bit = BIT(ASPEED_RESET_FSI % 32); 985 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 986 987 /* The FSI clock is shared between masters. If it's already on 988 * don't touch it, as that will reset the existing master. */ 989 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 990 debug("%s: already running, not touching it\n", __func__); 991 return 0; 992 } 993 994 writel(reset_bit, &scu->sysreset_ctrl2); 995 udelay(100); 996 //enable clk 997 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 998 mdelay(10); 999 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1000 1001 return 0; 1002 } 1003 1004 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1005 { 1006 u32 reset_bit; 1007 u32 clkstop_bit; 1008 1009 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1010 clkstop_bit = BIT(14); 1011 1012 writel(reset_bit, &scu->sysreset_ctrl1); 1013 udelay(100); 1014 //enable phy clk 1015 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1016 mdelay(20); 1017 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1018 1019 return 0; 1020 } 1021 1022 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1023 { 1024 u32 reset_bit; 1025 u32 clkstop_bit; 1026 1027 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1028 clkstop_bit = BIT(7); 1029 1030 writel(reset_bit, &scu->sysreset_ctrl1); 1031 udelay(100); 1032 //enable phy clk 1033 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1034 mdelay(20); 1035 1036 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1037 1038 return 0; 1039 } 1040 1041 static int ast2600_clk_enable(struct clk *clk) 1042 { 1043 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1044 1045 switch (clk->id) { 1046 case ASPEED_CLK_GATE_MAC1CLK: 1047 ast2600_configure_mac(priv->scu, 1); 1048 break; 1049 case ASPEED_CLK_GATE_MAC2CLK: 1050 ast2600_configure_mac(priv->scu, 2); 1051 break; 1052 case ASPEED_CLK_GATE_MAC3CLK: 1053 ast2600_configure_mac(priv->scu, 3); 1054 break; 1055 case ASPEED_CLK_GATE_MAC4CLK: 1056 ast2600_configure_mac(priv->scu, 4); 1057 break; 1058 case ASPEED_CLK_GATE_SDCLK: 1059 ast2600_enable_sdclk(priv->scu); 1060 break; 1061 case ASPEED_CLK_GATE_SDEXTCLK: 1062 ast2600_enable_extsdclk(priv->scu); 1063 break; 1064 case ASPEED_CLK_GATE_EMMCCLK: 1065 ast2600_enable_emmcclk(priv->scu); 1066 break; 1067 case ASPEED_CLK_GATE_EMMCEXTCLK: 1068 ast2600_enable_extemmcclk(priv->scu); 1069 break; 1070 case ASPEED_CLK_GATE_FSICLK: 1071 ast2600_enable_fsiclk(priv->scu); 1072 break; 1073 case ASPEED_CLK_GATE_USBPORT1CLK: 1074 ast2600_enable_usbahclk(priv->scu); 1075 break; 1076 case ASPEED_CLK_GATE_USBPORT2CLK: 1077 ast2600_enable_usbbhclk(priv->scu); 1078 break; 1079 default: 1080 pr_debug("can't enable clk \n"); 1081 return -ENOENT; 1082 break; 1083 } 1084 1085 return 0; 1086 } 1087 1088 struct clk_ops ast2600_clk_ops = { 1089 .get_rate = ast2600_clk_get_rate, 1090 .set_rate = ast2600_clk_set_rate, 1091 .enable = ast2600_clk_enable, 1092 }; 1093 1094 static int ast2600_clk_probe(struct udevice *dev) 1095 { 1096 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1097 u32 uart_clk_source; 1098 1099 priv->scu = devfdt_get_addr_ptr(dev); 1100 if (IS_ERR(priv->scu)) 1101 return PTR_ERR(priv->scu); 1102 1103 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 1104 0x0); 1105 1106 if(uart_clk_source) { 1107 if(uart_clk_source & GENMASK(5, 0)) 1108 setbits_le32(&priv->scu->clk_sel4, uart_clk_source & GENMASK(5, 0)); 1109 if(uart_clk_source & GENMASK(12, 6)) 1110 setbits_le32(&priv->scu->clk_sel5, uart_clk_source & GENMASK(12, 6)); 1111 } 1112 1113 1114 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1115 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1116 ast2600_configure_mac12_clk(priv->scu); 1117 ast2600_configure_mac34_clk(priv->scu); 1118 1119 /* RSA clock = HPLL/3 */ 1120 setbits_le32(&priv->scu->clk_sel1, BIT(19)); 1121 setbits_le32(&priv->scu->clk_sel1, BIT(27)); 1122 1123 return 0; 1124 } 1125 1126 static int ast2600_clk_bind(struct udevice *dev) 1127 { 1128 int ret; 1129 1130 /* The reset driver does not have a device node, so bind it here */ 1131 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1132 if (ret) 1133 debug("Warning: No reset driver: ret=%d\n", ret); 1134 1135 return 0; 1136 } 1137 1138 #if CONFIG_IS_ENABLED(CMD_CLK) 1139 struct aspeed_clks { 1140 ulong id; 1141 const char *name; 1142 }; 1143 1144 static struct aspeed_clks aspeed_clk_names[] = { 1145 { ASPEED_CLK_HPLL, "hpll" }, 1146 { ASPEED_CLK_MPLL, "mpll" }, 1147 { ASPEED_CLK_APLL, "apll" }, 1148 { ASPEED_CLK_EPLL, "epll" }, 1149 { ASPEED_CLK_DPLL, "dpll" }, 1150 { ASPEED_CLK_AHB, "hclk" }, 1151 { ASPEED_CLK_APB1, "pclk1" }, 1152 { ASPEED_CLK_APB2, "pclk2" }, 1153 { ASPEED_CLK_BCLK, "bclk" }, 1154 { ASPEED_CLK_UARTX, "uxclk" }, 1155 { ASPEED_CLK_HUARTX, "huxclk" }, 1156 }; 1157 1158 int soc_clk_dump(void) 1159 { 1160 struct udevice *dev; 1161 struct clk clk; 1162 unsigned long rate; 1163 int i, ret; 1164 1165 ret = uclass_get_device_by_driver(UCLASS_CLK, 1166 DM_GET_DRIVER(aspeed_scu), &dev); 1167 if (ret) 1168 return ret; 1169 1170 printf("Clk\t\tHz\n"); 1171 1172 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1173 clk.id = aspeed_clk_names[i].id; 1174 ret = clk_request(dev, &clk); 1175 if (ret < 0) { 1176 debug("%s clk_request() failed: %d\n", __func__, ret); 1177 continue; 1178 } 1179 1180 ret = clk_get_rate(&clk); 1181 rate = ret; 1182 1183 clk_free(&clk); 1184 1185 if (ret == -ENOTSUPP) { 1186 printf("clk ID %lu not supported yet\n", 1187 aspeed_clk_names[i].id); 1188 continue; 1189 } 1190 if (ret < 0) { 1191 printf("%s %lu: get_rate err: %d\n", 1192 __func__, aspeed_clk_names[i].id, ret); 1193 continue; 1194 } 1195 1196 printf("%s(%3lu):\t%lu\n", 1197 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1198 } 1199 1200 return 0; 1201 } 1202 #endif 1203 1204 static const struct udevice_id ast2600_clk_ids[] = { 1205 { .compatible = "aspeed,ast2600-scu", }, 1206 { } 1207 }; 1208 1209 U_BOOT_DRIVER(aspeed_scu) = { 1210 .name = "aspeed_scu", 1211 .id = UCLASS_CLK, 1212 .of_match = ast2600_clk_ids, 1213 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1214 .ops = &ast2600_clk_ops, 1215 .bind = ast2600_clk_bind, 1216 .probe = ast2600_clk_probe, 1217 }; 1218