1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings, taken from Aspeed SDK 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 {.in = AST2600_CLK_IN, .out = 400000000, 77 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 78 .cfg.ext_reg = 0x31, 79 }, 80 {.in = AST2600_CLK_IN, .out = 200000000, 81 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 82 .cfg.ext_reg = 0x3f 83 }, 84 {.in = AST2600_CLK_IN, .out = 334000000, 85 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 86 .cfg.ext_reg = 0x14d 87 }, 88 89 {.in = AST2600_CLK_IN, .out = 1000000000, 90 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 91 .cfg.ext_reg = 0x3d 92 }, 93 94 {.in = AST2600_CLK_IN, .out = 50000000, 95 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 96 .cfg.ext_reg = 0x31 97 }, 98 }; 99 100 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 101 { 102 u32 clkin = AST2600_CLK_IN; 103 u32 pll_reg = 0; 104 unsigned int mult, div = 1; 105 106 switch(pll_idx) { 107 case ASPEED_CLK_HPLL: 108 pll_reg = readl(&scu->h_pll_param); 109 break; 110 case ASPEED_CLK_MPLL: 111 pll_reg = readl(&scu->m_pll_param); 112 break; 113 case ASPEED_CLK_DPLL: 114 pll_reg = readl(&scu->d_pll_param); 115 break; 116 case ASPEED_CLK_EPLL: 117 pll_reg = readl(&scu->e_pll_param); 118 break; 119 120 } 121 if (pll_reg & BIT(24)) { 122 /* Pass through mode */ 123 mult = div = 1; 124 } else { 125 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 126 union ast2600_pll_reg reg; 127 reg.w = pll_reg; 128 mult = (reg.b.m + 1) / (reg.b.n + 1); 129 div = (reg.b.p + 1); 130 } 131 return ((clkin * mult)/div); 132 133 } 134 135 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 136 { 137 u32 clkin = AST2600_CLK_IN; 138 u32 apll_reg = readl(&scu->a_pll_param); 139 unsigned int mult, div = 1; 140 141 if (apll_reg & BIT(20)) { 142 /* Pass through mode */ 143 mult = div = 1; 144 } else { 145 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 146 u32 m = (apll_reg >> 5) & 0x3f; 147 u32 od = (apll_reg >> 4) & 0x1; 148 u32 n = apll_reg & 0xf; 149 150 mult = (2 - od) * (m + 2); 151 div = n + 1; 152 } 153 return ((clkin * mult)/div); 154 } 155 156 static u32 ast2600_a0_axi_ahb_div_table[] = { 157 2, 2, 3, 4, 158 }; 159 160 static u32 ast2600_a1_axi_ahb_div0_table[] = { 161 3, 2, 3, 4, 162 }; 163 164 static u32 ast2600_a1_axi_ahb_div1_table[] = { 165 3, 4, 6, 8, 166 }; 167 168 static u32 ast2600_a1_axi_ahb_default_table[] = { 169 3, 4, 3, 4, 2, 2, 2, 2, 170 }; 171 172 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 173 { 174 u32 hw_rev = readl(&scu->chip_id0); 175 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 176 u32 axi_div = 1; 177 u32 ahb_div = 0; 178 u32 rate = 0; 179 180 if (hw_rev & BIT(16)) { 181 if(hwstrap1 & BIT(16)) { 182 ast2600_a1_axi_ahb_div1_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 183 axi_div = 1; 184 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 185 } else { 186 ast2600_a1_axi_ahb_div0_table[0] = ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 187 axi_div = 2; 188 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 189 } 190 } else { 191 //a0 : fix axi = hpll / 2 192 axi_div = 2; 193 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 194 } 195 196 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 197 return (rate / axi_div / ahb_div); 198 } 199 200 static u32 ast2600_hpll_pclk1_div_table[] = { 201 4, 8, 12, 16, 20, 24, 28, 32, 202 }; 203 204 static u32 ast2600_hpll_pclk2_div_table[] = { 205 2, 4, 6, 8, 10, 12, 14, 16, 206 }; 207 208 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 209 { 210 u32 clk_sel1 = readl(&scu->clk_sel1); 211 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 212 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 213 214 return (rate / apb_div); 215 } 216 217 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 218 { 219 u32 clk_sel4 = readl(&scu->clk_sel4); 220 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 221 u32 rate = ast2600_get_hclk(scu); 222 223 return (rate / apb_div); 224 } 225 226 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 227 { 228 u32 clk_in = 0; 229 u32 uxclk_sel = readl(&scu->clk_sel5); 230 231 uxclk_sel &= 0x3; 232 switch(uxclk_sel) { 233 case 0: 234 clk_in = ast2600_get_apll_rate(scu) / 4; 235 break; 236 case 1: 237 clk_in = ast2600_get_apll_rate(scu) / 2; 238 break; 239 case 2: 240 clk_in = ast2600_get_apll_rate(scu); 241 break; 242 case 3: 243 clk_in = ast2600_get_hclk(scu); 244 break; 245 } 246 247 return clk_in; 248 } 249 250 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 251 { 252 u32 clk_in = 0; 253 u32 huclk_sel = readl(&scu->clk_sel5); 254 255 huclk_sel = ((huclk_sel >> 3) & 0x3); 256 switch(huclk_sel) { 257 case 0: 258 clk_in = ast2600_get_apll_rate(scu) / 4; 259 break; 260 case 1: 261 clk_in = ast2600_get_apll_rate(scu) / 2; 262 break; 263 case 2: 264 clk_in = ast2600_get_apll_rate(scu); 265 break; 266 case 3: 267 clk_in = ast2600_get_hclk(scu); 268 break; 269 } 270 271 return clk_in; 272 } 273 274 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 275 { 276 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 277 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 278 unsigned int mult, div; 279 280 u32 n = (div_reg >> 8) & 0x3ff; 281 u32 r = div_reg & 0xff; 282 283 mult = r; 284 div = (n * 2); 285 return (clk_in * mult)/div; 286 } 287 288 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 289 { 290 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 291 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 292 293 unsigned int mult, div; 294 295 u32 n = (div_reg >> 8) & 0x3ff; 296 u32 r = div_reg & 0xff; 297 298 mult = r; 299 div = (n * 2); 300 return (clk_in * mult)/div; 301 } 302 303 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 304 { 305 u32 clkin = 0; 306 u32 clk_sel = readl(&scu->clk_sel4); 307 u32 div = (clk_sel >> 28) & 0x7; 308 309 if(clk_sel & BIT(8)) { 310 clkin = ast2600_get_apll_rate(scu); 311 } else { 312 clkin = ast2600_get_hclk(scu); 313 } 314 div = (div + 1) << 1; 315 316 return (clkin / div); 317 } 318 319 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 320 { 321 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 322 u32 clk_sel = readl(&scu->clk_sel1); 323 u32 div = (clk_sel >> 12) & 0x7; 324 325 div = (div + 1) << 2; 326 327 return (clkin / div); 328 } 329 330 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 331 { 332 u32 uart_sel = readl(&scu->clk_sel4); 333 u32 uart_sel5 = readl(&scu->clk_sel5); 334 ulong uart_clk = 0; 335 336 switch(uart_idx) { 337 case 1: 338 case 2: 339 case 3: 340 case 4: 341 case 6: 342 if(uart_sel & BIT(uart_idx - 1)) 343 uart_clk = ast2600_get_uart_huxclk_rate(scu) ; 344 else 345 uart_clk = ast2600_get_uart_uxclk_rate(scu) ; 346 break; 347 case 5: //24mhz is come form usb phy 48Mhz 348 { 349 u8 uart5_clk_sel = 0; 350 //high bit 351 if (readl(&scu->misc_ctrl1) & BIT(12)) 352 uart5_clk_sel = 0x2; 353 else 354 uart5_clk_sel = 0x0; 355 356 if (readl(&scu->clk_sel2) & BIT(14)) 357 uart5_clk_sel |= 0x1; 358 359 switch(uart5_clk_sel) { 360 case 0: 361 uart_clk = 24000000; 362 break; 363 case 1: 364 uart_clk = 192000000; 365 break; 366 case 2: 367 uart_clk = 24000000/13; 368 break; 369 case 3: 370 uart_clk = 192000000/13; 371 break; 372 } 373 } 374 break; 375 case 7: 376 case 8: 377 case 9: 378 case 10: 379 case 11: 380 case 12: 381 case 13: 382 if(uart_sel5 & BIT(uart_idx - 1)) 383 uart_clk = ast2600_get_uart_huxclk_rate(scu); 384 else 385 uart_clk = ast2600_get_uart_uxclk_rate(scu); 386 break; 387 } 388 389 return uart_clk; 390 } 391 392 static ulong ast2600_clk_get_rate(struct clk *clk) 393 { 394 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 395 ulong rate = 0; 396 397 switch (clk->id) { 398 case ASPEED_CLK_HPLL: 399 case ASPEED_CLK_EPLL: 400 case ASPEED_CLK_DPLL: 401 case ASPEED_CLK_MPLL: 402 rate = ast2600_get_pll_rate(priv->scu, clk->id); 403 break; 404 case ASPEED_CLK_AHB: 405 rate = ast2600_get_hclk(priv->scu); 406 break; 407 case ASPEED_CLK_APB1: 408 rate = ast2600_get_pclk1(priv->scu); 409 break; 410 case ASPEED_CLK_APB2: 411 rate = ast2600_get_pclk2(priv->scu); 412 break; 413 case ASPEED_CLK_APLL: 414 rate = ast2600_get_apll_rate(priv->scu); 415 break; 416 case ASPEED_CLK_GATE_UART1CLK: 417 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 418 break; 419 case ASPEED_CLK_GATE_UART2CLK: 420 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 421 break; 422 case ASPEED_CLK_GATE_UART3CLK: 423 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 424 break; 425 case ASPEED_CLK_GATE_UART4CLK: 426 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 427 break; 428 case ASPEED_CLK_GATE_UART5CLK: 429 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 430 break; 431 case ASPEED_CLK_SDIO: 432 rate = ast2600_get_sdio_clk_rate(priv->scu); 433 break; 434 case ASPEED_CLK_EMMC: 435 rate = ast2600_get_emmc_clk_rate(priv->scu); 436 break; 437 case ASPEED_CLK_UARTX: 438 rate = ast2600_get_uart_uxclk_rate(priv->scu); 439 break; 440 case ASPEED_CLK_HUARTX: 441 rate = ast2600_get_uart_huxclk_rate(priv->scu); 442 break; 443 default: 444 pr_debug("can't get clk rate \n"); 445 return -ENOENT; 446 break; 447 } 448 449 return rate; 450 } 451 452 /** 453 * @brief lookup PLL divider config by input/output rate 454 * @param[in] *pll - PLL descriptor 455 * @return true - if PLL divider config is found, false - else 456 * 457 * The function caller shall fill "pll->in" and "pll->out", then this function 458 * will search the lookup table to find a valid PLL divider configuration. 459 */ 460 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 461 { 462 u32 i; 463 bool is_found = false; 464 465 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 466 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 467 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 468 is_found = true; 469 pll->cfg.reg.w = def_cfg->cfg.reg.w; 470 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 471 break; 472 } 473 } 474 return is_found; 475 } 476 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 477 struct ast2600_pll_cfg *p_cfg, int pll_idx) 478 { 479 u32 addr, addr_ext; 480 u32 reg; 481 482 switch (pll_idx) { 483 case ASPEED_CLK_HPLL: 484 addr = (u32)(&scu->h_pll_param); 485 addr_ext = (u32)(&scu->h_pll_ext_param); 486 break; 487 case ASPEED_CLK_MPLL: 488 addr = (u32)(&scu->m_pll_param); 489 addr_ext = (u32)(&scu->m_pll_ext_param); 490 break; 491 case ASPEED_CLK_DPLL: 492 addr = (u32)(&scu->d_pll_param); 493 addr_ext = (u32)(&scu->d_pll_ext_param); 494 break; 495 case ASPEED_CLK_EPLL: 496 addr = (u32)(&scu->e_pll_param); 497 addr_ext = (u32)(&scu->e_pll_ext_param); 498 break; 499 default: 500 debug("unknown PLL index\n"); 501 return 1; 502 } 503 504 p_cfg->reg.b.bypass = 0; 505 p_cfg->reg.b.off = 1; 506 p_cfg->reg.b.reset = 1; 507 508 reg = readl(addr); 509 reg &= ~GENMASK(25, 0); 510 reg |= p_cfg->reg.w; 511 writel(reg, addr); 512 513 /* write extend parameter */ 514 writel(p_cfg->ext_reg, addr_ext); 515 udelay(100); 516 p_cfg->reg.b.off = 0; 517 p_cfg->reg.b.reset = 0; 518 reg &= ~GENMASK(25, 0); 519 reg |= p_cfg->reg.w; 520 writel(reg, addr); 521 522 /* polling PLL lock status */ 523 while(0 == (readl(addr_ext) & BIT(31))); 524 525 return 0; 526 } 527 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 528 { 529 struct ast2600_pll_desc mpll; 530 531 mpll.in = AST2600_CLK_IN; 532 mpll.out = rate; 533 if (false == ast2600_search_clock_config(&mpll)) { 534 printf("error!! unable to find valid DDR clock setting\n"); 535 return 0; 536 } 537 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 538 539 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 540 } 541 542 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 543 { 544 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 545 546 ulong new_rate; 547 switch (clk->id) { 548 case ASPEED_CLK_MPLL: 549 new_rate = ast2600_configure_ddr(priv->scu, rate); 550 break; 551 default: 552 return -ENOENT; 553 } 554 555 return new_rate; 556 } 557 558 #define SCU_CLKSTOP_MAC1 (20) 559 #define SCU_CLKSTOP_MAC2 (21) 560 #define SCU_CLKSTOP_MAC3 (20) 561 #define SCU_CLKSTOP_MAC4 (21) 562 563 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 564 { 565 /* scu340[25:0]: 1G default delay */ 566 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 567 MAC_DEF_DELAY_1G); 568 569 /* set 100M/10M default delay */ 570 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 571 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 572 573 /* MAC AHB = HPLL / 6 */ 574 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 575 576 return 0; 577 } 578 579 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 580 { 581 582 /* 583 * scu350[31] RGMII 125M source: 0 = from IO pin 584 * scu350[25:0] MAC 1G delay 585 */ 586 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 587 MAC34_DEF_DELAY_1G); 588 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 589 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 590 591 /* 592 * clock source seletion and divider 593 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 594 * scu310[18:16] : RMII 50M = HCLK_200M / 4 595 */ 596 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 597 ((0x0 << 24) | (0x3 << 16))); 598 599 /* 600 * set driving strength 601 * scu458[3:2] : MAC4 driving strength 602 * scu458[1:0] : MAC3 driving strength 603 */ 604 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 605 (0x3 << 2) | (0x3 << 0)); 606 607 return 0; 608 } 609 610 /** 611 * ast2600 RGMII clock source tree 612 * 613 * 125M from external PAD -------->|\ 614 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 615 * | |---->| divider |---->|/ + 616 * EPLL -->|/ | 617 * | 618 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 619 * | 620 * +--------------------------->|\ 621 * | |----> RGMII 125M for MAC#3 & MAC#4 622 * HCLK 200M ---->|divider|---->|/ 623 * 624 * To simplify the control flow: 625 * 1. RGMII 1/2 always use EPLL as the internal clock source 626 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 627 * 628 * 125M from external PAD -------->|\ 629 * | |---->RGMII 125M for MAC#1 & MAC#2 630 * EPLL---->| divider |--->|/ + 631 * | 632 * +<--------------------|RGMIICK PAD output enable|<-------------+ 633 * | 634 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 635 */ 636 #define RGMIICK_SRC_PAD 0 637 #define RGMIICK_SRC_EPLL 1 /* recommended */ 638 #define RGMIICK_SRC_HPLL 2 639 640 #define RGMIICK_DIV2 1 641 #define RGMIICK_DIV3 2 642 #define RGMIICK_DIV4 3 643 #define RGMIICK_DIV5 4 644 #define RGMIICK_DIV6 5 645 #define RGMIICK_DIV7 6 646 #define RGMIICK_DIV8 7 /* recommended */ 647 648 #define RMIICK_DIV4 0 649 #define RMIICK_DIV8 1 650 #define RMIICK_DIV12 2 651 #define RMIICK_DIV16 3 652 #define RMIICK_DIV20 4 /* recommended */ 653 #define RMIICK_DIV24 5 654 #define RMIICK_DIV28 6 655 #define RMIICK_DIV32 7 656 657 struct ast2600_mac_clk_div { 658 u32 src; /* 0=external PAD, 1=internal PLL */ 659 u32 fin; /* divider input speed */ 660 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 661 u32 fout; /* fout = fin / n */ 662 }; 663 664 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 665 .src = ASPEED_CLK_EPLL, 666 .fin = 1000000000, 667 .n = RGMIICK_DIV8, 668 .fout = 125000000, 669 }; 670 671 struct ast2600_mac_clk_div rmii_clk_defconfig = { 672 .src = ASPEED_CLK_EPLL, 673 .fin = 1000000000, 674 .n = RMIICK_DIV20, 675 .fout = 50000000, 676 }; 677 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 678 struct ast2600_mac_clk_div *p_cfg) 679 { 680 struct ast2600_pll_desc pll; 681 682 pll.in = AST2600_CLK_IN; 683 pll.out = p_cfg->fin; 684 if (false == ast2600_search_clock_config(&pll)) { 685 printf("error!! unable to find valid ETHNET MAC clock " 686 "setting\n"); 687 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 688 pll.cfg.ext_reg); 689 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 690 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 691 return; 692 } 693 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 694 } 695 696 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 697 struct ast2600_mac_clk_div *p_cfg) 698 { 699 u32 reg_304 = readl(&p_scu->clk_sel2); 700 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 701 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 702 703 reg_340 &= ~GENMASK(31, 29); 704 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 705 reg_340 |= BIT(28); 706 if ((p_cfg->src == ASPEED_CLK_EPLL) || 707 (p_cfg->src == ASPEED_CLK_HPLL)) { 708 /* 709 * re-init PLL if the current PLL output frequency doesn't match 710 * the divider setting 711 */ 712 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 713 ast2600_init_mac_pll(p_scu, p_cfg); 714 } 715 /* scu340[31]: select RGMII 125M from internal source */ 716 reg_340 |= BIT(31); 717 } 718 719 reg_304 &= ~GENMASK(23, 20); 720 721 /* set clock divider */ 722 reg_304 |= (p_cfg->n & 0x7) << 20; 723 724 /* select internal clock source */ 725 if (ASPEED_CLK_HPLL == p_cfg->src) { 726 reg_304 |= BIT(23); 727 } 728 729 /* RGMII 3/4 clock source select */ 730 reg_350 &= ~BIT(31); 731 #if 0 732 if (RGMII_3_4_CLK_SRC_HCLK == p_cfg->rgmii_3_4_clk_src) { 733 reg_350 |= BIT(31); 734 } 735 736 /* set clock divider */ 737 reg_310 &= ~GENMASK(22, 20); 738 reg_310 |= (p_cfg->hclk_clk_div & 0x7) << 20; 739 #endif 740 741 writel(reg_304, &p_scu->clk_sel2); 742 writel(reg_340, &p_scu->mac12_clk_delay); 743 writel(reg_350, &p_scu->mac34_clk_delay); 744 } 745 746 /** 747 * ast2600 RMII/NCSI clock source tree 748 * 749 * HPLL -->|\ 750 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 751 * EPLL -->|/ 752 * 753 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 754 */ 755 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 756 struct ast2600_mac_clk_div *p_cfg) 757 { 758 u32 reg_304; 759 u32 reg_310; 760 761 if ((p_cfg->src == ASPEED_CLK_EPLL) || 762 (p_cfg->src == ASPEED_CLK_HPLL)) { 763 /* 764 * re-init PLL if the current PLL output frequency doesn't match 765 * the divider setting 766 */ 767 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 768 ast2600_init_mac_pll(p_scu, p_cfg); 769 } 770 } 771 772 reg_304 = readl(&p_scu->clk_sel2); 773 reg_310 = readl(&p_scu->clk_sel4); 774 775 reg_304 &= ~GENMASK(19, 16); 776 777 /* set RMII 1/2 clock divider */ 778 reg_304 |= (p_cfg->n & 0x7) << 16; 779 780 /* RMII clock source selection */ 781 if (ASPEED_CLK_HPLL == p_cfg->src) { 782 reg_304 |= BIT(19); 783 } 784 785 /* set RMII 3/4 clock divider */ 786 reg_310 &= ~GENMASK(18, 16); 787 reg_310 |= (0x3 << 16); 788 789 writel(reg_304, &p_scu->clk_sel2); 790 writel(reg_310, &p_scu->clk_sel4); 791 } 792 793 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 794 { 795 u32 reset_bit; 796 u32 clkstop_bit; 797 798 switch (index) { 799 case 1: 800 reset_bit = BIT(ASPEED_RESET_MAC1); 801 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 802 writel(reset_bit, &scu->sysreset_ctrl1); 803 udelay(100); 804 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 805 mdelay(10); 806 writel(reset_bit, &scu->sysreset_clr_ctrl1); 807 808 break; 809 case 2: 810 reset_bit = BIT(ASPEED_RESET_MAC2); 811 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 812 writel(reset_bit, &scu->sysreset_ctrl1); 813 udelay(100); 814 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 815 mdelay(10); 816 writel(reset_bit, &scu->sysreset_clr_ctrl1); 817 break; 818 case 3: 819 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 820 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 821 writel(reset_bit, &scu->sysreset_ctrl2); 822 udelay(100); 823 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 824 mdelay(10); 825 writel(reset_bit, &scu->sysreset_clr_ctrl2); 826 break; 827 case 4: 828 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 829 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 830 writel(reset_bit, &scu->sysreset_ctrl2); 831 udelay(100); 832 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 833 mdelay(10); 834 writel(reset_bit, &scu->sysreset_clr_ctrl2); 835 break; 836 default: 837 return -EINVAL; 838 } 839 840 return 0; 841 } 842 843 #define SCU_CLKSTOP_SDIO 4 844 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 845 { 846 u32 reset_bit; 847 u32 clkstop_bit; 848 849 reset_bit = BIT(ASPEED_RESET_SD - 32); 850 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 851 852 writel(reset_bit, &scu->sysreset_ctrl2); 853 854 udelay(100); 855 //enable clk 856 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 857 mdelay(10); 858 writel(reset_bit, &scu->sysreset_clr_ctrl2); 859 860 return 0; 861 } 862 863 #define SCU_CLKSTOP_EXTSD 31 864 #define SCU_CLK_SD_MASK (0x7 << 28) 865 #define SCU_CLK_SD_DIV(x) (x << 28) 866 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 867 868 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 869 { 870 u32 clk_sel = readl(&scu->clk_sel4); 871 u32 enableclk_bit; 872 u32 rate = 0; 873 u32 div = 0; 874 int i = 0; 875 876 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 877 878 //ast2600 sd controller max clk is 200Mhz : use apll for clock source 800/4 = 200 : controller max is 200mhz 879 rate = ast2600_get_apll_rate(scu); 880 for(i = 0; i < 8; i++) { 881 div = (i + 1) * 2; 882 if ((rate / div) <= 200000000) 883 break; 884 } 885 clk_sel &= ~SCU_CLK_SD_MASK; 886 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 887 writel(clk_sel, &scu->clk_sel4); 888 889 //enable clk 890 setbits_le32(&scu->clk_sel4, enableclk_bit); 891 892 return 0; 893 } 894 895 #define SCU_CLKSTOP_EMMC 27 896 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 897 { 898 u32 reset_bit; 899 u32 clkstop_bit; 900 901 reset_bit = BIT(ASPEED_RESET_EMMC); 902 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 903 904 writel(reset_bit, &scu->sysreset_ctrl1); 905 udelay(100); 906 //enable clk 907 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 908 mdelay(10); 909 writel(reset_bit, &scu->sysreset_clr_ctrl1); 910 911 return 0; 912 } 913 914 #define SCU_CLKSTOP_EXTEMMC 15 915 #define SCU_CLK_EMMC_MASK (0x7 << 12) 916 #define SCU_CLK_EMMC_DIV(x) (x << 12) 917 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) //AST2600A1 918 919 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 920 { 921 u32 revision_id = readl(&scu->chip_id0); 922 u32 clk_sel = readl(&scu->clk_sel1); 923 u32 enableclk_bit; 924 u32 rate = 0; 925 u32 div = 0; 926 int i = 0; 927 928 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 929 930 //ast2600 eMMC controller max clk is 200Mhz 931 if(((revision_id & GENMASK(23, 16)) >> 16)) { 932 //AST2600A1 ~ : use mpll to be clk source 933 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 934 for(i = 0; i < 8; i++) { 935 div = (i + 1) * 2; 936 if ((rate / div) <= 200000000) 937 break; 938 } 939 940 clk_sel &= ~SCU_CLK_EMMC_MASK; 941 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 942 writel(clk_sel, &scu->clk_sel1); 943 944 } else { 945 //AST2600A0 : use hpll to be clk source 946 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 947 948 for(i = 0; i < 8; i++) { 949 div = (i + 1) * 4; 950 if ((rate / div) <= 200000000) 951 break; 952 } 953 954 clk_sel &= ~SCU_CLK_EMMC_MASK; 955 clk_sel |= SCU_CLK_EMMC_DIV(i); 956 writel(clk_sel, &scu->clk_sel1); 957 } 958 959 //enable clk 960 setbits_le32(&scu->clk_sel1, enableclk_bit); 961 962 return 0; 963 } 964 965 #define SCU_CLKSTOP_FSICLK 30 966 967 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 968 { 969 u32 reset_bit; 970 u32 clkstop_bit; 971 972 reset_bit = BIT(ASPEED_RESET_FSI % 32); 973 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 974 975 /* The FSI clock is shared between masters. If it's already on 976 * don't touch it, as that will reset the existing master. */ 977 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 978 debug("%s: already running, not touching it\n", __func__); 979 return 0; 980 } 981 982 writel(reset_bit, &scu->sysreset_ctrl2); 983 udelay(100); 984 //enable clk 985 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 986 mdelay(10); 987 writel(reset_bit, &scu->sysreset_clr_ctrl2); 988 989 return 0; 990 } 991 992 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 993 { 994 u32 reset_bit; 995 u32 clkstop_bit; 996 997 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 998 clkstop_bit = BIT(14); 999 1000 writel(reset_bit, &scu->sysreset_ctrl1); 1001 udelay(100); 1002 //enable phy clk 1003 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1004 mdelay(20); 1005 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1006 1007 return 0; 1008 } 1009 1010 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1011 { 1012 u32 reset_bit; 1013 u32 clkstop_bit; 1014 1015 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1016 clkstop_bit = BIT(7); 1017 1018 writel(reset_bit, &scu->sysreset_ctrl1); 1019 udelay(100); 1020 //enable phy clk 1021 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1022 mdelay(20); 1023 1024 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1025 1026 return 0; 1027 } 1028 1029 static int ast2600_clk_enable(struct clk *clk) 1030 { 1031 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1032 1033 switch (clk->id) { 1034 case ASPEED_CLK_GATE_MAC1CLK: 1035 ast2600_configure_mac(priv->scu, 1); 1036 break; 1037 case ASPEED_CLK_GATE_MAC2CLK: 1038 ast2600_configure_mac(priv->scu, 2); 1039 break; 1040 case ASPEED_CLK_GATE_MAC3CLK: 1041 ast2600_configure_mac(priv->scu, 3); 1042 break; 1043 case ASPEED_CLK_GATE_MAC4CLK: 1044 ast2600_configure_mac(priv->scu, 4); 1045 break; 1046 case ASPEED_CLK_GATE_SDCLK: 1047 ast2600_enable_sdclk(priv->scu); 1048 break; 1049 case ASPEED_CLK_GATE_SDEXTCLK: 1050 ast2600_enable_extsdclk(priv->scu); 1051 break; 1052 case ASPEED_CLK_GATE_EMMCCLK: 1053 ast2600_enable_emmcclk(priv->scu); 1054 break; 1055 case ASPEED_CLK_GATE_EMMCEXTCLK: 1056 ast2600_enable_extemmcclk(priv->scu); 1057 break; 1058 case ASPEED_CLK_GATE_FSICLK: 1059 ast2600_enable_fsiclk(priv->scu); 1060 break; 1061 case ASPEED_CLK_GATE_USBPORT1CLK: 1062 ast2600_enable_usbahclk(priv->scu); 1063 break; 1064 case ASPEED_CLK_GATE_USBPORT2CLK: 1065 ast2600_enable_usbbhclk(priv->scu); 1066 break; 1067 default: 1068 pr_debug("can't enable clk \n"); 1069 return -ENOENT; 1070 break; 1071 } 1072 1073 return 0; 1074 } 1075 1076 struct clk_ops ast2600_clk_ops = { 1077 .get_rate = ast2600_clk_get_rate, 1078 .set_rate = ast2600_clk_set_rate, 1079 .enable = ast2600_clk_enable, 1080 }; 1081 1082 static int ast2600_clk_probe(struct udevice *dev) 1083 { 1084 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1085 u32 uart_clk_source; 1086 1087 priv->scu = devfdt_get_addr_ptr(dev); 1088 if (IS_ERR(priv->scu)) 1089 return PTR_ERR(priv->scu); 1090 1091 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 1092 0x0); 1093 1094 if(uart_clk_source) { 1095 if(uart_clk_source & GENMASK(5, 0)) 1096 setbits_le32(&priv->scu->clk_sel4, uart_clk_source & GENMASK(5, 0)); 1097 if(uart_clk_source & GENMASK(12, 6)) 1098 setbits_le32(&priv->scu->clk_sel5, uart_clk_source & GENMASK(12, 6)); 1099 } 1100 1101 1102 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1103 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1104 ast2600_configure_mac12_clk(priv->scu); 1105 ast2600_configure_mac34_clk(priv->scu); 1106 1107 return 0; 1108 } 1109 1110 static int ast2600_clk_bind(struct udevice *dev) 1111 { 1112 int ret; 1113 1114 /* The reset driver does not have a device node, so bind it here */ 1115 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1116 if (ret) 1117 debug("Warning: No reset driver: ret=%d\n", ret); 1118 1119 return 0; 1120 } 1121 1122 #if CONFIG_IS_ENABLED(CMD_CLK) 1123 struct aspeed_clks { 1124 ulong id; 1125 const char *name; 1126 }; 1127 1128 static struct aspeed_clks aspeed_clk_names[] = { 1129 { ASPEED_CLK_HPLL, "hpll" }, 1130 { ASPEED_CLK_MPLL, "mpll" }, 1131 { ASPEED_CLK_APLL, "apll" }, 1132 { ASPEED_CLK_EPLL, "epll" }, 1133 { ASPEED_CLK_DPLL, "dpll" }, 1134 { ASPEED_CLK_AHB, "hclk" }, 1135 { ASPEED_CLK_APB1, "pclk1" }, 1136 { ASPEED_CLK_APB2, "pclk2" }, 1137 { ASPEED_CLK_UARTX, "uxclk" }, 1138 { ASPEED_CLK_HUARTX, "huxclk" }, 1139 }; 1140 1141 int soc_clk_dump(void) 1142 { 1143 struct udevice *dev; 1144 struct clk clk; 1145 unsigned long rate; 1146 int i, ret; 1147 1148 ret = uclass_get_device_by_driver(UCLASS_CLK, 1149 DM_GET_DRIVER(aspeed_scu), &dev); 1150 if (ret) 1151 return ret; 1152 1153 printf("Clk\t\tHz\n"); 1154 1155 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1156 clk.id = aspeed_clk_names[i].id; 1157 ret = clk_request(dev, &clk); 1158 if (ret < 0) { 1159 debug("%s clk_request() failed: %d\n", __func__, ret); 1160 continue; 1161 } 1162 1163 ret = clk_get_rate(&clk); 1164 rate = ret; 1165 1166 clk_free(&clk); 1167 1168 if (ret == -ENOTSUPP) { 1169 printf("clk ID %lu not supported yet\n", 1170 aspeed_clk_names[i].id); 1171 continue; 1172 } 1173 if (ret < 0) { 1174 printf("%s %lu: get_rate err: %d\n", 1175 __func__, aspeed_clk_names[i].id, ret); 1176 continue; 1177 } 1178 1179 printf("%s(%3lu):\t%lu\n", 1180 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1181 } 1182 1183 return 0; 1184 } 1185 #endif 1186 1187 static const struct udevice_id ast2600_clk_ids[] = { 1188 { .compatible = "aspeed,ast2600-scu", }, 1189 { } 1190 }; 1191 1192 U_BOOT_DRIVER(aspeed_scu) = { 1193 .name = "aspeed_scu", 1194 .id = UCLASS_CLK, 1195 .of_match = ast2600_clk_ids, 1196 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1197 .ops = &ast2600_clk_ops, 1198 .bind = ast2600_clk_bind, 1199 .probe = ast2600_clk_probe, 1200 }; 1201