1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 u32 w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 u32 ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, { 84 .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f, 90 }, { 91 .in = AST2600_CLK_IN, 92 .out = 334000000, 93 .cfg.reg.b.m = 667, 94 .cfg.reg.b.n = 4, 95 .cfg.reg.b.p = 9, 96 .cfg.ext_reg = 0x14d, 97 }, { 98 .in = AST2600_CLK_IN, 99 .out = 1000000000, 100 .cfg.reg.b.m = 119, 101 .cfg.reg.b.n = 2, 102 .cfg.reg.b.p = 0, 103 .cfg.ext_reg = 0x3d, 104 }, { 105 .in = AST2600_CLK_IN, 106 .out = 50000000, 107 .cfg.reg.b.m = 95, 108 .cfg.reg.b.n = 2, 109 .cfg.reg.b.p = 15, 110 .cfg.ext_reg = 0x31, 111 }, 112 }; 113 114 union mac_delay_1g { 115 u32 w; 116 struct { 117 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 118 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 119 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 120 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 121 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 122 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 123 unsigned int rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 124 unsigned int rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 125 unsigned int rgmiick_pad_dir : 1; /* bit[28] */ 126 unsigned int rmii_50m_oe_1 : 1; /* bit[29] */ 127 unsigned int rmii_50m_oe_2 : 1; /* bit[30] */ 128 unsigned int rgmii_125m_o_sel : 1; /* bit[31] */ 129 } b; 130 }; 131 132 union mac_delay_100_10 { 133 u32 w; 134 struct { 135 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 136 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 137 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 138 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 139 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 140 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 141 unsigned int reserved_0 : 6; /* bit[31:26] */ 142 } b; 143 }; 144 145 struct mac_delay_config { 146 u32 tx_delay_1000; 147 u32 rx_delay_1000; 148 u32 tx_delay_100; 149 u32 rx_delay_100; 150 u32 tx_delay_10; 151 u32 rx_delay_10; 152 }; 153 154 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 155 { 156 u32 clkin = AST2600_CLK_IN; 157 u32 pll_reg = 0; 158 unsigned int mult, div = 1; 159 160 switch (pll_idx) { 161 case ASPEED_CLK_HPLL: 162 pll_reg = readl(&scu->h_pll_param); 163 break; 164 case ASPEED_CLK_MPLL: 165 pll_reg = readl(&scu->m_pll_param); 166 break; 167 case ASPEED_CLK_DPLL: 168 pll_reg = readl(&scu->d_pll_param); 169 break; 170 case ASPEED_CLK_EPLL: 171 pll_reg = readl(&scu->e_pll_param); 172 break; 173 } 174 if (pll_reg & BIT(24)) { 175 /* Pass through mode */ 176 mult = 1; 177 div = 1; 178 } else { 179 union ast2600_pll_reg reg; 180 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 181 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 182 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 183 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 184 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 185 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 186 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 187 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 188 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 189 */ 190 reg.w = pll_reg; 191 if (pll_idx == ASPEED_CLK_HPLL) { 192 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 193 194 if (hwstrap1 & BIT(10)) { 195 reg.b.m = 0x5F; 196 } else { 197 if (hwstrap1 & BIT(8)) 198 reg.b.m = 0xBF; 199 /* Otherwise keep default 0x8F */ 200 } 201 } 202 mult = (reg.b.m + 1) / (reg.b.n + 1); 203 div = (reg.b.p + 1); 204 } 205 206 return ((clkin * mult) / div); 207 } 208 209 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 210 { 211 u32 hw_rev = readl(&scu->chip_id1); 212 u32 clkin = AST2600_CLK_IN; 213 u32 apll_reg = readl(&scu->a_pll_param); 214 unsigned int mult, div = 1; 215 216 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 2) { 217 //after A2 version 218 if (apll_reg & BIT(24)) { 219 /* Pass through mode */ 220 mult = 1; 221 div = 1; 222 } else { 223 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 224 u32 m = apll_reg & 0x1fff; 225 u32 n = (apll_reg >> 13) & 0x3f; 226 u32 p = (apll_reg >> 19) & 0xf; 227 228 mult = (m + 1); 229 div = (n + 1) * (p + 1); 230 } 231 } else { 232 if (apll_reg & BIT(20)) { 233 /* Pass through mode */ 234 mult = 1; 235 div = 1; 236 } else { 237 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 238 u32 m = (apll_reg >> 5) & 0x3f; 239 u32 od = (apll_reg >> 4) & 0x1; 240 u32 n = apll_reg & 0xf; 241 242 mult = (2 - od) * (m + 2); 243 div = n + 1; 244 } 245 } 246 247 return ((clkin * mult) / div); 248 } 249 250 static u32 ast2600_a0_axi_ahb_div_table[] = { 251 2, 252 2, 253 3, 254 4, 255 }; 256 257 static u32 ast2600_a1_axi_ahb_div0_table[] = { 258 3, 259 2, 260 3, 261 4, 262 }; 263 264 static u32 ast2600_a1_axi_ahb_div1_table[] = { 265 3, 266 4, 267 6, 268 8, 269 }; 270 271 static u32 ast2600_a1_axi_ahb_default_table[] = { 272 3, 4, 3, 4, 2, 2, 2, 2, 273 }; 274 275 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 276 { 277 u32 hw_rev = readl(&scu->chip_id1); 278 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 279 u32 axi_div = 1; 280 u32 ahb_div = 0; 281 u32 rate = 0; 282 283 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 284 //After A0 285 if (hwstrap1 & BIT(16)) { 286 ast2600_a1_axi_ahb_div1_table[0] = 287 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 288 0x7] * 2; 289 axi_div = 1; 290 ahb_div = 291 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 292 0x3]; 293 } else { 294 ast2600_a1_axi_ahb_div0_table[0] = 295 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 296 0x7]; 297 axi_div = 2; 298 ahb_div = 299 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 300 0x3]; 301 } 302 } else { 303 //A0 : fix axi = hpll / 2 304 axi_div = 2; 305 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 306 } 307 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 308 309 return (rate / axi_div / ahb_div); 310 } 311 312 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 313 { 314 u32 rate; 315 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 316 317 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 318 319 return (rate / ((bclk_sel + 1) * 4)); 320 } 321 322 static u32 ast2600_hpll_pclk1_div_table[] = { 323 4, 8, 12, 16, 20, 24, 28, 32, 324 }; 325 326 static u32 ast2600_hpll_pclk2_div_table[] = { 327 2, 4, 6, 8, 10, 12, 14, 16, 328 }; 329 330 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 331 { 332 u32 clk_sel1 = readl(&scu->clk_sel1); 333 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 334 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 335 336 return (rate / apb_div); 337 } 338 339 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 340 { 341 u32 clk_sel4 = readl(&scu->clk_sel4); 342 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 343 u32 rate = ast2600_get_hclk(scu); 344 345 return (rate / apb_div); 346 } 347 348 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 349 { 350 u32 clk_in = 0; 351 u32 uxclk_sel = readl(&scu->clk_sel5); 352 353 uxclk_sel &= 0x3; 354 switch (uxclk_sel) { 355 case 0: 356 clk_in = ast2600_get_apll_rate(scu) / 4; 357 break; 358 case 1: 359 clk_in = ast2600_get_apll_rate(scu) / 2; 360 break; 361 case 2: 362 clk_in = ast2600_get_apll_rate(scu); 363 break; 364 case 3: 365 clk_in = ast2600_get_hclk(scu); 366 break; 367 } 368 369 return clk_in; 370 } 371 372 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 373 { 374 u32 clk_in = 0; 375 u32 huclk_sel = readl(&scu->clk_sel5); 376 377 huclk_sel = ((huclk_sel >> 3) & 0x3); 378 switch (huclk_sel) { 379 case 0: 380 clk_in = ast2600_get_apll_rate(scu) / 4; 381 break; 382 case 1: 383 clk_in = ast2600_get_apll_rate(scu) / 2; 384 break; 385 case 2: 386 clk_in = ast2600_get_apll_rate(scu); 387 break; 388 case 3: 389 clk_in = ast2600_get_hclk(scu); 390 break; 391 } 392 393 return clk_in; 394 } 395 396 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 397 { 398 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 399 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 400 unsigned int mult, div; 401 402 u32 n = (div_reg >> 8) & 0x3ff; 403 u32 r = div_reg & 0xff; 404 405 mult = r; 406 div = (n * 2); 407 return (clk_in * mult) / div; 408 } 409 410 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 411 { 412 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 413 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 414 415 unsigned int mult, div; 416 417 u32 n = (div_reg >> 8) & 0x3ff; 418 u32 r = div_reg & 0xff; 419 420 mult = r; 421 div = (n * 2); 422 return (clk_in * mult) / div; 423 } 424 425 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 426 { 427 u32 clkin = 0; 428 u32 clk_sel = readl(&scu->clk_sel4); 429 u32 div = (clk_sel >> 28) & 0x7; 430 431 if (clk_sel & BIT(8)) 432 clkin = ast2600_get_apll_rate(scu); 433 else 434 clkin = ast2600_get_hclk(scu); 435 436 div = (div + 1) << 1; 437 438 return (clkin / div); 439 } 440 441 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 442 { 443 u32 mmc_clk_src = readl(&scu->clk_sel1); 444 u32 clkin; 445 u32 clk_sel = readl(&scu->clk_sel1); 446 u32 div = (clk_sel >> 12) & 0x7; 447 448 if (mmc_clk_src & BIT(11)) { 449 /* emmc clock comes from MPLL */ 450 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 451 div = (div + 1) * 2; 452 } else { 453 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 454 div = (div + 1) << 2; 455 } 456 457 return (clkin / div); 458 } 459 460 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 461 { 462 u32 uart_sel = readl(&scu->clk_sel4); 463 u32 uart_sel5 = readl(&scu->clk_sel5); 464 ulong uart_clk = 0; 465 466 switch (uart_idx) { 467 case 1: 468 case 2: 469 case 3: 470 case 4: 471 case 6: 472 if (uart_sel & BIT(uart_idx - 1)) 473 uart_clk = ast2600_get_uart_huxclk_rate(scu); 474 else 475 uart_clk = ast2600_get_uart_uxclk_rate(scu); 476 break; 477 case 5: //24mhz is come form usb phy 48Mhz 478 { 479 u8 uart5_clk_sel = 0; 480 //high bit 481 if (readl(&scu->misc_ctrl1) & BIT(12)) 482 uart5_clk_sel = 0x2; 483 else 484 uart5_clk_sel = 0x0; 485 486 if (readl(&scu->clk_sel2) & BIT(14)) 487 uart5_clk_sel |= 0x1; 488 489 switch (uart5_clk_sel) { 490 case 0: 491 uart_clk = 24000000; 492 break; 493 case 1: 494 uart_clk = 192000000; 495 break; 496 case 2: 497 uart_clk = 24000000 / 13; 498 break; 499 case 3: 500 uart_clk = 192000000 / 13; 501 break; 502 } 503 } break; 504 case 7: 505 case 8: 506 case 9: 507 case 10: 508 case 11: 509 case 12: 510 case 13: 511 if (uart_sel5 & BIT(uart_idx - 1)) 512 uart_clk = ast2600_get_uart_huxclk_rate(scu); 513 else 514 uart_clk = ast2600_get_uart_uxclk_rate(scu); 515 break; 516 } 517 518 return uart_clk; 519 } 520 521 static ulong ast2600_clk_get_rate(struct clk *clk) 522 { 523 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 524 ulong rate = 0; 525 526 switch (clk->id) { 527 case ASPEED_CLK_HPLL: 528 case ASPEED_CLK_EPLL: 529 case ASPEED_CLK_DPLL: 530 case ASPEED_CLK_MPLL: 531 rate = ast2600_get_pll_rate(priv->scu, clk->id); 532 break; 533 case ASPEED_CLK_AHB: 534 rate = ast2600_get_hclk(priv->scu); 535 break; 536 case ASPEED_CLK_APB1: 537 rate = ast2600_get_pclk1(priv->scu); 538 break; 539 case ASPEED_CLK_APB2: 540 rate = ast2600_get_pclk2(priv->scu); 541 break; 542 case ASPEED_CLK_APLL: 543 rate = ast2600_get_apll_rate(priv->scu); 544 break; 545 case ASPEED_CLK_GATE_UART1CLK: 546 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 547 break; 548 case ASPEED_CLK_GATE_UART2CLK: 549 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 550 break; 551 case ASPEED_CLK_GATE_UART3CLK: 552 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 553 break; 554 case ASPEED_CLK_GATE_UART4CLK: 555 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 556 break; 557 case ASPEED_CLK_GATE_UART5CLK: 558 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 559 break; 560 case ASPEED_CLK_BCLK: 561 rate = ast2600_get_bclk_rate(priv->scu); 562 break; 563 case ASPEED_CLK_SDIO: 564 rate = ast2600_get_sdio_clk_rate(priv->scu); 565 break; 566 case ASPEED_CLK_EMMC: 567 rate = ast2600_get_emmc_clk_rate(priv->scu); 568 break; 569 case ASPEED_CLK_UARTX: 570 rate = ast2600_get_uart_uxclk_rate(priv->scu); 571 break; 572 case ASPEED_CLK_HUARTX: 573 rate = ast2600_get_uart_huxclk_rate(priv->scu); 574 break; 575 default: 576 pr_debug("can't get clk rate\n"); 577 return -ENOENT; 578 } 579 580 return rate; 581 } 582 583 /** 584 * @brief lookup PLL divider config by input/output rate 585 * @param[in] *pll - PLL descriptor 586 * @return true - if PLL divider config is found, false - else 587 * The function caller shall fill "pll->in" and "pll->out", 588 * then this function will search the lookup table 589 * to find a valid PLL divider configuration. 590 */ 591 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 592 { 593 u32 i; 594 bool is_found = false; 595 596 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 597 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 598 599 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 600 is_found = true; 601 pll->cfg.reg.w = def_cfg->cfg.reg.w; 602 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 603 break; 604 } 605 } 606 return is_found; 607 } 608 609 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 610 struct ast2600_pll_cfg *p_cfg, int pll_idx) 611 { 612 u32 addr, addr_ext; 613 u32 reg; 614 615 switch (pll_idx) { 616 case ASPEED_CLK_HPLL: 617 addr = (u32)(&scu->h_pll_param); 618 addr_ext = (u32)(&scu->h_pll_ext_param); 619 break; 620 case ASPEED_CLK_MPLL: 621 addr = (u32)(&scu->m_pll_param); 622 addr_ext = (u32)(&scu->m_pll_ext_param); 623 break; 624 case ASPEED_CLK_DPLL: 625 addr = (u32)(&scu->d_pll_param); 626 addr_ext = (u32)(&scu->d_pll_ext_param); 627 break; 628 case ASPEED_CLK_EPLL: 629 addr = (u32)(&scu->e_pll_param); 630 addr_ext = (u32)(&scu->e_pll_ext_param); 631 break; 632 default: 633 debug("unknown PLL index\n"); 634 return 1; 635 } 636 637 p_cfg->reg.b.bypass = 0; 638 p_cfg->reg.b.off = 1; 639 p_cfg->reg.b.reset = 1; 640 641 reg = readl(addr); 642 reg &= ~GENMASK(25, 0); 643 reg |= p_cfg->reg.w; 644 writel(reg, addr); 645 646 /* write extend parameter */ 647 writel(p_cfg->ext_reg, addr_ext); 648 udelay(100); 649 p_cfg->reg.b.off = 0; 650 p_cfg->reg.b.reset = 0; 651 reg &= ~GENMASK(25, 0); 652 reg |= p_cfg->reg.w; 653 writel(reg, addr); 654 while (!(readl(addr_ext) & BIT(31))) 655 ; 656 657 return 0; 658 } 659 660 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 661 { 662 struct ast2600_pll_desc mpll; 663 664 mpll.in = AST2600_CLK_IN; 665 mpll.out = rate; 666 if (ast2600_search_clock_config(&mpll) == false) { 667 printf("error!! unable to find valid DDR clock setting\n"); 668 return 0; 669 } 670 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 671 672 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 673 } 674 675 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 676 { 677 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 678 ulong new_rate; 679 680 switch (clk->id) { 681 case ASPEED_CLK_MPLL: 682 new_rate = ast2600_configure_ddr(priv->scu, rate); 683 break; 684 default: 685 return -ENOENT; 686 } 687 688 return new_rate; 689 } 690 691 #define SCU_CLKSTOP_MAC1 (20) 692 #define SCU_CLKSTOP_MAC2 (21) 693 #define SCU_CLKSTOP_MAC3 (20) 694 #define SCU_CLKSTOP_MAC4 (21) 695 696 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu, struct udevice *dev) 697 { 698 union mac_delay_1g reg_1g; 699 union mac_delay_100_10 reg_100, reg_10; 700 struct mac_delay_config mac1_cfg, mac2_cfg; 701 int ret; 702 703 reg_1g.w = (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0)) | 704 MAC_DEF_DELAY_1G; 705 reg_100.w = MAC_DEF_DELAY_100M; 706 reg_10.w = MAC_DEF_DELAY_10M; 707 708 ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg, sizeof(mac1_cfg) / sizeof(u32)); 709 if (!ret) { 710 reg_1g.b.tx_delay_1 = mac1_cfg.tx_delay_1000; 711 reg_1g.b.rx_delay_1 = mac1_cfg.rx_delay_1000; 712 reg_100.b.tx_delay_1 = mac1_cfg.tx_delay_100; 713 reg_100.b.rx_delay_1 = mac1_cfg.rx_delay_100; 714 reg_10.b.tx_delay_1 = mac1_cfg.tx_delay_10; 715 reg_10.b.rx_delay_1 = mac1_cfg.rx_delay_10; 716 } 717 718 ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg, sizeof(mac2_cfg) / sizeof(u32)); 719 if (!ret) { 720 reg_1g.b.tx_delay_2 = mac2_cfg.tx_delay_1000; 721 reg_1g.b.rx_delay_2 = mac2_cfg.rx_delay_1000; 722 reg_100.b.tx_delay_2 = mac2_cfg.tx_delay_100; 723 reg_100.b.rx_delay_2 = mac2_cfg.rx_delay_100; 724 reg_10.b.tx_delay_2 = mac2_cfg.tx_delay_10; 725 reg_10.b.rx_delay_2 = mac2_cfg.rx_delay_10; 726 } 727 728 writel(reg_1g.w, &scu->mac12_clk_delay); 729 writel(reg_100.w, &scu->mac12_clk_delay_100M); 730 writel(reg_10.w, &scu->mac12_clk_delay_10M); 731 732 /* MAC AHB = HPLL / 6 */ 733 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 734 735 return 0; 736 } 737 738 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu, struct udevice *dev) 739 { 740 union mac_delay_1g reg_1g; 741 union mac_delay_100_10 reg_100, reg_10; 742 struct mac_delay_config mac3_cfg, mac4_cfg; 743 int ret; 744 745 /* 746 * scu350[31] RGMII 125M source: 0 = from IO pin 747 * scu350[25:0] MAC 1G delay 748 */ 749 reg_1g.w = (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0)) | 750 MAC34_DEF_DELAY_1G; 751 reg_1g.b.rgmii_125m_o_sel = 0; 752 reg_100.w = MAC34_DEF_DELAY_100M; 753 reg_10.w = MAC34_DEF_DELAY_10M; 754 755 ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32)); 756 if (!ret) { 757 reg_1g.b.tx_delay_1 = mac3_cfg.tx_delay_1000; 758 reg_1g.b.rx_delay_1 = mac3_cfg.rx_delay_1000; 759 reg_100.b.tx_delay_1 = mac3_cfg.tx_delay_100; 760 reg_100.b.rx_delay_1 = mac3_cfg.rx_delay_100; 761 reg_10.b.tx_delay_1 = mac3_cfg.tx_delay_10; 762 reg_10.b.rx_delay_1 = mac3_cfg.rx_delay_10; 763 } 764 765 ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32)); 766 if (!ret) { 767 reg_1g.b.tx_delay_2 = mac4_cfg.tx_delay_1000; 768 reg_1g.b.rx_delay_2 = mac4_cfg.rx_delay_1000; 769 reg_100.b.tx_delay_2 = mac4_cfg.tx_delay_100; 770 reg_100.b.rx_delay_2 = mac4_cfg.rx_delay_100; 771 reg_10.b.tx_delay_2 = mac4_cfg.tx_delay_10; 772 reg_10.b.rx_delay_2 = mac4_cfg.rx_delay_10; 773 } 774 775 writel(reg_1g.w, &scu->mac34_clk_delay); 776 writel(reg_100.w, &scu->mac34_clk_delay_100M); 777 writel(reg_10.w, &scu->mac34_clk_delay_10M); 778 779 /* 780 * clock source seletion and divider 781 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 782 * scu310[18:16] : RMII 50M = HCLK_200M / 4 783 */ 784 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 785 ((0x0 << 24) | (0x3 << 16))); 786 787 /* 788 * set driving strength 789 * scu458[3:2] : MAC4 driving strength 790 * scu458[1:0] : MAC3 driving strength 791 */ 792 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 793 (0x3 << 2) | (0x3 << 0)); 794 795 return 0; 796 } 797 798 /** 799 * ast2600 RGMII clock source tree 800 * 125M from external PAD -------->|\ 801 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 802 * | |---->| divider |---->|/ + 803 * EPLL -->|/ | 804 * | 805 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 806 * | 807 * +--------------------------->|\ 808 * | |----> RGMII 125M for MAC#3 & MAC#4 809 * HCLK 200M ---->|divider|---->|/ 810 * To simplify the control flow: 811 * 1. RGMII 1/2 always use EPLL as the internal clock source 812 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 813 * 125M from external PAD -------->|\ 814 * | |---->RGMII 125M for MAC#1 & MAC#2 815 * EPLL---->| divider |--->|/ + 816 * | 817 * +<--------------------|RGMIICK PAD output enable|<-------------+ 818 * | 819 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 820 */ 821 #define RGMIICK_SRC_PAD 0 822 #define RGMIICK_SRC_EPLL 1 /* recommended */ 823 #define RGMIICK_SRC_HPLL 2 824 825 #define RGMIICK_DIV2 1 826 #define RGMIICK_DIV3 2 827 #define RGMIICK_DIV4 3 828 #define RGMIICK_DIV5 4 829 #define RGMIICK_DIV6 5 830 #define RGMIICK_DIV7 6 831 #define RGMIICK_DIV8 7 /* recommended */ 832 833 #define RMIICK_DIV4 0 834 #define RMIICK_DIV8 1 835 #define RMIICK_DIV12 2 836 #define RMIICK_DIV16 3 837 #define RMIICK_DIV20 4 /* recommended */ 838 #define RMIICK_DIV24 5 839 #define RMIICK_DIV28 6 840 #define RMIICK_DIV32 7 841 842 struct ast2600_mac_clk_div { 843 u32 src; /* 0=external PAD, 1=internal PLL */ 844 u32 fin; /* divider input speed */ 845 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 846 u32 fout; /* fout = fin / n */ 847 }; 848 849 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 850 .src = ASPEED_CLK_EPLL, 851 .fin = 1000000000, 852 .n = RGMIICK_DIV8, 853 .fout = 125000000, 854 }; 855 856 struct ast2600_mac_clk_div rmii_clk_defconfig = { 857 .src = ASPEED_CLK_EPLL, 858 .fin = 1000000000, 859 .n = RMIICK_DIV20, 860 .fout = 50000000, 861 }; 862 863 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 864 struct ast2600_mac_clk_div *p_cfg) 865 { 866 struct ast2600_pll_desc pll; 867 868 pll.in = AST2600_CLK_IN; 869 pll.out = p_cfg->fin; 870 if (ast2600_search_clock_config(&pll) == false) { 871 pr_err("unable to find valid ETHNET MAC clock setting\n"); 872 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 873 pll.cfg.ext_reg); 874 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 875 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 876 return; 877 } 878 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 879 } 880 881 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 882 struct ast2600_mac_clk_div *p_cfg) 883 { 884 u32 reg_304 = readl(&p_scu->clk_sel2); 885 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 886 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 887 888 reg_340 &= ~GENMASK(31, 29); 889 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 890 reg_340 |= BIT(28); 891 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 892 /* 893 * re-init PLL if the current PLL output frequency doesn't match 894 * the divider setting 895 */ 896 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 897 ast2600_init_mac_pll(p_scu, p_cfg); 898 /* scu340[31]: select RGMII 125M from internal source */ 899 reg_340 |= BIT(31); 900 } 901 902 reg_304 &= ~GENMASK(23, 20); 903 904 /* set clock divider */ 905 reg_304 |= (p_cfg->n & 0x7) << 20; 906 907 /* select internal clock source */ 908 if (p_cfg->src == ASPEED_CLK_HPLL) 909 reg_304 |= BIT(23); 910 911 /* RGMII 3/4 clock source select */ 912 reg_350 &= ~BIT(31); 913 914 writel(reg_304, &p_scu->clk_sel2); 915 writel(reg_340, &p_scu->mac12_clk_delay); 916 writel(reg_350, &p_scu->mac34_clk_delay); 917 } 918 919 /** 920 * ast2600 RMII/NCSI clock source tree 921 * HPLL -->|\ 922 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 923 * EPLL -->|/ 924 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 925 */ 926 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 927 struct ast2600_mac_clk_div *p_cfg) 928 { 929 u32 reg_304; 930 u32 reg_310; 931 932 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 933 /* 934 * re-init PLL if the current PLL output frequency doesn't match 935 * the divider setting 936 */ 937 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 938 ast2600_init_mac_pll(p_scu, p_cfg); 939 } 940 941 reg_304 = readl(&p_scu->clk_sel2); 942 reg_310 = readl(&p_scu->clk_sel4); 943 944 reg_304 &= ~GENMASK(19, 16); 945 946 /* set RMII 1/2 clock divider */ 947 reg_304 |= (p_cfg->n & 0x7) << 16; 948 949 /* RMII clock source selection */ 950 if (p_cfg->src == ASPEED_CLK_HPLL) 951 reg_304 |= BIT(19); 952 953 /* set RMII 3/4 clock divider */ 954 reg_310 &= ~GENMASK(18, 16); 955 reg_310 |= (0x3 << 16); 956 957 writel(reg_304, &p_scu->clk_sel2); 958 writel(reg_310, &p_scu->clk_sel4); 959 } 960 961 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 962 { 963 u32 reset_bit; 964 u32 clkstop_bit; 965 966 switch (index) { 967 case 1: 968 reset_bit = BIT(ASPEED_RESET_MAC1); 969 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 970 writel(reset_bit, &scu->sysreset_ctrl1); 971 udelay(100); 972 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 973 mdelay(10); 974 writel(reset_bit, &scu->sysreset_clr_ctrl1); 975 break; 976 case 2: 977 reset_bit = BIT(ASPEED_RESET_MAC2); 978 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 979 writel(reset_bit, &scu->sysreset_ctrl1); 980 udelay(100); 981 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 982 mdelay(10); 983 writel(reset_bit, &scu->sysreset_clr_ctrl1); 984 break; 985 case 3: 986 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 987 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 988 writel(reset_bit, &scu->sysreset_ctrl2); 989 udelay(100); 990 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 991 mdelay(10); 992 writel(reset_bit, &scu->sysreset_clr_ctrl2); 993 break; 994 case 4: 995 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 996 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 997 writel(reset_bit, &scu->sysreset_ctrl2); 998 udelay(100); 999 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1000 mdelay(10); 1001 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 1007 return 0; 1008 } 1009 1010 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 1011 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 1012 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 1013 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 1014 { 1015 u32 clk_sel = readl(&scu->clk_sel1); 1016 1017 /* Configure RSA clock = HPLL/4 */ 1018 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 1019 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 1020 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(3); 1021 1022 writel(clk_sel, &scu->clk_sel1); 1023 } 1024 1025 #define SCU_CLKSTOP_SDIO 4 1026 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 1027 { 1028 u32 reset_bit; 1029 u32 clkstop_bit; 1030 1031 reset_bit = BIT(ASPEED_RESET_SD - 32); 1032 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 1033 1034 writel(reset_bit, &scu->sysreset_ctrl2); 1035 1036 udelay(100); 1037 //enable clk 1038 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1039 mdelay(10); 1040 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1041 1042 return 0; 1043 } 1044 1045 #define SCU_CLKSTOP_EXTSD 31 1046 #define SCU_CLK_SD_MASK (0x7 << 28) 1047 #define SCU_CLK_SD_DIV(x) ((x) << 28) 1048 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 1049 1050 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 1051 { 1052 u32 clk_sel = readl(&scu->clk_sel4); 1053 u32 enableclk_bit; 1054 u32 rate = 0; 1055 u32 div = 0; 1056 int i = 0; 1057 1058 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 1059 1060 /* ast2600 sd controller max clk is 200Mhz : 1061 * use apll for clock source 800/4 = 200 : controller max is 200mhz 1062 */ 1063 rate = ast2600_get_apll_rate(scu); 1064 for (i = 0; i < 8; i++) { 1065 div = (i + 1) * 2; 1066 if ((rate / div) <= 200000000) 1067 break; 1068 } 1069 clk_sel &= ~SCU_CLK_SD_MASK; 1070 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 1071 writel(clk_sel, &scu->clk_sel4); 1072 1073 //enable clk 1074 setbits_le32(&scu->clk_sel4, enableclk_bit); 1075 1076 return 0; 1077 } 1078 1079 #define SCU_CLKSTOP_EMMC 27 1080 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 1081 { 1082 u32 reset_bit; 1083 u32 clkstop_bit; 1084 1085 reset_bit = BIT(ASPEED_RESET_EMMC); 1086 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 1087 1088 writel(reset_bit, &scu->sysreset_ctrl1); 1089 udelay(100); 1090 //enable clk 1091 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1092 mdelay(10); 1093 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1094 1095 return 0; 1096 } 1097 1098 #define SCU_CLKSTOP_EXTEMMC 15 1099 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1100 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 1101 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1102 1103 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1104 { 1105 u32 revision_id = readl(&scu->chip_id1); 1106 u32 clk_sel = readl(&scu->clk_sel1); 1107 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1108 u32 rate = 0; 1109 u32 div = 0; 1110 int i = 0; 1111 1112 /* 1113 * ast2600 eMMC controller max clk is 200Mhz 1114 * HPll->1/2->|\ 1115 * |->SCU300[11]->SCU300[14:12][1/N] + 1116 * MPLL------>|/ | 1117 * +----------------------------------------------+ 1118 * | 1119 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1120 */ 1121 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1122 //AST2600A1 : use mpll to be clk source 1123 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1124 for (i = 0; i < 8; i++) { 1125 div = (i + 1) * 2; 1126 if ((rate / div) <= 200000000) 1127 break; 1128 } 1129 1130 clk_sel &= ~SCU_CLK_EMMC_MASK; 1131 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1132 writel(clk_sel, &scu->clk_sel1); 1133 1134 } else { 1135 //AST2600A0 : use hpll to be clk source 1136 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1137 1138 for (i = 0; i < 8; i++) { 1139 div = (i + 1) * 4; 1140 if ((rate / div) <= 200000000) 1141 break; 1142 } 1143 1144 clk_sel &= ~SCU_CLK_EMMC_MASK; 1145 clk_sel |= SCU_CLK_EMMC_DIV(i); 1146 writel(clk_sel, &scu->clk_sel1); 1147 } 1148 setbits_le32(&scu->clk_sel1, enableclk_bit); 1149 1150 return 0; 1151 } 1152 1153 #define SCU_CLKSTOP_FSICLK 30 1154 1155 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1156 { 1157 u32 reset_bit; 1158 u32 clkstop_bit; 1159 1160 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1161 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1162 1163 /* The FSI clock is shared between masters. If it's already on 1164 * don't touch it, as that will reset the existing master. 1165 */ 1166 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1167 debug("%s: already running, not touching it\n", __func__); 1168 return 0; 1169 } 1170 1171 writel(reset_bit, &scu->sysreset_ctrl2); 1172 udelay(100); 1173 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1174 mdelay(10); 1175 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1176 1177 return 0; 1178 } 1179 1180 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1181 { 1182 u32 reset_bit; 1183 u32 clkstop_bit; 1184 1185 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1186 clkstop_bit = BIT(14); 1187 1188 writel(reset_bit, &scu->sysreset_ctrl1); 1189 udelay(100); 1190 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1191 mdelay(20); 1192 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1193 1194 return 0; 1195 } 1196 1197 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1198 { 1199 u32 reset_bit; 1200 u32 clkstop_bit; 1201 1202 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1203 clkstop_bit = BIT(7); 1204 1205 writel(reset_bit, &scu->sysreset_ctrl1); 1206 udelay(100); 1207 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1208 mdelay(20); 1209 1210 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1211 1212 return 0; 1213 } 1214 1215 /* also known as yclk */ 1216 static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) 1217 { 1218 u32 reset_bit; 1219 u32 clkstop_bit; 1220 1221 reset_bit = BIT(ASPEED_RESET_HACE); 1222 clkstop_bit = BIT(13); 1223 1224 writel(reset_bit, &scu->sysreset_ctrl1); 1225 udelay(100); 1226 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1227 mdelay(20); 1228 1229 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1230 1231 return 0; 1232 } 1233 1234 static ulong ast2600_enable_rsaeccclk(struct ast2600_scu *scu) 1235 { 1236 u32 clkstop_bit; 1237 1238 clkstop_bit = BIT(24); 1239 1240 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1241 mdelay(20); 1242 1243 return 0; 1244 } 1245 1246 static int ast2600_clk_enable(struct clk *clk) 1247 { 1248 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1249 1250 switch (clk->id) { 1251 case ASPEED_CLK_GATE_MAC1CLK: 1252 ast2600_configure_mac(priv->scu, 1); 1253 break; 1254 case ASPEED_CLK_GATE_MAC2CLK: 1255 ast2600_configure_mac(priv->scu, 2); 1256 break; 1257 case ASPEED_CLK_GATE_MAC3CLK: 1258 ast2600_configure_mac(priv->scu, 3); 1259 break; 1260 case ASPEED_CLK_GATE_MAC4CLK: 1261 ast2600_configure_mac(priv->scu, 4); 1262 break; 1263 case ASPEED_CLK_GATE_SDCLK: 1264 ast2600_enable_sdclk(priv->scu); 1265 break; 1266 case ASPEED_CLK_GATE_SDEXTCLK: 1267 ast2600_enable_extsdclk(priv->scu); 1268 break; 1269 case ASPEED_CLK_GATE_EMMCCLK: 1270 ast2600_enable_emmcclk(priv->scu); 1271 break; 1272 case ASPEED_CLK_GATE_EMMCEXTCLK: 1273 ast2600_enable_extemmcclk(priv->scu); 1274 break; 1275 case ASPEED_CLK_GATE_FSICLK: 1276 ast2600_enable_fsiclk(priv->scu); 1277 break; 1278 case ASPEED_CLK_GATE_USBPORT1CLK: 1279 ast2600_enable_usbahclk(priv->scu); 1280 break; 1281 case ASPEED_CLK_GATE_USBPORT2CLK: 1282 ast2600_enable_usbbhclk(priv->scu); 1283 break; 1284 case ASPEED_CLK_GATE_YCLK: 1285 ast2600_enable_haceclk(priv->scu); 1286 break; 1287 case ASPEED_CLK_GATE_RSAECCCLK: 1288 ast2600_enable_rsaeccclk(priv->scu); 1289 break; 1290 default: 1291 pr_err("can't enable clk\n"); 1292 return -ENOENT; 1293 } 1294 1295 return 0; 1296 } 1297 1298 struct clk_ops ast2600_clk_ops = { 1299 .get_rate = ast2600_clk_get_rate, 1300 .set_rate = ast2600_clk_set_rate, 1301 .enable = ast2600_clk_enable, 1302 }; 1303 1304 static int ast2600_clk_probe(struct udevice *dev) 1305 { 1306 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1307 u32 uart_clk_source; 1308 1309 priv->scu = devfdt_get_addr_ptr(dev); 1310 if (IS_ERR(priv->scu)) 1311 return PTR_ERR(priv->scu); 1312 1313 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1314 1315 if (uart_clk_source) { 1316 if (uart_clk_source & GENMASK(5, 0)) 1317 setbits_le32(&priv->scu->clk_sel4, 1318 uart_clk_source & GENMASK(5, 0)); 1319 if (uart_clk_source & GENMASK(12, 6)) 1320 setbits_le32(&priv->scu->clk_sel5, 1321 uart_clk_source & GENMASK(12, 6)); 1322 } 1323 1324 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1325 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1326 ast2600_configure_mac12_clk(priv->scu, dev); 1327 ast2600_configure_mac34_clk(priv->scu, dev); 1328 ast2600_configure_rsa_ecc_clk(priv->scu); 1329 1330 return 0; 1331 } 1332 1333 static int ast2600_clk_bind(struct udevice *dev) 1334 { 1335 int ret; 1336 1337 /* The reset driver does not have a device node, so bind it here */ 1338 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1339 if (ret) 1340 debug("Warning: No reset driver: ret=%d\n", ret); 1341 1342 return 0; 1343 } 1344 1345 struct aspeed_clks { 1346 ulong id; 1347 const char *name; 1348 }; 1349 1350 static struct aspeed_clks aspeed_clk_names[] = { 1351 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1352 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1353 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1354 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1355 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1356 { ASPEED_CLK_HUARTX, "huxclk" }, 1357 }; 1358 1359 int soc_clk_dump(void) 1360 { 1361 struct udevice *dev; 1362 struct clk clk; 1363 unsigned long rate; 1364 int i, ret; 1365 1366 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1367 &dev); 1368 if (ret) 1369 return ret; 1370 1371 printf("Clk\t\tHz\n"); 1372 1373 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1374 clk.id = aspeed_clk_names[i].id; 1375 ret = clk_request(dev, &clk); 1376 if (ret < 0) { 1377 debug("%s clk_request() failed: %d\n", __func__, ret); 1378 continue; 1379 } 1380 1381 ret = clk_get_rate(&clk); 1382 rate = ret; 1383 1384 clk_free(&clk); 1385 1386 if (ret == -ENOTSUPP) { 1387 printf("clk ID %lu not supported yet\n", 1388 aspeed_clk_names[i].id); 1389 continue; 1390 } 1391 if (ret < 0) { 1392 printf("%s %lu: get_rate err: %d\n", __func__, 1393 aspeed_clk_names[i].id, ret); 1394 continue; 1395 } 1396 1397 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1398 aspeed_clk_names[i].id, rate); 1399 } 1400 1401 return 0; 1402 } 1403 1404 static const struct udevice_id ast2600_clk_ids[] = { 1405 { 1406 .compatible = "aspeed,ast2600-scu", 1407 }, 1408 {} 1409 }; 1410 1411 U_BOOT_DRIVER(aspeed_scu) = { 1412 .name = "aspeed_scu", 1413 .id = UCLASS_CLK, 1414 .of_match = ast2600_clk_ids, 1415 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1416 .ops = &ast2600_clk_ops, 1417 .bind = ast2600_clk_bind, 1418 .probe = ast2600_clk_probe, 1419 }; 1420