1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2016 Google, Inc 4 * 5 * Copyright (C) ASPEED Technology Inc. 6 * 7 */ 8 9 #include <common.h> 10 #include <clk-uclass.h> 11 #include <dm.h> 12 #include <asm/io.h> 13 #include <dm/lists.h> 14 #include <asm/arch/scu_ast2500.h> 15 #include <dt-bindings/clock/ast2500-clock.h> 16 #include <dt-bindings/reset/ast2500-reset.h> 17 18 /* 19 * MAC Clock Delay settings, taken from Aspeed SDK 20 */ 21 #define RGMII_TXCLK_ODLY 8 22 #define RMII_RXCLK_IDLY 2 23 24 /* 25 * TGMII Clock Duty constants, taken from Aspeed SDK 26 */ 27 #define RGMII2_TXCK_DUTY 0x66 28 #define RGMII1_TXCK_DUTY 0x64 29 30 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* 35 * Clock divider/multiplier configuration struct. 36 * For H-PLL and M-PLL the formula is 37 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 38 * M - Numerator 39 * N - Denumerator 40 * P - Post Divider 41 * They have the same layout in their control register. 42 * 43 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 44 * yet needed and ignored by clock configurations. 45 */ 46 struct ast2500_div_config { 47 unsigned int num; 48 unsigned int denum; 49 unsigned int post_div; 50 }; 51 52 extern u32 ast2500_get_clkin(struct ast2500_scu *scu) 53 { 54 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ 55 ? 25 * 1000 * 1000 : 24 * 1000 * 1000; 56 } 57 58 /* 59 * Get the rate of the M-PLL clock from input clock frequency and 60 * the value of the M-PLL Parameter Register. 61 */ 62 extern u32 ast2500_get_mpll_rate(struct ast2500_scu *scu) 63 { 64 u32 clkin = ast2500_get_clkin(scu); 65 u32 mpll_reg = readl(&scu->m_pll_param); 66 67 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; 68 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) 69 >> SCU_MPLL_DENUM_SHIFT; 70 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) 71 >> SCU_MPLL_POST_SHIFT; 72 73 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 74 } 75 76 /* 77 * Get the rate of the H-PLL clock from input clock frequency and 78 * the value of the H-PLL Parameter Register. 79 */ 80 extern u32 ast2500_get_hpll_rate(struct ast2500_scu *scu) 81 { 82 u32 clkin = ast2500_get_clkin(scu); 83 u32 hpll_reg = readl(&scu->h_pll_param); 84 85 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ 86 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; 87 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) 88 >> SCU_HPLL_DENUM_SHIFT; 89 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) 90 >> SCU_HPLL_POST_SHIFT; 91 92 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 93 } 94 95 /* 96 * Get the rate of the D-PLL clock from input clock frequency and 97 * the value of the D-PLL Parameter Register. 98 */ 99 extern u32 ast2500_get_dpll_rate(struct ast2500_scu *scu) 100 { 101 u32 clkin = ast2500_get_clkin(scu); 102 u32 dpll_reg = readl(&scu->d_pll_param); 103 104 /* F = clkin * [(M+1) / (N+1)] / (P + 1)/ (od + 1) */ 105 const ulong num = (dpll_reg & 0xff); 106 const ulong denum = (dpll_reg >> 8) & 0x1f; 107 const ulong post_div = (dpll_reg >> 13) & 0x3f; 108 const ulong od_div = (dpll_reg >> 19) & 0x7; 109 return (((clkin * ((num + 1) / (denum + 1))) / (post_div + 1))/ (od_div + 1)); 110 } 111 112 /* 113 * Get the rate of the D2-PLL clock from input clock frequency and 114 * the value of the D2-PLL Parameter Register. 115 */ 116 extern u32 ast2500_get_d2pll_rate(struct ast2500_scu *scu) 117 { 118 u32 clkin = ast2500_get_clkin(scu); 119 u32 d2pll_reg = readl(&scu->d2_pll_param); 120 121 /* F = clkin * [(M+1) / (N+1)] / (P + 1)/ (od + 1) */ 122 const ulong num = (d2pll_reg & 0xff); 123 const ulong denum = (d2pll_reg >> 8) & 0x1f; 124 const ulong post_div = (d2pll_reg >> 13) & 0x3f; 125 const ulong od_div = (d2pll_reg >> 19) & 0x7 ; 126 127 return (((clkin * ((num + 1) / (denum + 1))) / (post_div + 1))/ (od_div + 1)); 128 } 129 130 /** 131 * Get current rate or uart clock 132 * 133 * @scu SCU registers 134 * @uart_index UART index, 1-5 135 * 136 * @return current setting for uart clock rate 137 */ 138 static u32 ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) 139 { 140 /* 141 * ast2500 datasheet is very confusing when it comes to UART clocks, 142 * especially when CLKIN = 25 MHz. The settings are in 143 * different registers and it is unclear how they interact. 144 * 145 * This has only been tested with default settings and CLKIN = 24 MHz. 146 */ 147 u32 uart_clkin; 148 149 if (readl(&scu->misc_ctrl2) & 150 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) 151 uart_clkin = 192 * 1000 * 1000; 152 else 153 uart_clkin = 24 * 1000 * 1000; 154 155 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) 156 uart_clkin /= 13; 157 158 return uart_clkin; 159 } 160 161 static unsigned long ast2500_clk_get_rate(struct clk *clk) 162 { 163 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 164 ulong rate; 165 166 switch (clk->id) { 167 //HPLL 168 case ASPEED_CLK_HPLL: 169 rate = ast2500_get_hpll_rate(priv->scu); 170 break; 171 //HCLK 172 case ASPEED_CLK_AHB: 173 { 174 ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap) 175 & SCU_HWSTRAP_AXIAHB_DIV_MASK) 176 >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT); 177 ulong axi_div = 2; 178 179 rate = ast2500_get_hpll_rate(priv->scu); 180 rate = rate / axi_div / ahb_div; 181 } 182 break; 183 //mpll 184 case ASPEED_CLK_MPLL: 185 rate = ast2500_get_mpll_rate(priv->scu); 186 break; 187 //pclk 188 case ASPEED_CLK_APB: 189 { 190 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) 191 & SCU_PCLK_DIV_MASK) 192 >> SCU_PCLK_DIV_SHIFT); 193 rate = ast2500_get_hpll_rate(priv->scu); 194 rate = rate / apb_div; 195 } 196 break; 197 case ASPEED_CLK_GATE_UART1CLK: 198 rate = ast2500_get_uart_clk_rate(priv->scu, 1); 199 break; 200 case ASPEED_CLK_GATE_UART2CLK: 201 rate = ast2500_get_uart_clk_rate(priv->scu, 2); 202 break; 203 case ASPEED_CLK_GATE_UART3CLK: 204 rate = ast2500_get_uart_clk_rate(priv->scu, 3); 205 break; 206 case ASPEED_CLK_GATE_UART4CLK: 207 rate = ast2500_get_uart_clk_rate(priv->scu, 4); 208 break; 209 case ASPEED_CLK_GATE_UART5CLK: 210 rate = ast2500_get_uart_clk_rate(priv->scu, 5); 211 break; 212 default: 213 return -ENOENT; 214 } 215 216 return rate; 217 } 218 219 struct ast2500_clock_config { 220 ulong input_rate; 221 ulong rate; 222 struct ast2500_div_config cfg; 223 }; 224 225 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { 226 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 227 }; 228 229 static bool ast2500_get_clock_config_default(ulong input_rate, 230 ulong requested_rate, 231 struct ast2500_div_config *cfg) 232 { 233 int i; 234 235 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { 236 const struct ast2500_clock_config *default_cfg = 237 &ast2500_clock_config_defaults[i]; 238 if (default_cfg->input_rate == input_rate && 239 default_cfg->rate == requested_rate) { 240 *cfg = default_cfg->cfg; 241 return true; 242 } 243 } 244 245 return false; 246 } 247 248 /* 249 * @input_rate - the rate of input clock in Hz 250 * @requested_rate - desired output rate in Hz 251 * @div - this is an IN/OUT parameter, at input all fields of the config 252 * need to be set to their maximum allowed values. 253 * The result (the best config we could find), would also be returned 254 * in this structure. 255 * 256 * @return The clock rate, when the resulting div_config is used. 257 */ 258 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, 259 struct ast2500_div_config *cfg) 260 { 261 /* 262 * The assumption is that kHz precision is good enough and 263 * also enough to avoid overflow when multiplying. 264 */ 265 const ulong input_rate_khz = input_rate / 1000; 266 const ulong rate_khz = requested_rate / 1000; 267 const struct ast2500_div_config max_vals = *cfg; 268 struct ast2500_div_config it = { 0, 0, 0 }; 269 ulong delta = rate_khz; 270 ulong new_rate_khz = 0; 271 272 /* 273 * Look for a well known frequency first. 274 */ 275 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) 276 return requested_rate; 277 278 for (; it.denum <= max_vals.denum; ++it.denum) { 279 for (it.post_div = 0; it.post_div <= max_vals.post_div; 280 ++it.post_div) { 281 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 282 * (it.denum + 1); 283 if (it.num > max_vals.num) 284 continue; 285 286 new_rate_khz = (input_rate_khz 287 * ((it.num + 1) / (it.denum + 1))) 288 / (it.post_div + 1); 289 290 /* Keep the rate below requested one. */ 291 if (new_rate_khz > rate_khz) 292 continue; 293 294 if (new_rate_khz - rate_khz < delta) { 295 delta = new_rate_khz - rate_khz; 296 *cfg = it; 297 if (delta == 0) 298 return new_rate_khz * 1000; 299 } 300 } 301 } 302 303 return new_rate_khz * 1000; 304 } 305 306 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) 307 { 308 ulong clkin = ast2500_get_clkin(scu); 309 u32 mpll_reg; 310 struct ast2500_div_config div_cfg = { 311 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 312 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 313 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 314 }; 315 316 ast2500_calc_clock_config(clkin, rate, &div_cfg); 317 318 mpll_reg = readl(&scu->m_pll_param); 319 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 320 | SCU_MPLL_DENUM_MASK); 321 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 322 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 323 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 324 325 writel(mpll_reg, &scu->m_pll_param); 326 327 return ast2500_get_mpll_rate(scu); 328 } 329 330 #define SCU_CLKSTOP_MAC1 (20) 331 #define SCU_CLKSTOP_MAC2 (21) 332 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) 333 { 334 ulong hpll_rate = ast2500_get_hpll_rate(scu); 335 ulong required_rate; 336 u32 hwstrap; 337 u32 divisor; 338 u32 reset_bit; 339 u32 clkstop_bit; 340 u32 clk_delay_settings = 341 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 342 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 343 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 344 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); 345 346 /* 347 * According to data sheet, for 10/100 mode the MAC clock frequency 348 * should be at least 25MHz and for 1000 mode at least 100MHz 349 */ 350 hwstrap = readl(&scu->hwstrap); 351 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) 352 required_rate = 100 * 1000 * 1000; 353 else 354 required_rate = 25 * 1000 * 1000; 355 356 divisor = hpll_rate / required_rate; 357 358 if (divisor < 4) { 359 /* Clock can't run fast enough, but let's try anyway */ 360 debug("MAC clock too slow\n"); 361 divisor = 4; 362 } else if (divisor > 16) { 363 /* Can't slow down the clock enough, but let's try anyway */ 364 debug("MAC clock too fast\n"); 365 divisor = 16; 366 } 367 368 switch (index) { 369 case 1: 370 reset_bit = BIT(ASPEED_RESET_MAC1); 371 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 372 break; 373 case 2: 374 reset_bit = BIT(ASPEED_RESET_MAC2); 375 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, 382 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); 383 384 /* 385 * Disable MAC, start its clock and re-enable it. 386 * The procedure and the delays (100us & 10ms) are 387 * specified in the datasheet. 388 */ 389 setbits_le32(&scu->sysreset_ctrl1, reset_bit); 390 udelay(100); 391 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); 392 mdelay(10); 393 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); 394 395 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 396 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), 397 &scu->clk_duty_sel); 398 399 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); 400 writel(clk_delay_settings, &scu->mac_clk_delay_100M); 401 writel(clk_delay_settings, &scu->mac_clk_delay_10M); 402 403 return required_rate; 404 } 405 406 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) 407 { 408 /* 409 * The values and the meaning of the next three 410 * parameters are undocumented. Taken from Aspeed SDK. 411 * 412 * TODO(clg@kaod.org): the SIP and SIC values depend on the 413 * Numerator value 414 */ 415 const u32 d2_pll_ext_param = 0x2c; 416 const u32 d2_pll_sip = 0x11; 417 const u32 d2_pll_sic = 0x18; 418 struct ast2500_div_config div_cfg = { 419 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, 420 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, 421 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, 422 }; 423 ulong clkin = ast2500_get_clkin(scu); 424 ulong new_rate; 425 426 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) 427 | SCU_D2PLL_EXT1_OFF 428 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); 429 430 /* 431 * Select USB2.0 port1 PHY clock as a clock source for GCRT. 432 * This would disconnect it from D2-PLL. 433 */ 434 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, 435 SCU_MISC_GCRT_USB20CLK); 436 437 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); 438 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) 439 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) 440 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) 441 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) 442 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), 443 &scu->d2_pll_param); 444 445 clrbits_le32(&scu->d2_pll_ext_param[0], 446 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); 447 448 clrsetbits_le32(&scu->misc_ctrl2, 449 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL 450 | SCU_MISC2_RGMII_CLKDIV_MASK | 451 SCU_MISC2_RMII_CLKDIV_MASK, 452 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); 453 454 return new_rate; 455 } 456 457 static unsigned long ast2500_clk_set_rate(struct clk *clk, ulong rate) 458 { 459 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 460 461 ulong new_rate; 462 switch (clk->id) { 463 //mpll 464 case ASPEED_CLK_MPLL: 465 new_rate = ast2500_configure_ddr(priv->scu, rate); 466 // printf("ast2500_clk_set_rate mpll %ld \n", new_rate); 467 break; 468 case ASPEED_CLK_D2PLL: 469 new_rate = ast2500_configure_d2pll(priv->scu, rate); 470 // printf("ast2500_clk_set_rate d2pll ==== %ld \n", new_rate); 471 break; 472 default: 473 return -ENOENT; 474 } 475 476 return new_rate; 477 } 478 479 static int ast2500_clk_enable(struct clk *clk) 480 { 481 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 482 483 switch (clk->id) { 484 /* 485 * For MAC clocks the clock rate is 486 * configured based on whether RGMII or RMII mode has been selected 487 * through hardware strapping. 488 */ 489 case ASPEED_CLK_GATE_MAC1CLK: 490 ast2500_configure_mac(priv->scu, 1); 491 break; 492 case ASPEED_CLK_GATE_MAC2CLK: 493 ast2500_configure_mac(priv->scu, 2); 494 break; 495 case ASPEED_CLK_D2PLL: 496 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); 497 break; 498 default: 499 return -ENOENT; 500 } 501 502 return 0; 503 } 504 505 struct clk_ops ast2500_clk_ops = { 506 .get_rate = ast2500_clk_get_rate, 507 .set_rate = ast2500_clk_set_rate, 508 .enable = ast2500_clk_enable, 509 }; 510 511 static int ast2500_clk_probe(struct udevice *dev) 512 { 513 struct ast2500_clk_priv *priv = dev_get_priv(dev); 514 515 priv->scu = devfdt_get_addr_ptr(dev); 516 if (IS_ERR(priv->scu)) 517 return PTR_ERR(priv->scu); 518 519 return 0; 520 } 521 522 static int ast2500_clk_bind(struct udevice *dev) 523 { 524 int ret; 525 526 /* The reset driver does not have a device node, so bind it here */ 527 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 528 if (ret) 529 debug("Warning: No reset driver: ret=%d\n", ret); 530 531 return 0; 532 } 533 534 static const struct udevice_id ast2500_clk_ids[] = { 535 { .compatible = "aspeed,ast2500-scu" }, 536 { } 537 }; 538 539 U_BOOT_DRIVER(aspeed_scu) = { 540 .name = "aspeed_scu", 541 .id = UCLASS_CLK, 542 .of_match = ast2500_clk_ids, 543 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv), 544 .ops = &ast2500_clk_ops, 545 .bind = ast2500_clk_bind, 546 .probe = ast2500_clk_probe, 547 }; 548