1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2016 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/scu_ast2500.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/clock/ast2500-scu.h> 13 14 /* 15 * MAC Clock Delay settings, taken from Aspeed SDK 16 */ 17 #define RGMII_TXCLK_ODLY 8 18 #define RMII_RXCLK_IDLY 2 19 20 /* 21 * TGMII Clock Duty constants, taken from Aspeed SDK 22 */ 23 #define RGMII2_TXCK_DUTY 0x66 24 #define RGMII1_TXCK_DUTY 0x64 25 26 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * Clock divider/multiplier configuration struct. 32 * For H-PLL and M-PLL the formula is 33 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 34 * M - Numerator 35 * N - Denumerator 36 * P - Post Divider 37 * They have the same layout in their control register. 38 * 39 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 40 * yet needed and ignored by clock configurations. 41 */ 42 struct ast2500_div_config { 43 unsigned int num; 44 unsigned int denum; 45 unsigned int post_div; 46 }; 47 48 /* 49 * Get the rate of the M-PLL clock from input clock frequency and 50 * the value of the M-PLL Parameter Register. 51 */ 52 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) 53 { 54 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; 55 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) 56 >> SCU_MPLL_DENUM_SHIFT; 57 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) 58 >> SCU_MPLL_POST_SHIFT; 59 60 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 61 } 62 63 /* 64 * Get the rate of the H-PLL clock from input clock frequency and 65 * the value of the H-PLL Parameter Register. 66 */ 67 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) 68 { 69 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; 70 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) 71 >> SCU_HPLL_DENUM_SHIFT; 72 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) 73 >> SCU_HPLL_POST_SHIFT; 74 75 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 76 } 77 78 static ulong ast2500_get_clkin(struct ast2500_scu *scu) 79 { 80 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ 81 ? 25 * 1000 * 1000 : 24 * 1000 * 1000; 82 } 83 84 /** 85 * Get current rate or uart clock 86 * 87 * @scu SCU registers 88 * @uart_index UART index, 1-5 89 * 90 * @return current setting for uart clock rate 91 */ 92 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) 93 { 94 /* 95 * ast2500 datasheet is very confusing when it comes to UART clocks, 96 * especially when CLKIN = 25 MHz. The settings are in 97 * different registers and it is unclear how they interact. 98 * 99 * This has only been tested with default settings and CLKIN = 24 MHz. 100 */ 101 ulong uart_clkin; 102 103 if (readl(&scu->misc_ctrl2) & 104 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) 105 uart_clkin = 192 * 1000 * 1000; 106 else 107 uart_clkin = 24 * 1000 * 1000; 108 109 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) 110 uart_clkin /= 13; 111 112 return uart_clkin; 113 } 114 115 static ulong ast2500_clk_get_rate(struct clk *clk) 116 { 117 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 118 ulong clkin = ast2500_get_clkin(priv->scu); 119 ulong rate; 120 121 switch (clk->id) { 122 case PLL_HPLL: 123 case ARMCLK: 124 /* 125 * This ignores dynamic/static slowdown of ARMCLK and may 126 * be inaccurate. 127 */ 128 rate = ast2500_get_hpll_rate(clkin, 129 readl(&priv->scu->h_pll_param)); 130 break; 131 case MCLK_DDR: 132 rate = ast2500_get_mpll_rate(clkin, 133 readl(&priv->scu->m_pll_param)); 134 break; 135 case BCLK_PCLK: 136 { 137 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) 138 & SCU_PCLK_DIV_MASK) 139 >> SCU_PCLK_DIV_SHIFT); 140 rate = ast2500_get_hpll_rate(clkin, 141 readl(&priv-> 142 scu->h_pll_param)); 143 rate = rate / apb_div; 144 } 145 break; 146 case PCLK_UART1: 147 rate = ast2500_get_uart_clk_rate(priv->scu, 1); 148 break; 149 case PCLK_UART2: 150 rate = ast2500_get_uart_clk_rate(priv->scu, 2); 151 break; 152 case PCLK_UART3: 153 rate = ast2500_get_uart_clk_rate(priv->scu, 3); 154 break; 155 case PCLK_UART4: 156 rate = ast2500_get_uart_clk_rate(priv->scu, 4); 157 break; 158 case PCLK_UART5: 159 rate = ast2500_get_uart_clk_rate(priv->scu, 5); 160 break; 161 default: 162 return -ENOENT; 163 } 164 165 return rate; 166 } 167 168 struct ast2500_clock_config { 169 ulong input_rate; 170 ulong rate; 171 struct ast2500_div_config cfg; 172 }; 173 174 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { 175 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 176 }; 177 178 static bool ast2500_get_clock_config_default(ulong input_rate, 179 ulong requested_rate, 180 struct ast2500_div_config *cfg) 181 { 182 int i; 183 184 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { 185 const struct ast2500_clock_config *default_cfg = 186 &ast2500_clock_config_defaults[i]; 187 if (default_cfg->input_rate == input_rate && 188 default_cfg->rate == requested_rate) { 189 *cfg = default_cfg->cfg; 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 /* 198 * @input_rate - the rate of input clock in Hz 199 * @requested_rate - desired output rate in Hz 200 * @div - this is an IN/OUT parameter, at input all fields of the config 201 * need to be set to their maximum allowed values. 202 * The result (the best config we could find), would also be returned 203 * in this structure. 204 * 205 * @return The clock rate, when the resulting div_config is used. 206 */ 207 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, 208 struct ast2500_div_config *cfg) 209 { 210 /* 211 * The assumption is that kHz precision is good enough and 212 * also enough to avoid overflow when multiplying. 213 */ 214 const ulong input_rate_khz = input_rate / 1000; 215 const ulong rate_khz = requested_rate / 1000; 216 const struct ast2500_div_config max_vals = *cfg; 217 struct ast2500_div_config it = { 0, 0, 0 }; 218 ulong delta = rate_khz; 219 ulong new_rate_khz = 0; 220 221 /* 222 * Look for a well known frequency first. 223 */ 224 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) 225 return requested_rate; 226 227 for (; it.denum <= max_vals.denum; ++it.denum) { 228 for (it.post_div = 0; it.post_div <= max_vals.post_div; 229 ++it.post_div) { 230 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 231 * (it.denum + 1); 232 if (it.num > max_vals.num) 233 continue; 234 235 new_rate_khz = (input_rate_khz 236 * ((it.num + 1) / (it.denum + 1))) 237 / (it.post_div + 1); 238 239 /* Keep the rate below requested one. */ 240 if (new_rate_khz > rate_khz) 241 continue; 242 243 if (new_rate_khz - rate_khz < delta) { 244 delta = new_rate_khz - rate_khz; 245 *cfg = it; 246 if (delta == 0) 247 return new_rate_khz * 1000; 248 } 249 } 250 } 251 252 return new_rate_khz * 1000; 253 } 254 255 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) 256 { 257 ulong clkin = ast2500_get_clkin(scu); 258 u32 mpll_reg; 259 struct ast2500_div_config div_cfg = { 260 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 261 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 262 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 263 }; 264 265 ast2500_calc_clock_config(clkin, rate, &div_cfg); 266 267 mpll_reg = readl(&scu->m_pll_param); 268 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 269 | SCU_MPLL_DENUM_MASK); 270 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 271 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 272 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 273 274 ast_scu_unlock(scu); 275 writel(mpll_reg, &scu->m_pll_param); 276 ast_scu_lock(scu); 277 278 return ast2500_get_mpll_rate(clkin, mpll_reg); 279 } 280 281 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) 282 { 283 ulong clkin = ast2500_get_clkin(scu); 284 ulong hpll_rate = ast2500_get_hpll_rate(clkin, 285 readl(&scu->h_pll_param)); 286 ulong required_rate; 287 u32 hwstrap; 288 u32 divisor; 289 u32 reset_bit; 290 u32 clkstop_bit; 291 292 /* 293 * According to data sheet, for 10/100 mode the MAC clock frequency 294 * should be at least 25MHz and for 1000 mode at least 100MHz 295 */ 296 hwstrap = readl(&scu->hwstrap); 297 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) 298 required_rate = 100 * 1000 * 1000; 299 else 300 required_rate = 25 * 1000 * 1000; 301 302 divisor = hpll_rate / required_rate; 303 304 if (divisor < 4) { 305 /* Clock can't run fast enough, but let's try anyway */ 306 debug("MAC clock too slow\n"); 307 divisor = 4; 308 } else if (divisor > 16) { 309 /* Can't slow down the clock enough, but let's try anyway */ 310 debug("MAC clock too fast\n"); 311 divisor = 16; 312 } 313 314 switch (index) { 315 case 1: 316 reset_bit = SCU_SYSRESET_MAC1; 317 clkstop_bit = SCU_CLKSTOP_MAC1; 318 break; 319 case 2: 320 reset_bit = SCU_SYSRESET_MAC2; 321 clkstop_bit = SCU_CLKSTOP_MAC2; 322 break; 323 default: 324 return -EINVAL; 325 } 326 327 ast_scu_unlock(scu); 328 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, 329 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); 330 331 /* 332 * Disable MAC, start its clock and re-enable it. 333 * The procedure and the delays (100us & 10ms) are 334 * specified in the datasheet. 335 */ 336 setbits_le32(&scu->sysreset_ctrl1, reset_bit); 337 udelay(100); 338 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); 339 mdelay(10); 340 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); 341 342 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 343 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), 344 &scu->clk_duty_sel); 345 346 ast_scu_lock(scu); 347 348 return required_rate; 349 } 350 351 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) 352 { 353 /* 354 * The values and the meaning of the next three 355 * parameters are undocumented. Taken from Aspeed SDK. 356 * 357 * TODO(clg@kaod.org): the SIP and SIC values depend on the 358 * Numerator value 359 */ 360 const u32 d2_pll_ext_param = 0x2c; 361 const u32 d2_pll_sip = 0x11; 362 const u32 d2_pll_sic = 0x18; 363 u32 clk_delay_settings = 364 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 365 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 366 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 367 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); 368 struct ast2500_div_config div_cfg = { 369 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, 370 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, 371 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, 372 }; 373 ulong clkin = ast2500_get_clkin(scu); 374 ulong new_rate; 375 376 ast_scu_unlock(scu); 377 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) 378 | SCU_D2PLL_EXT1_OFF 379 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); 380 381 /* 382 * Select USB2.0 port1 PHY clock as a clock source for GCRT. 383 * This would disconnect it from D2-PLL. 384 */ 385 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, 386 SCU_MISC_GCRT_USB20CLK); 387 388 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); 389 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) 390 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) 391 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) 392 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) 393 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), 394 &scu->d2_pll_param); 395 396 clrbits_le32(&scu->d2_pll_ext_param[0], 397 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); 398 399 clrsetbits_le32(&scu->misc_ctrl2, 400 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL 401 | SCU_MISC2_RGMII_CLKDIV_MASK | 402 SCU_MISC2_RMII_CLKDIV_MASK, 403 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); 404 405 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); 406 writel(clk_delay_settings, &scu->mac_clk_delay_100M); 407 writel(clk_delay_settings, &scu->mac_clk_delay_10M); 408 409 ast_scu_lock(scu); 410 411 return new_rate; 412 } 413 414 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) 415 { 416 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 417 418 ulong new_rate; 419 switch (clk->id) { 420 case PLL_MPLL: 421 case MCLK_DDR: 422 new_rate = ast2500_configure_ddr(priv->scu, rate); 423 break; 424 case PLL_D2PLL: 425 new_rate = ast2500_configure_d2pll(priv->scu, rate); 426 break; 427 default: 428 return -ENOENT; 429 } 430 431 return new_rate; 432 } 433 434 static int ast2500_clk_enable(struct clk *clk) 435 { 436 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 437 438 switch (clk->id) { 439 /* 440 * For MAC clocks the clock rate is 441 * configured based on whether RGMII or RMII mode has been selected 442 * through hardware strapping. 443 */ 444 case PCLK_MAC1: 445 ast2500_configure_mac(priv->scu, 1); 446 break; 447 case PCLK_MAC2: 448 ast2500_configure_mac(priv->scu, 2); 449 break; 450 case PLL_D2PLL: 451 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); 452 break; 453 default: 454 return -ENOENT; 455 } 456 457 return 0; 458 } 459 460 struct clk_ops ast2500_clk_ops = { 461 .get_rate = ast2500_clk_get_rate, 462 .set_rate = ast2500_clk_set_rate, 463 .enable = ast2500_clk_enable, 464 }; 465 466 static int ast2500_clk_probe(struct udevice *dev) 467 { 468 struct ast2500_clk_priv *priv = dev_get_priv(dev); 469 470 priv->scu = devfdt_get_addr_ptr(dev); 471 if (IS_ERR(priv->scu)) 472 return PTR_ERR(priv->scu); 473 474 return 0; 475 } 476 477 static int ast2500_clk_bind(struct udevice *dev) 478 { 479 int ret; 480 481 /* The reset driver does not have a device node, so bind it here */ 482 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 483 if (ret) 484 debug("Warning: No reset driver: ret=%d\n", ret); 485 486 return 0; 487 } 488 489 static const struct udevice_id ast2500_clk_ids[] = { 490 { .compatible = "aspeed,ast2500-scu" }, 491 { } 492 }; 493 494 U_BOOT_DRIVER(aspeed_ast2500_scu) = { 495 .name = "aspeed_ast2500_scu", 496 .id = UCLASS_CLK, 497 .of_match = ast2500_clk_ids, 498 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv), 499 .ops = &ast2500_clk_ops, 500 .bind = ast2500_clk_bind, 501 .probe = ast2500_clk_probe, 502 }; 503