1a63e54abSMario Sixmenuconfig AXI 2a63e54abSMario Six bool "AXI bus drivers" 3a63e54abSMario Six help 4a63e54abSMario Six Support AXI (Advanced eXtensible Interface) busses, a on-chip 5a63e54abSMario Six interconnect specification for managing functional blocks in SoC 6a63e54abSMario Six designs, which is also often used in designs involving FPGAs (e.g. 7a63e54abSMario Six communication with IP cores in Xilinx FPGAs). 8a63e54abSMario Six 9a63e54abSMario Six These types of busses expose a virtual address space that can be 10a63e54abSMario Six accessed using different address widths (8, 16, and 32 are supported 11a63e54abSMario Six for now). 12a63e54abSMario Six 13a63e54abSMario Six Other similar bus architectures may be compatible as well. 14*9fc8706dSMario Six 15*9fc8706dSMario Sixif AXI 16*9fc8706dSMario Six 17*9fc8706dSMario Sixconfig IHS_AXI 18*9fc8706dSMario Six bool "Enable IHS AXI driver" 19*9fc8706dSMario Six depends on DM 20*9fc8706dSMario Six help 21*9fc8706dSMario Six Support for gdsys Integrated Hardware Systems Advanced eXtensible 22*9fc8706dSMario Six Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with 23*9fc8706dSMario Six IP cores in the FPGA (e.g. video transmitter cores). 24*9fc8706dSMario Six 25*9fc8706dSMario Sixendif 26