xref: /openbmc/u-boot/drivers/ata/sata_sil.h (revision 971a54193c9a90a6651064c4a7879e3568e9e7b8)
1  /*
2   * Copyright (C) 2011 Freescale Semiconductor, Inc.
3   * Author: Tang Yuantian <b29983@freescale.com>
4   *
5   * SPDX-License-Identifier:	GPL-2.0+
6   */
7  
8  #ifndef SATA_SIL3132_H
9  #define SATA_SIL3132_H
10  
11  #define READ_CMD	0
12  #define WRITE_CMD	1
13  
14  /*
15   * SATA device driver struct for each dev
16   */
17  struct sil_sata {
18  	char	name[12];
19  	void	*port;	/* the port base address */
20  	int		lba48;
21  	u16		pio;
22  	u16		mwdma;
23  	u16		udma;
24  	pci_dev_t devno;
25  	int		wcache;
26  	int		flush;
27  	int		flush_ext;
28  };
29  
30  /* sata info for each controller */
31  struct sata_info {
32  	ulong iobase[3];
33  	pci_dev_t devno;
34  	int portbase;
35  	int maxport;
36  };
37  
38  /*
39   * Scatter gather entry (SGE),MUST 8 bytes aligned
40   */
41  struct sil_sge {
42  	__le64 addr;
43  	__le32 cnt;
44  	__le32 flags;
45  } __attribute__ ((aligned(8), packed));
46  
47  /*
48   * Port request block, MUST 8 bytes aligned
49   */
50  struct sil_prb {
51  	__le16 ctrl;
52  	__le16 prot;
53  	__le32 rx_cnt;
54  	struct sata_fis_h2d fis;
55  } __attribute__ ((aligned(8), packed));
56  
57  struct sil_cmd_block {
58  	struct sil_prb prb;
59  	struct sil_sge sge;
60  };
61  
62  enum {
63  	HOST_SLOT_STAT		= 0x00, /* 32 bit slot stat * 4 */
64  	HOST_CTRL		= 0x40,
65  	HOST_IRQ_STAT		= 0x44,
66  	HOST_PHY_CFG		= 0x48,
67  	HOST_BIST_CTRL		= 0x50,
68  	HOST_BIST_PTRN		= 0x54,
69  	HOST_BIST_STAT		= 0x58,
70  	HOST_MEM_BIST_STAT	= 0x5c,
71  	HOST_FLASH_CMD		= 0x70,
72  		/* 8 bit regs */
73  	HOST_FLASH_DATA		= 0x74,
74  	HOST_TRANSITION_DETECT	= 0x75,
75  	HOST_GPIO_CTRL		= 0x76,
76  	HOST_I2C_ADDR		= 0x78, /* 32 bit */
77  	HOST_I2C_DATA		= 0x7c,
78  	HOST_I2C_XFER_CNT	= 0x7e,
79  	HOST_I2C_CTRL		= 0x7f,
80  
81  	/* HOST_SLOT_STAT bits */
82  	HOST_SSTAT_ATTN		= (1 << 31),
83  
84  	/* HOST_CTRL bits */
85  	HOST_CTRL_M66EN		= (1 << 16), /* M66EN PCI bus signal */
86  	HOST_CTRL_TRDY		= (1 << 17), /* latched PCI TRDY */
87  	HOST_CTRL_STOP		= (1 << 18), /* latched PCI STOP */
88  	HOST_CTRL_DEVSEL	= (1 << 19), /* latched PCI DEVSEL */
89  	HOST_CTRL_REQ64		= (1 << 20), /* latched PCI REQ64 */
90  	HOST_CTRL_GLOBAL_RST	= (1 << 31), /* global reset */
91  
92  	/*
93  	 * Port registers
94  	 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
95  	 */
96  	PORT_REGS_SIZE		= 0x2000,
97  
98  	PORT_LRAM		= 0x0000, /* 31 LRAM slots and PMP regs */
99  	PORT_LRAM_SLOT_SZ	= 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
100  
101  	PORT_PMP		= 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
102  	PORT_PMP_STATUS		= 0x0000, /* port device status offset */
103  	PORT_PMP_QACTIVE	= 0x0004, /* port device QActive offset */
104  	PORT_PMP_SIZE		= 0x0008, /* 8 bytes per PMP */
105  
106  	/* 32 bit regs */
107  	PORT_CTRL_STAT		= 0x1000, /* write: ctrl-set, read: stat */
108  	PORT_CTRL_CLR		= 0x1004, /* write: ctrl-clear */
109  	PORT_IRQ_STAT		= 0x1008, /* high: status, low: interrupt */
110  	PORT_IRQ_ENABLE_SET	= 0x1010, /* write: enable-set */
111  	PORT_IRQ_ENABLE_CLR	= 0x1014, /* write: enable-clear */
112  	PORT_ACTIVATE_UPPER_ADDR = 0x101c,
113  	PORT_EXEC_FIFO		= 0x1020, /* command execution fifo */
114  	PORT_CMD_ERR		= 0x1024, /* command error number */
115  	PORT_FIS_CFG		= 0x1028,
116  	PORT_FIFO_THRES		= 0x102c,
117  
118  	/* 16 bit regs */
119  	PORT_DECODE_ERR_CNT	= 0x1040,
120  	PORT_DECODE_ERR_THRESH	= 0x1042,
121  	PORT_CRC_ERR_CNT	= 0x1044,
122  	PORT_CRC_ERR_THRESH	= 0x1046,
123  	PORT_HSHK_ERR_CNT	= 0x1048,
124  	PORT_HSHK_ERR_THRESH	= 0x104a,
125  
126  	/* 32 bit regs */
127  	PORT_PHY_CFG		= 0x1050,
128  	PORT_SLOT_STAT		= 0x1800,
129  	PORT_CMD_ACTIVATE	= 0x1c00, /* 64 bit cmd activate * 31 */
130  	PORT_CONTEXT		= 0x1e04,
131  	PORT_EXEC_DIAG		= 0x1e00, /* 32bit exec diag * 16 */
132  	PORT_PSD_DIAG		= 0x1e40, /* 32bit psd diag * 16 */
133  	PORT_SCONTROL		= 0x1f00,
134  	PORT_SSTATUS		= 0x1f04,
135  	PORT_SERROR		= 0x1f08,
136  	PORT_SACTIVE		= 0x1f0c,
137  
138  	/* PORT_CTRL_STAT bits */
139  	PORT_CS_PORT_RST	= (1 << 0), /* port reset */
140  	PORT_CS_DEV_RST		= (1 << 1), /* device reset */
141  	PORT_CS_INIT		= (1 << 2), /* port initialize */
142  	PORT_CS_IRQ_WOC		= (1 << 3), /* interrupt write one to clear */
143  	PORT_CS_CDB16		= (1 << 5), /* 0=12b cdb, 1=16b cdb */
144  	PORT_CS_PMP_RESUME	= (1 << 6), /* PMP resume */
145  	PORT_CS_32BIT_ACTV	= (1 << 10), /* 32-bit activation */
146  	PORT_CS_PMP_EN		= (1 << 13), /* port multiplier enable */
147  	PORT_CS_RDY		= (1 << 31), /* port ready to accept commands */
148  
149  	/* PORT_IRQ_STAT/ENABLE_SET/CLR */
150  	/* bits[11:0] are masked */
151  	PORT_IRQ_COMPLETE	= (1 << 0), /* command(s) completed */
152  	PORT_IRQ_ERROR		= (1 << 1), /* command execution error */
153  	PORT_IRQ_PORTRDY_CHG	= (1 << 2), /* port ready change */
154  	PORT_IRQ_PWR_CHG	= (1 << 3), /* power management change */
155  	PORT_IRQ_PHYRDY_CHG	= (1 << 4), /* PHY ready change */
156  	PORT_IRQ_COMWAKE	= (1 << 5), /* COMWAKE received */
157  	PORT_IRQ_UNK_FIS	= (1 << 6), /* unknown FIS received */
158  	PORT_IRQ_DEV_XCHG	= (1 << 7), /* device exchanged */
159  	PORT_IRQ_8B10B		= (1 << 8), /* 8b/10b decode error threshold */
160  	PORT_IRQ_CRC		= (1 << 9), /* CRC error threshold */
161  	PORT_IRQ_HANDSHAKE	= (1 << 10), /* handshake error threshold */
162  	PORT_IRQ_SDB_NOTIFY	= (1 << 11), /* SDB notify received */
163  
164  	DEF_PORT_IRQ		= PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
165  				  PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
166  				  PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
167  
168  	/* bits[27:16] are unmasked (raw) */
169  	PORT_IRQ_RAW_SHIFT	= 16,
170  	PORT_IRQ_MASKED_MASK	= 0x7ff,
171  	PORT_IRQ_RAW_MASK	= (0x7ff << PORT_IRQ_RAW_SHIFT),
172  
173  	/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
174  	PORT_IRQ_STEER_SHIFT	= 30,
175  	PORT_IRQ_STEER_MASK	= (3 << PORT_IRQ_STEER_SHIFT),
176  
177  	/* PORT_CMD_ERR constants */
178  	PORT_CERR_DEV		= 1, /* Error bit in D2H Register FIS */
179  	PORT_CERR_SDB		= 2, /* Error bit in SDB FIS */
180  	PORT_CERR_DATA		= 3, /* Error in data FIS not detected by dev */
181  	PORT_CERR_SEND		= 4, /* Initial cmd FIS transmission failure */
182  	PORT_CERR_INCONSISTENT	= 5, /* Protocol mismatch */
183  	PORT_CERR_DIRECTION	= 6, /* Data direction mismatch */
184  	PORT_CERR_UNDERRUN	= 7, /* Ran out of SGEs while writing */
185  	PORT_CERR_OVERRUN	= 8, /* Ran out of SGEs while reading */
186  
187  	/* bits of PRB control field */
188  	PRB_CTRL_PROTOCOL	= (1 << 0), /* override def. ATA protocol */
189  	PRB_CTRL_PACKET_READ	= (1 << 4), /* PACKET cmd read */
190  	PRB_CTRL_PACKET_WRITE	= (1 << 5), /* PACKET cmd write */
191  	PRB_CTRL_NIEN		= (1 << 6), /* Mask completion irq */
192  	PRB_CTRL_SRST		= (1 << 7), /* Soft reset request (ign BSY?) */
193  
194  	/* PRB protocol field */
195  	PRB_PROT_PACKET		= (1 << 0),
196  	PRB_PROT_TCQ		= (1 << 1),
197  	PRB_PROT_NCQ		= (1 << 2),
198  	PRB_PROT_READ		= (1 << 3),
199  	PRB_PROT_WRITE		= (1 << 4),
200  	PRB_PROT_TRANSPARENT	= (1 << 5),
201  
202  	/*
203  	 * Other constants
204  	 */
205  	SGE_TRM			= (1 << 31), /* Last SGE in chain */
206  	SGE_LNK			= (1 << 30), /* linked list
207  						Points to SGT, not SGE */
208  	SGE_DRD			= (1 << 29), /* discard data read (/dev/null)
209  						data address ignored */
210  
211  	CMD_ERR		= 0x21,
212  };
213  
214  #endif
215