1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2f2105c61SSimon Glass /* 3f2105c61SSimon Glass * Copyright (C) 2011 Freescale Semiconductor, Inc. 4f2105c61SSimon Glass * Author: Tang Yuantian <b29983@freescale.com> 5f2105c61SSimon Glass */ 6f2105c61SSimon Glass 7f2105c61SSimon Glass #ifndef SATA_SIL3132_H 8f2105c61SSimon Glass #define SATA_SIL3132_H 9f2105c61SSimon Glass 10f2105c61SSimon Glass #define READ_CMD 0 11f2105c61SSimon Glass #define WRITE_CMD 1 12f2105c61SSimon Glass 13f2105c61SSimon Glass /* 14f2105c61SSimon Glass * SATA device driver struct for each dev 15f2105c61SSimon Glass */ 16f2105c61SSimon Glass struct sil_sata { 17f2105c61SSimon Glass char name[12]; 18f2105c61SSimon Glass void *port; /* the port base address */ 19f2105c61SSimon Glass int lba48; 20f2105c61SSimon Glass u16 pio; 21f2105c61SSimon Glass u16 mwdma; 22f2105c61SSimon Glass u16 udma; 23f2105c61SSimon Glass pci_dev_t devno; 24f2105c61SSimon Glass int wcache; 25f2105c61SSimon Glass int flush; 26f2105c61SSimon Glass int flush_ext; 27f2105c61SSimon Glass }; 28f2105c61SSimon Glass 29f2105c61SSimon Glass /* sata info for each controller */ 30f2105c61SSimon Glass struct sata_info { 31f2105c61SSimon Glass ulong iobase[3]; 32f2105c61SSimon Glass pci_dev_t devno; 33f2105c61SSimon Glass int portbase; 34f2105c61SSimon Glass int maxport; 35f2105c61SSimon Glass }; 36f2105c61SSimon Glass 37f2105c61SSimon Glass /* 38f2105c61SSimon Glass * Scatter gather entry (SGE),MUST 8 bytes aligned 39f2105c61SSimon Glass */ 40f2105c61SSimon Glass struct sil_sge { 41f2105c61SSimon Glass __le64 addr; 42f2105c61SSimon Glass __le32 cnt; 43f2105c61SSimon Glass __le32 flags; 44f2105c61SSimon Glass } __attribute__ ((aligned(8), packed)); 45f2105c61SSimon Glass 46f2105c61SSimon Glass /* 47f2105c61SSimon Glass * Port request block, MUST 8 bytes aligned 48f2105c61SSimon Glass */ 49f2105c61SSimon Glass struct sil_prb { 50f2105c61SSimon Glass __le16 ctrl; 51f2105c61SSimon Glass __le16 prot; 52f2105c61SSimon Glass __le32 rx_cnt; 53f2105c61SSimon Glass struct sata_fis_h2d fis; 54f2105c61SSimon Glass } __attribute__ ((aligned(8), packed)); 55f2105c61SSimon Glass 56f2105c61SSimon Glass struct sil_cmd_block { 57f2105c61SSimon Glass struct sil_prb prb; 58f2105c61SSimon Glass struct sil_sge sge; 59f2105c61SSimon Glass }; 60f2105c61SSimon Glass 61f2105c61SSimon Glass enum { 62f2105c61SSimon Glass HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 63f2105c61SSimon Glass HOST_CTRL = 0x40, 64f2105c61SSimon Glass HOST_IRQ_STAT = 0x44, 65f2105c61SSimon Glass HOST_PHY_CFG = 0x48, 66f2105c61SSimon Glass HOST_BIST_CTRL = 0x50, 67f2105c61SSimon Glass HOST_BIST_PTRN = 0x54, 68f2105c61SSimon Glass HOST_BIST_STAT = 0x58, 69f2105c61SSimon Glass HOST_MEM_BIST_STAT = 0x5c, 70f2105c61SSimon Glass HOST_FLASH_CMD = 0x70, 71f2105c61SSimon Glass /* 8 bit regs */ 72f2105c61SSimon Glass HOST_FLASH_DATA = 0x74, 73f2105c61SSimon Glass HOST_TRANSITION_DETECT = 0x75, 74f2105c61SSimon Glass HOST_GPIO_CTRL = 0x76, 75f2105c61SSimon Glass HOST_I2C_ADDR = 0x78, /* 32 bit */ 76f2105c61SSimon Glass HOST_I2C_DATA = 0x7c, 77f2105c61SSimon Glass HOST_I2C_XFER_CNT = 0x7e, 78f2105c61SSimon Glass HOST_I2C_CTRL = 0x7f, 79f2105c61SSimon Glass 80f2105c61SSimon Glass /* HOST_SLOT_STAT bits */ 81f2105c61SSimon Glass HOST_SSTAT_ATTN = (1 << 31), 82f2105c61SSimon Glass 83f2105c61SSimon Glass /* HOST_CTRL bits */ 84f2105c61SSimon Glass HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 85f2105c61SSimon Glass HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 86f2105c61SSimon Glass HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 87f2105c61SSimon Glass HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 88f2105c61SSimon Glass HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 89f2105c61SSimon Glass HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 90f2105c61SSimon Glass 91f2105c61SSimon Glass /* 92f2105c61SSimon Glass * Port registers 93f2105c61SSimon Glass * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 94f2105c61SSimon Glass */ 95f2105c61SSimon Glass PORT_REGS_SIZE = 0x2000, 96f2105c61SSimon Glass 97f2105c61SSimon Glass PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 98f2105c61SSimon Glass PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 99f2105c61SSimon Glass 100f2105c61SSimon Glass PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 101f2105c61SSimon Glass PORT_PMP_STATUS = 0x0000, /* port device status offset */ 102f2105c61SSimon Glass PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 103f2105c61SSimon Glass PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 104f2105c61SSimon Glass 105f2105c61SSimon Glass /* 32 bit regs */ 106f2105c61SSimon Glass PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 107f2105c61SSimon Glass PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 108f2105c61SSimon Glass PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 109f2105c61SSimon Glass PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 110f2105c61SSimon Glass PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 111f2105c61SSimon Glass PORT_ACTIVATE_UPPER_ADDR = 0x101c, 112f2105c61SSimon Glass PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 113f2105c61SSimon Glass PORT_CMD_ERR = 0x1024, /* command error number */ 114f2105c61SSimon Glass PORT_FIS_CFG = 0x1028, 115f2105c61SSimon Glass PORT_FIFO_THRES = 0x102c, 116f2105c61SSimon Glass 117f2105c61SSimon Glass /* 16 bit regs */ 118f2105c61SSimon Glass PORT_DECODE_ERR_CNT = 0x1040, 119f2105c61SSimon Glass PORT_DECODE_ERR_THRESH = 0x1042, 120f2105c61SSimon Glass PORT_CRC_ERR_CNT = 0x1044, 121f2105c61SSimon Glass PORT_CRC_ERR_THRESH = 0x1046, 122f2105c61SSimon Glass PORT_HSHK_ERR_CNT = 0x1048, 123f2105c61SSimon Glass PORT_HSHK_ERR_THRESH = 0x104a, 124f2105c61SSimon Glass 125f2105c61SSimon Glass /* 32 bit regs */ 126f2105c61SSimon Glass PORT_PHY_CFG = 0x1050, 127f2105c61SSimon Glass PORT_SLOT_STAT = 0x1800, 128f2105c61SSimon Glass PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */ 129f2105c61SSimon Glass PORT_CONTEXT = 0x1e04, 130f2105c61SSimon Glass PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */ 131f2105c61SSimon Glass PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */ 132f2105c61SSimon Glass PORT_SCONTROL = 0x1f00, 133f2105c61SSimon Glass PORT_SSTATUS = 0x1f04, 134f2105c61SSimon Glass PORT_SERROR = 0x1f08, 135f2105c61SSimon Glass PORT_SACTIVE = 0x1f0c, 136f2105c61SSimon Glass 137f2105c61SSimon Glass /* PORT_CTRL_STAT bits */ 138f2105c61SSimon Glass PORT_CS_PORT_RST = (1 << 0), /* port reset */ 139f2105c61SSimon Glass PORT_CS_DEV_RST = (1 << 1), /* device reset */ 140f2105c61SSimon Glass PORT_CS_INIT = (1 << 2), /* port initialize */ 141f2105c61SSimon Glass PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 142f2105c61SSimon Glass PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 143f2105c61SSimon Glass PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 144f2105c61SSimon Glass PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 145f2105c61SSimon Glass PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 146f2105c61SSimon Glass PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 147f2105c61SSimon Glass 148f2105c61SSimon Glass /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 149f2105c61SSimon Glass /* bits[11:0] are masked */ 150f2105c61SSimon Glass PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 151f2105c61SSimon Glass PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 152f2105c61SSimon Glass PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 153f2105c61SSimon Glass PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 154f2105c61SSimon Glass PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 155f2105c61SSimon Glass PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 156f2105c61SSimon Glass PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 157f2105c61SSimon Glass PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 158f2105c61SSimon Glass PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 159f2105c61SSimon Glass PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 160f2105c61SSimon Glass PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 161f2105c61SSimon Glass PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 162f2105c61SSimon Glass 163f2105c61SSimon Glass DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 164f2105c61SSimon Glass PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 165f2105c61SSimon Glass PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, 166f2105c61SSimon Glass 167f2105c61SSimon Glass /* bits[27:16] are unmasked (raw) */ 168f2105c61SSimon Glass PORT_IRQ_RAW_SHIFT = 16, 169f2105c61SSimon Glass PORT_IRQ_MASKED_MASK = 0x7ff, 170f2105c61SSimon Glass PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 171f2105c61SSimon Glass 172f2105c61SSimon Glass /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 173f2105c61SSimon Glass PORT_IRQ_STEER_SHIFT = 30, 174f2105c61SSimon Glass PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 175f2105c61SSimon Glass 176f2105c61SSimon Glass /* PORT_CMD_ERR constants */ 177f2105c61SSimon Glass PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 178f2105c61SSimon Glass PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 179f2105c61SSimon Glass PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 180f2105c61SSimon Glass PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 181f2105c61SSimon Glass PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 182f2105c61SSimon Glass PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 183f2105c61SSimon Glass PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 184f2105c61SSimon Glass PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 185f2105c61SSimon Glass 186f2105c61SSimon Glass /* bits of PRB control field */ 187f2105c61SSimon Glass PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 188f2105c61SSimon Glass PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 189f2105c61SSimon Glass PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 190f2105c61SSimon Glass PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 191f2105c61SSimon Glass PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 192f2105c61SSimon Glass 193f2105c61SSimon Glass /* PRB protocol field */ 194f2105c61SSimon Glass PRB_PROT_PACKET = (1 << 0), 195f2105c61SSimon Glass PRB_PROT_TCQ = (1 << 1), 196f2105c61SSimon Glass PRB_PROT_NCQ = (1 << 2), 197f2105c61SSimon Glass PRB_PROT_READ = (1 << 3), 198f2105c61SSimon Glass PRB_PROT_WRITE = (1 << 4), 199f2105c61SSimon Glass PRB_PROT_TRANSPARENT = (1 << 5), 200f2105c61SSimon Glass 201f2105c61SSimon Glass /* 202f2105c61SSimon Glass * Other constants 203f2105c61SSimon Glass */ 204f2105c61SSimon Glass SGE_TRM = (1 << 31), /* Last SGE in chain */ 205f2105c61SSimon Glass SGE_LNK = (1 << 30), /* linked list 206f2105c61SSimon Glass Points to SGT, not SGE */ 207f2105c61SSimon Glass SGE_DRD = (1 << 29), /* discard data read (/dev/null) 208f2105c61SSimon Glass data address ignored */ 209f2105c61SSimon Glass 210f2105c61SSimon Glass CMD_ERR = 0x21, 211f2105c61SSimon Glass }; 212f2105c61SSimon Glass 213f2105c61SSimon Glass #endif 214