1 /* 2 * Copyright (C) Excito Elektronik i Skåne AB, 2010. 3 * Author: Tor Krill <tor@excito.com> 4 * 5 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * This driver supports the SATA controller of some Mavell SoC's. 12 * Here a (most likely incomplete) list of the supported SoC's: 13 * - Kirkwood 14 * - Armada 370 15 * - Armada XP 16 * 17 * This driver implementation is an alternative to the already available 18 * driver via the "ide" commands interface (drivers/block/mvsata_ide.c). 19 * But this driver only supports PIO mode and as this new driver also 20 * supports transfer via DMA, its much faster. 21 * 22 * Please note, that the newer SoC's (e.g. Armada 38x) are not supported 23 * by this driver. As they have an AHCI compatible SATA controller 24 * integrated. 25 */ 26 27 /* 28 * TODO: 29 * Better error recovery 30 * No support for using PRDs (Thus max 64KB transfers) 31 * No NCQ support 32 * No port multiplier support 33 */ 34 35 #include <common.h> 36 #include <fis.h> 37 #include <libata.h> 38 #include <malloc.h> 39 #include <sata.h> 40 #include <linux/errno.h> 41 #include <asm/io.h> 42 #include <linux/mbus.h> 43 44 #if defined(CONFIG_KIRKWOOD) 45 #include <asm/arch/kirkwood.h> 46 #define SATAHC_BASE KW_SATA_BASE 47 #else 48 #include <asm/arch/soc.h> 49 #define SATAHC_BASE MVEBU_AXP_SATA_BASE 50 #endif 51 52 #define SATA0_BASE (SATAHC_BASE + 0x2000) 53 #define SATA1_BASE (SATAHC_BASE + 0x4000) 54 55 /* EDMA registers */ 56 #define EDMA_CFG 0x000 57 #define EDMA_CFG_NCQ (1 << 5) 58 #define EDMA_CFG_EQUE (1 << 9) 59 #define EDMA_TIMER 0x004 60 #define EDMA_IECR 0x008 61 #define EDMA_IEMR 0x00c 62 #define EDMA_RQBA_HI 0x010 63 #define EDMA_RQIPR 0x014 64 #define EDMA_RQIPR_IPMASK (0x1f << 5) 65 #define EDMA_RQIPR_IPSHIFT 5 66 #define EDMA_RQOPR 0x018 67 #define EDMA_RQOPR_OPMASK (0x1f << 5) 68 #define EDMA_RQOPR_OPSHIFT 5 69 #define EDMA_RSBA_HI 0x01c 70 #define EDMA_RSIPR 0x020 71 #define EDMA_RSIPR_IPMASK (0x1f << 3) 72 #define EDMA_RSIPR_IPSHIFT 3 73 #define EDMA_RSOPR 0x024 74 #define EDMA_RSOPR_OPMASK (0x1f << 3) 75 #define EDMA_RSOPR_OPSHIFT 3 76 #define EDMA_CMD 0x028 77 #define EDMA_CMD_ENEDMA (0x01 << 0) 78 #define EDMA_CMD_DISEDMA (0x01 << 1) 79 #define EDMA_CMD_ATARST (0x01 << 2) 80 #define EDMA_CMD_FREEZE (0x01 << 4) 81 #define EDMA_TEST_CTL 0x02c 82 #define EDMA_STATUS 0x030 83 #define EDMA_IORTO 0x034 84 #define EDMA_CDTR 0x040 85 #define EDMA_HLTCND 0x060 86 #define EDMA_NTSR 0x094 87 88 /* Basic DMA registers */ 89 #define BDMA_CMD 0x224 90 #define BDMA_STATUS 0x228 91 #define BDMA_DTLB 0x22c 92 #define BDMA_DTHB 0x230 93 #define BDMA_DRL 0x234 94 #define BDMA_DRH 0x238 95 96 /* SATA Interface registers */ 97 #define SIR_ICFG 0x050 98 #define SIR_CFG_GEN2EN (0x1 << 7) 99 #define SIR_PLL_CFG 0x054 100 #define SIR_SSTATUS 0x300 101 #define SSTATUS_DET_MASK (0x0f << 0) 102 #define SIR_SERROR 0x304 103 #define SIR_SCONTROL 0x308 104 #define SIR_SCONTROL_DETEN (0x01 << 0) 105 #define SIR_LTMODE 0x30c 106 #define SIR_LTMODE_NELBE (0x01 << 7) 107 #define SIR_PHYMODE3 0x310 108 #define SIR_PHYMODE4 0x314 109 #define SIR_PHYMODE1 0x32c 110 #define SIR_PHYMODE2 0x330 111 #define SIR_BIST_CTRL 0x334 112 #define SIR_BIST_DW1 0x338 113 #define SIR_BIST_DW2 0x33c 114 #define SIR_SERR_IRQ_MASK 0x340 115 #define SIR_SATA_IFCTRL 0x344 116 #define SIR_SATA_TESTCTRL 0x348 117 #define SIR_SATA_IFSTATUS 0x34c 118 #define SIR_VEND_UNIQ 0x35c 119 #define SIR_FIS_CFG 0x360 120 #define SIR_FIS_IRQ_CAUSE 0x364 121 #define SIR_FIS_IRQ_MASK 0x368 122 #define SIR_FIS_DWORD0 0x370 123 #define SIR_FIS_DWORD1 0x374 124 #define SIR_FIS_DWORD2 0x378 125 #define SIR_FIS_DWORD3 0x37c 126 #define SIR_FIS_DWORD4 0x380 127 #define SIR_FIS_DWORD5 0x384 128 #define SIR_FIS_DWORD6 0x388 129 #define SIR_PHYM9_GEN2 0x398 130 #define SIR_PHYM9_GEN1 0x39c 131 #define SIR_PHY_CFG 0x3a0 132 #define SIR_PHYCTL 0x3a4 133 #define SIR_PHYM10 0x3a8 134 #define SIR_PHYM12 0x3b0 135 136 /* Shadow registers */ 137 #define PIO_DATA 0x100 138 #define PIO_ERR_FEATURES 0x104 139 #define PIO_SECTOR_COUNT 0x108 140 #define PIO_LBA_LOW 0x10c 141 #define PIO_LBA_MID 0x110 142 #define PIO_LBA_HI 0x114 143 #define PIO_DEVICE 0x118 144 #define PIO_CMD_STATUS 0x11c 145 #define PIO_STATUS_ERR (0x01 << 0) 146 #define PIO_STATUS_DRQ (0x01 << 3) 147 #define PIO_STATUS_DF (0x01 << 5) 148 #define PIO_STATUS_DRDY (0x01 << 6) 149 #define PIO_STATUS_BSY (0x01 << 7) 150 #define PIO_CTRL_ALTSTAT 0x120 151 152 /* SATAHC arbiter registers */ 153 #define SATAHC_CFG 0x000 154 #define SATAHC_RQOP 0x004 155 #define SATAHC_RQIP 0x008 156 #define SATAHC_ICT 0x00c 157 #define SATAHC_ITT 0x010 158 #define SATAHC_ICR 0x014 159 #define SATAHC_ICR_PORT0 (0x01 << 0) 160 #define SATAHC_ICR_PORT1 (0x01 << 1) 161 #define SATAHC_MIC 0x020 162 #define SATAHC_MIM 0x024 163 #define SATAHC_LED_CFG 0x02c 164 165 #define REQUEST_QUEUE_SIZE 32 166 #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE 167 168 struct crqb { 169 u32 dtb_low; /* DW0 */ 170 u32 dtb_high; /* DW1 */ 171 u32 control_flags; /* DW2 */ 172 u32 drb_count; /* DW3 */ 173 u32 ata_cmd_feat; /* DW4 */ 174 u32 ata_addr; /* DW5 */ 175 u32 ata_addr_exp; /* DW6 */ 176 u32 ata_sect_count; /* DW7 */ 177 }; 178 179 #define CRQB_ALIGN 0x400 180 181 #define CRQB_CNTRLFLAGS_DIR (0x01 << 0) 182 #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1) 183 #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1 184 #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12) 185 #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12 186 #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16) 187 #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17) 188 #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17 189 190 #define CRQB_CMDFEAT_CMDMASK (0xff << 16) 191 #define CRQB_CMDFEAT_CMDSHIFT 16 192 #define CRQB_CMDFEAT_FEATMASK (0xff << 16) 193 #define CRQB_CMDFEAT_FEATSHIFT 24 194 195 #define CRQB_ADDR_LBA_LOWMASK (0xff << 0) 196 #define CRQB_ADDR_LBA_LOWSHIFT 0 197 #define CRQB_ADDR_LBA_MIDMASK (0xff << 8) 198 #define CRQB_ADDR_LBA_MIDSHIFT 8 199 #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16) 200 #define CRQB_ADDR_LBA_HIGHSHIFT 16 201 #define CRQB_ADDR_DEVICE_MASK (0xff << 24) 202 #define CRQB_ADDR_DEVICE_SHIFT 24 203 204 #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0) 205 #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0 206 #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8) 207 #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8 208 #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16) 209 #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16 210 #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24) 211 #define CRQB_ADDR_FEATURE_EXP_SHIFT 24 212 213 #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0) 214 #define CRQB_SECTCOUNT_COUNT_SHIFT 0 215 #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8) 216 #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8 217 218 #define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) 219 #define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) 220 221 struct eprd { 222 u32 phyaddr_low; 223 u32 bytecount_eot; 224 u32 phyaddr_hi; 225 u32 reserved; 226 }; 227 228 #define EPRD_PHYADDR_MASK 0xfffffffe 229 #define EPRD_BYTECOUNT_MASK 0x0000ffff 230 #define EPRD_EOT (0x01 << 31) 231 232 struct crpb { 233 u32 id; 234 u32 flags; 235 u32 timestamp; 236 }; 237 238 #define CRPB_ALIGN 0x100 239 240 #define READ_CMD 0 241 #define WRITE_CMD 1 242 243 /* 244 * Since we don't use PRDs yet max transfer size 245 * is 64KB 246 */ 247 #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE) 248 249 /* Keep track if hw is initialized or not */ 250 static u32 hw_init; 251 252 struct mv_priv { 253 char name[12]; 254 u32 link; 255 u32 regbase; 256 u32 queue_depth; 257 u16 pio; 258 u16 mwdma; 259 u16 udma; 260 261 void *crqb_alloc; 262 struct crqb *request; 263 264 void *crpb_alloc; 265 struct crpb *response; 266 }; 267 268 static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec) 269 { 270 ulong start; 271 272 start = get_timer(0); 273 do { 274 if ((in_le32(addr) & mask) == val) 275 return 0; 276 } while (get_timer(start) < timeout_msec); 277 278 return -ETIMEDOUT; 279 } 280 281 /* Cut from sata_mv in linux kernel */ 282 static int mv_stop_edma_engine(int port) 283 { 284 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 285 int i; 286 287 /* Disable eDMA. The disable bit auto clears. */ 288 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA); 289 290 /* Wait for the chip to confirm eDMA is off. */ 291 for (i = 10000; i > 0; i--) { 292 u32 reg = in_le32(priv->regbase + EDMA_CMD); 293 if (!(reg & EDMA_CMD_ENEDMA)) { 294 debug("EDMA stop on port %d succesful\n", port); 295 return 0; 296 } 297 udelay(10); 298 } 299 debug("EDMA stop on port %d failed\n", port); 300 return -1; 301 } 302 303 static int mv_start_edma_engine(int port) 304 { 305 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 306 u32 tmp; 307 308 /* Check preconditions */ 309 tmp = in_le32(priv->regbase + SIR_SSTATUS); 310 if ((tmp & SSTATUS_DET_MASK) != 0x03) { 311 printf("Device error on port: %d\n", port); 312 return -1; 313 } 314 315 tmp = in_le32(priv->regbase + PIO_CMD_STATUS); 316 if (tmp & (ATA_BUSY | ATA_DRQ)) { 317 printf("Device not ready on port: %d\n", port); 318 return -1; 319 } 320 321 /* Clear interrupt cause */ 322 out_le32(priv->regbase + EDMA_IECR, 0x0); 323 324 tmp = in_le32(SATAHC_BASE + SATAHC_ICR); 325 tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1); 326 out_le32(SATAHC_BASE + SATAHC_ICR, tmp); 327 328 /* Configure edma operation */ 329 tmp = in_le32(priv->regbase + EDMA_CFG); 330 tmp &= ~EDMA_CFG_NCQ; /* No NCQ */ 331 tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */ 332 out_le32(priv->regbase + EDMA_CFG, tmp); 333 334 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0); 335 336 /* Configure fis, set all to no-wait for now */ 337 out_le32(priv->regbase + SIR_FIS_CFG, 0x0); 338 339 /* Setup request queue */ 340 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0); 341 out_le32(priv->regbase + EDMA_RQIPR, priv->request); 342 out_le32(priv->regbase + EDMA_RQOPR, 0x0); 343 344 /* Setup response queue */ 345 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0); 346 out_le32(priv->regbase + EDMA_RSOPR, priv->response); 347 out_le32(priv->regbase + EDMA_RSIPR, 0x0); 348 349 /* Start edma */ 350 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA); 351 352 return 0; 353 } 354 355 static int mv_reset_channel(int port) 356 { 357 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 358 359 /* Make sure edma is stopped */ 360 mv_stop_edma_engine(port); 361 362 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST); 363 udelay(25); /* allow reset propagation */ 364 out_le32(priv->regbase + EDMA_CMD, 0); 365 mdelay(10); 366 367 return 0; 368 } 369 370 static void mv_reset_port(int port) 371 { 372 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 373 374 mv_reset_channel(port); 375 376 out_le32(priv->regbase + EDMA_CMD, 0x0); 377 out_le32(priv->regbase + EDMA_CFG, 0x101f); 378 out_le32(priv->regbase + EDMA_IECR, 0x0); 379 out_le32(priv->regbase + EDMA_IEMR, 0x0); 380 out_le32(priv->regbase + EDMA_RQBA_HI, 0x0); 381 out_le32(priv->regbase + EDMA_RQIPR, 0x0); 382 out_le32(priv->regbase + EDMA_RQOPR, 0x0); 383 out_le32(priv->regbase + EDMA_RSBA_HI, 0x0); 384 out_le32(priv->regbase + EDMA_RSIPR, 0x0); 385 out_le32(priv->regbase + EDMA_RSOPR, 0x0); 386 out_le32(priv->regbase + EDMA_IORTO, 0xfa); 387 } 388 389 static void mv_reset_one_hc(void) 390 { 391 out_le32(SATAHC_BASE + SATAHC_ICT, 0x00); 392 out_le32(SATAHC_BASE + SATAHC_ITT, 0x00); 393 out_le32(SATAHC_BASE + SATAHC_ICR, 0x00); 394 } 395 396 static int probe_port(int port) 397 { 398 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 399 int tries, tries2, set15 = 0; 400 u32 tmp; 401 402 debug("Probe port: %d\n", port); 403 404 for (tries = 0; tries < 2; tries++) { 405 /* Clear SError */ 406 out_le32(priv->regbase + SIR_SERROR, 0x0); 407 408 /* trigger com-init */ 409 tmp = in_le32(priv->regbase + SIR_SCONTROL); 410 tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN; 411 out_le32(priv->regbase + SIR_SCONTROL, tmp); 412 413 mdelay(1); 414 415 tmp = in_le32(priv->regbase + SIR_SCONTROL); 416 tries2 = 5; 417 do { 418 tmp = (tmp & 0x0f0) | 0x300; 419 out_le32(priv->regbase + SIR_SCONTROL, tmp); 420 mdelay(10); 421 tmp = in_le32(priv->regbase + SIR_SCONTROL); 422 } while ((tmp & 0xf0f) != 0x300 && tries2--); 423 424 mdelay(10); 425 426 for (tries2 = 0; tries2 < 200; tries2++) { 427 tmp = in_le32(priv->regbase + SIR_SSTATUS); 428 if ((tmp & SSTATUS_DET_MASK) == 0x03) { 429 debug("Found device on port\n"); 430 return 0; 431 } 432 mdelay(1); 433 } 434 435 if ((tmp & SSTATUS_DET_MASK) == 0) { 436 debug("No device attached on port %d\n", port); 437 return -ENODEV; 438 } 439 440 if (!set15) { 441 /* Try on 1.5Gb/S */ 442 debug("Try 1.5Gb link\n"); 443 set15 = 1; 444 out_le32(priv->regbase + SIR_SCONTROL, 0x304); 445 446 tmp = in_le32(priv->regbase + SIR_ICFG); 447 tmp &= ~SIR_CFG_GEN2EN; 448 out_le32(priv->regbase + SIR_ICFG, tmp); 449 450 mv_reset_channel(port); 451 } 452 } 453 454 debug("Failed to probe port\n"); 455 return -1; 456 } 457 458 /* Get request queue in pointer */ 459 static int get_reqip(int port) 460 { 461 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 462 u32 tmp; 463 464 tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK; 465 tmp = tmp >> EDMA_RQIPR_IPSHIFT; 466 467 return tmp; 468 } 469 470 static void set_reqip(int port, int reqin) 471 { 472 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 473 u32 tmp; 474 475 tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK; 476 tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK); 477 out_le32(priv->regbase + EDMA_RQIPR, tmp); 478 } 479 480 /* Get next available slot, ignoring possible overwrite */ 481 static int get_next_reqip(int port) 482 { 483 int slot = get_reqip(port); 484 slot = (slot + 1) % REQUEST_QUEUE_SIZE; 485 return slot; 486 } 487 488 /* Get response queue in pointer */ 489 static int get_rspip(int port) 490 { 491 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 492 u32 tmp; 493 494 tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK; 495 tmp = tmp >> EDMA_RSIPR_IPSHIFT; 496 497 return tmp; 498 } 499 500 /* Get response queue out pointer */ 501 static int get_rspop(int port) 502 { 503 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 504 u32 tmp; 505 506 tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK; 507 tmp = tmp >> EDMA_RSOPR_OPSHIFT; 508 return tmp; 509 } 510 511 /* Get next response queue pointer */ 512 static int get_next_rspop(int port) 513 { 514 return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE; 515 } 516 517 /* Set response queue pointer */ 518 static void set_rspop(int port, int reqin) 519 { 520 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 521 u32 tmp; 522 523 tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK; 524 tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK); 525 526 out_le32(priv->regbase + EDMA_RSOPR, tmp); 527 } 528 529 static int wait_dma_completion(int port, int index, u32 timeout_msec) 530 { 531 u32 tmp, res; 532 533 tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1; 534 res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp, 535 tmp, timeout_msec); 536 if (res) 537 printf("Failed to wait for completion on port %d\n", port); 538 539 return res; 540 } 541 542 static void process_responses(int port) 543 { 544 #ifdef DEBUG 545 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 546 #endif 547 u32 tmp; 548 u32 outind = get_rspop(port); 549 550 /* Ack interrupts */ 551 tmp = in_le32(SATAHC_BASE + SATAHC_ICR); 552 if (port == 0) 553 tmp &= ~(BIT(0) | BIT(8)); 554 else 555 tmp &= ~(BIT(1) | BIT(9)); 556 tmp &= ~(BIT(4)); 557 out_le32(SATAHC_BASE + SATAHC_ICR, tmp); 558 559 while (get_rspip(port) != outind) { 560 #ifdef DEBUG 561 debug("Response index %d flags %08x on port %d\n", outind, 562 priv->response[outind].flags, port); 563 #endif 564 outind = get_next_rspop(port); 565 set_rspop(port, outind); 566 } 567 } 568 569 static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis, 570 u8 *buffer, u32 len, u32 iswrite) 571 { 572 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 573 struct crqb *req; 574 int slot; 575 u32 start; 576 577 if (len >= 64 * 1024) { 578 printf("We only support <64K transfers for now\n"); 579 return -1; 580 } 581 582 /* Initialize request */ 583 slot = get_reqip(port); 584 memset(&priv->request[slot], 0, sizeof(struct crqb)); 585 req = &priv->request[slot]; 586 587 req->dtb_low = (u32)buffer; 588 589 /* Dont use PRDs */ 590 req->control_flags = CRQB_CNTRLFLAGS_PRDMODE; 591 req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR; 592 req->control_flags |= 593 ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT) 594 & CRQB_CNTRLFLAGS_PMPORTMASK); 595 596 req->drb_count = len; 597 598 req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) & 599 CRQB_CMDFEAT_CMDMASK; 600 req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) & 601 CRQB_CMDFEAT_FEATMASK; 602 603 req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) & 604 CRQB_ADDR_LBA_LOWMASK; 605 req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) & 606 CRQB_ADDR_LBA_MIDMASK; 607 req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) & 608 CRQB_ADDR_LBA_HIGHMASK; 609 req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) & 610 CRQB_ADDR_DEVICE_MASK; 611 612 req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) & 613 CRQB_ADDR_LBA_LOW_EXP_MASK; 614 req->ata_addr_exp |= 615 (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) & 616 CRQB_ADDR_LBA_MID_EXP_MASK; 617 req->ata_addr_exp |= 618 (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) & 619 CRQB_ADDR_LBA_HIGH_EXP_MASK; 620 req->ata_addr_exp |= 621 (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) & 622 CRQB_ADDR_FEATURE_EXP_MASK; 623 624 req->ata_sect_count = 625 (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) & 626 CRQB_SECTCOUNT_COUNT_MASK; 627 req->ata_sect_count |= 628 (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) & 629 CRQB_SECTCOUNT_COUNT_EXP_MASK; 630 631 /* Flush data */ 632 start = (u32)req & ~(ARCH_DMA_MINALIGN - 1); 633 flush_dcache_range(start, 634 start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN)); 635 636 /* Trigger operation */ 637 slot = get_next_reqip(port); 638 set_reqip(port, slot); 639 640 /* Wait for completion */ 641 if (wait_dma_completion(port, slot, 10000)) { 642 printf("ATA operation timed out\n"); 643 return -1; 644 } 645 646 process_responses(port); 647 648 /* Invalidate data on read */ 649 if (buffer && len) { 650 start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1); 651 invalidate_dcache_range(start, 652 start + ALIGN(len, ARCH_DMA_MINALIGN)); 653 } 654 655 return len; 656 } 657 658 static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt, 659 u8 *buffer, int is_write) 660 { 661 struct sata_fis_h2d cfis; 662 u32 res; 663 u64 block; 664 665 block = (u64)start; 666 667 memset(&cfis, 0, sizeof(struct sata_fis_h2d)); 668 669 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; 670 cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 671 672 cfis.lba_high_exp = (block >> 40) & 0xff; 673 cfis.lba_mid_exp = (block >> 32) & 0xff; 674 cfis.lba_low_exp = (block >> 24) & 0xff; 675 cfis.lba_high = (block >> 16) & 0xff; 676 cfis.lba_mid = (block >> 8) & 0xff; 677 cfis.lba_low = block & 0xff; 678 cfis.device = ATA_LBA; 679 cfis.sector_count_exp = (blkcnt >> 8) & 0xff; 680 cfis.sector_count = blkcnt & 0xff; 681 682 res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt, 683 is_write); 684 685 return res >= 0 ? blkcnt : res; 686 } 687 688 static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer, 689 int is_write) 690 { 691 struct sata_fis_h2d cfis; 692 lbaint_t block; 693 u32 res; 694 695 block = start; 696 697 memset(&cfis, 0, sizeof(struct sata_fis_h2d)); 698 699 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; 700 cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 701 cfis.device = ATA_LBA; 702 703 cfis.device |= (block >> 24) & 0xf; 704 cfis.lba_high = (block >> 16) & 0xff; 705 cfis.lba_mid = (block >> 8) & 0xff; 706 cfis.lba_low = block & 0xff; 707 cfis.sector_count = (u8)(blkcnt & 0xff); 708 709 res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt, 710 is_write); 711 712 return res >= 0 ? blkcnt : res; 713 } 714 715 static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt, 716 void *buffer, int is_write) 717 { 718 lbaint_t start, blks; 719 u8 *addr; 720 int max_blks; 721 722 debug("%s: %ld %ld\n", __func__, blknr, blkcnt); 723 724 start = blknr; 725 blks = blkcnt; 726 addr = (u8 *)buffer; 727 728 max_blks = MV_ATA_MAX_SECTORS; 729 do { 730 if (blks > max_blks) { 731 if (sata_dev_desc[dev].lba48) { 732 mv_sata_rw_cmd_ext(dev, start, max_blks, addr, 733 is_write); 734 } else { 735 mv_sata_rw_cmd(dev, start, max_blks, addr, 736 is_write); 737 } 738 start += max_blks; 739 blks -= max_blks; 740 addr += ATA_SECT_SIZE * max_blks; 741 } else { 742 if (sata_dev_desc[dev].lba48) { 743 mv_sata_rw_cmd_ext(dev, start, blks, addr, 744 is_write); 745 } else { 746 mv_sata_rw_cmd(dev, start, blks, addr, 747 is_write); 748 } 749 start += blks; 750 blks = 0; 751 addr += ATA_SECT_SIZE * blks; 752 } 753 } while (blks != 0); 754 755 return blkcnt; 756 } 757 758 static int mv_ata_exec_ata_cmd_nondma(int port, 759 struct sata_fis_h2d *cfis, u8 *buffer, 760 u32 len, u32 iswrite) 761 { 762 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 763 int i; 764 u16 *tp; 765 766 debug("%s\n", __func__); 767 768 out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count); 769 out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high); 770 out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid); 771 out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low); 772 out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features); 773 out_le32(priv->regbase + PIO_DEVICE, cfis->device); 774 out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command); 775 776 if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS), 777 ATA_BUSY, 0x0, 10000)) { 778 debug("Failed to wait for completion\n"); 779 return -1; 780 } 781 782 if (len > 0) { 783 tp = (u16 *)buffer; 784 for (i = 0; i < len / 2; i++) { 785 if (iswrite) 786 out_le16(priv->regbase + PIO_DATA, *tp++); 787 else 788 *tp++ = in_le16(priv->regbase + PIO_DATA); 789 } 790 } 791 792 return len; 793 } 794 795 static int mv_sata_identify(int port, u16 *id) 796 { 797 struct sata_fis_h2d h2d; 798 799 memset(&h2d, 0, sizeof(struct sata_fis_h2d)); 800 801 h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D; 802 h2d.command = ATA_CMD_ID_ATA; 803 804 /* Give device time to get operational */ 805 mdelay(10); 806 807 return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id, 808 ATA_ID_WORDS * 2, READ_CMD); 809 } 810 811 static void mv_sata_xfer_mode(int port, u16 *id) 812 { 813 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 814 815 priv->pio = id[ATA_ID_PIO_MODES]; 816 priv->mwdma = id[ATA_ID_MWDMA_MODES]; 817 priv->udma = id[ATA_ID_UDMA_MODES]; 818 debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma, 819 priv->udma); 820 } 821 822 static void mv_sata_set_features(int port) 823 { 824 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 825 struct sata_fis_h2d cfis; 826 u8 udma_cap; 827 828 memset(&cfis, 0, sizeof(struct sata_fis_h2d)); 829 830 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; 831 cfis.command = ATA_CMD_SET_FEATURES; 832 cfis.features = SETFEATURES_XFER; 833 834 /* First check the device capablity */ 835 udma_cap = (u8) (priv->udma & 0xff); 836 837 if (udma_cap == ATA_UDMA6) 838 cfis.sector_count = XFER_UDMA_6; 839 if (udma_cap == ATA_UDMA5) 840 cfis.sector_count = XFER_UDMA_5; 841 if (udma_cap == ATA_UDMA4) 842 cfis.sector_count = XFER_UDMA_4; 843 if (udma_cap == ATA_UDMA3) 844 cfis.sector_count = XFER_UDMA_3; 845 846 mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD); 847 } 848 849 int mv_sata_spin_down(int dev) 850 { 851 struct sata_fis_h2d cfis; 852 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv; 853 854 if (priv->link == 0) { 855 debug("No device on port: %d\n", dev); 856 return 1; 857 } 858 859 memset(&cfis, 0, sizeof(struct sata_fis_h2d)); 860 861 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; 862 cfis.command = ATA_CMD_STANDBY; 863 864 return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD); 865 } 866 867 int mv_sata_spin_up(int dev) 868 { 869 struct sata_fis_h2d cfis; 870 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv; 871 872 if (priv->link == 0) { 873 debug("No device on port: %d\n", dev); 874 return 1; 875 } 876 877 memset(&cfis, 0, sizeof(struct sata_fis_h2d)); 878 879 cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D; 880 cfis.command = ATA_CMD_IDLE; 881 882 return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD); 883 } 884 885 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 886 { 887 return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD); 888 } 889 890 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 891 { 892 return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD); 893 } 894 895 /* 896 * Initialize SATA memory windows 897 */ 898 static void mvsata_ide_conf_mbus_windows(void) 899 { 900 const struct mbus_dram_target_info *dram; 901 int i; 902 903 dram = mvebu_mbus_dram_info(); 904 905 /* Disable windows, Set Size/Base to 0 */ 906 for (i = 0; i < 4; i++) { 907 writel(0, MVSATA_WIN_CONTROL(i)); 908 writel(0, MVSATA_WIN_BASE(i)); 909 } 910 911 for (i = 0; i < dram->num_cs; i++) { 912 const struct mbus_dram_window *cs = dram->cs + i; 913 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | 914 (dram->mbus_dram_target_id << 4) | 1, 915 MVSATA_WIN_CONTROL(i)); 916 writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); 917 } 918 } 919 920 int init_sata(int dev) 921 { 922 struct mv_priv *priv; 923 924 debug("Initialize sata dev: %d\n", dev); 925 926 if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) { 927 printf("Invalid sata device %d\n", dev); 928 return -1; 929 } 930 931 priv = (struct mv_priv *)malloc(sizeof(struct mv_priv)); 932 if (!priv) { 933 printf("Failed to allocate memory for private sata data\n"); 934 return -ENOMEM; 935 } 936 937 memset((void *)priv, 0, sizeof(struct mv_priv)); 938 939 /* Allocate and align request buffer */ 940 priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE + 941 CRQB_ALIGN); 942 if (!priv->crqb_alloc) { 943 printf("Unable to allocate memory for request queue\n"); 944 return -ENOMEM; 945 } 946 memset(priv->crqb_alloc, 0, 947 sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN); 948 priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) & 949 ~(CRQB_ALIGN - 1)); 950 951 /* Allocate and align response buffer */ 952 priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE + 953 CRPB_ALIGN); 954 if (!priv->crpb_alloc) { 955 printf("Unable to allocate memory for response queue\n"); 956 return -ENOMEM; 957 } 958 memset(priv->crpb_alloc, 0, 959 sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN); 960 priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) & 961 ~(CRPB_ALIGN - 1)); 962 963 sata_dev_desc[dev].priv = (void *)priv; 964 965 sprintf(priv->name, "SATA%d", dev); 966 967 priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE; 968 969 if (!hw_init) { 970 debug("Initialize sata hw\n"); 971 hw_init = 1; 972 mv_reset_one_hc(); 973 mvsata_ide_conf_mbus_windows(); 974 } 975 976 mv_reset_port(dev); 977 978 if (probe_port(dev)) { 979 priv->link = 0; 980 return -ENODEV; 981 } 982 priv->link = 1; 983 984 return 0; 985 } 986 987 int reset_sata(int dev) 988 { 989 return 0; 990 } 991 992 int scan_sata(int port) 993 { 994 unsigned char serial[ATA_ID_SERNO_LEN + 1]; 995 unsigned char firmware[ATA_ID_FW_REV_LEN + 1]; 996 unsigned char product[ATA_ID_PROD_LEN + 1]; 997 u64 n_sectors; 998 u16 *id; 999 struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; 1000 1001 if (!priv->link) 1002 return -ENODEV; 1003 1004 id = (u16 *)malloc(ATA_ID_WORDS * 2); 1005 if (!id) { 1006 printf("Failed to malloc id data\n"); 1007 return -ENOMEM; 1008 } 1009 1010 mv_sata_identify(port, id); 1011 ata_swap_buf_le16(id, ATA_ID_WORDS); 1012 #ifdef DEBUG 1013 ata_dump_id(id); 1014 #endif 1015 1016 /* Serial number */ 1017 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 1018 memcpy(sata_dev_desc[port].product, serial, sizeof(serial)); 1019 1020 /* Firmware version */ 1021 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 1022 memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware)); 1023 1024 /* Product model */ 1025 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 1026 memcpy(sata_dev_desc[port].vendor, product, sizeof(product)); 1027 1028 /* Total sectors */ 1029 n_sectors = ata_id_n_sectors(id); 1030 sata_dev_desc[port].lba = n_sectors; 1031 1032 /* Check if support LBA48 */ 1033 if (ata_id_has_lba48(id)) { 1034 sata_dev_desc[port].lba48 = 1; 1035 debug("Device support LBA48\n"); 1036 } 1037 1038 /* Get the NCQ queue depth from device */ 1039 priv->queue_depth = ata_id_queue_depth(id); 1040 1041 /* Get the xfer mode from device */ 1042 mv_sata_xfer_mode(port, id); 1043 1044 /* Set the xfer mode to highest speed */ 1045 mv_sata_set_features(port); 1046 1047 /* Start up */ 1048 mv_start_edma_engine(port); 1049 1050 return 0; 1051 } 1052