xref: /openbmc/u-boot/drivers/ata/sata_mv.c (revision 3ba98ed8)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) Excito Elektronik i Skåne AB, 2010.
4  * Author: Tor Krill <tor@excito.com>
5  *
6  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
7  */
8 
9 /*
10  * This driver supports the SATA controller of some Mavell SoC's.
11  * Here a (most likely incomplete) list of the supported SoC's:
12  * - Kirkwood
13  * - Armada 370
14  * - Armada XP
15  *
16  * This driver implementation is an alternative to the already available
17  * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
18  * But this driver only supports PIO mode and as this new driver also
19  * supports transfer via DMA, its much faster.
20  *
21  * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
22  * by this driver. As they have an AHCI compatible SATA controller
23  * integrated.
24  */
25 
26 /*
27  * TODO:
28  * Better error recovery
29  * No support for using PRDs (Thus max 64KB transfers)
30  * No NCQ support
31  * No port multiplier support
32  */
33 
34 #include <common.h>
35 #include <fis.h>
36 #include <libata.h>
37 #include <malloc.h>
38 #include <sata.h>
39 #include <linux/errno.h>
40 #include <asm/io.h>
41 #include <linux/mbus.h>
42 
43 #if defined(CONFIG_KIRKWOOD)
44 #include <asm/arch/kirkwood.h>
45 #define SATAHC_BASE		KW_SATA_BASE
46 #else
47 #include <asm/arch/soc.h>
48 #define SATAHC_BASE		MVEBU_AXP_SATA_BASE
49 #endif
50 
51 #define SATA0_BASE		(SATAHC_BASE + 0x2000)
52 #define SATA1_BASE		(SATAHC_BASE + 0x4000)
53 
54 /* EDMA registers */
55 #define EDMA_CFG		0x000
56 #define EDMA_CFG_NCQ		(1 << 5)
57 #define EDMA_CFG_EQUE		(1 << 9)
58 #define EDMA_TIMER		0x004
59 #define EDMA_IECR		0x008
60 #define EDMA_IEMR		0x00c
61 #define EDMA_RQBA_HI		0x010
62 #define EDMA_RQIPR		0x014
63 #define EDMA_RQIPR_IPMASK	(0x1f << 5)
64 #define EDMA_RQIPR_IPSHIFT	5
65 #define EDMA_RQOPR		0x018
66 #define EDMA_RQOPR_OPMASK	(0x1f << 5)
67 #define EDMA_RQOPR_OPSHIFT	5
68 #define EDMA_RSBA_HI		0x01c
69 #define EDMA_RSIPR		0x020
70 #define EDMA_RSIPR_IPMASK	(0x1f << 3)
71 #define EDMA_RSIPR_IPSHIFT	3
72 #define	EDMA_RSOPR		0x024
73 #define EDMA_RSOPR_OPMASK	(0x1f << 3)
74 #define EDMA_RSOPR_OPSHIFT	3
75 #define EDMA_CMD		0x028
76 #define EDMA_CMD_ENEDMA		(0x01 << 0)
77 #define EDMA_CMD_DISEDMA	(0x01 << 1)
78 #define EDMA_CMD_ATARST		(0x01 << 2)
79 #define EDMA_CMD_FREEZE		(0x01 << 4)
80 #define EDMA_TEST_CTL		0x02c
81 #define EDMA_STATUS		0x030
82 #define EDMA_IORTO		0x034
83 #define EDMA_CDTR		0x040
84 #define EDMA_HLTCND		0x060
85 #define EDMA_NTSR		0x094
86 
87 /* Basic DMA registers */
88 #define BDMA_CMD		0x224
89 #define BDMA_STATUS		0x228
90 #define BDMA_DTLB		0x22c
91 #define BDMA_DTHB		0x230
92 #define BDMA_DRL		0x234
93 #define BDMA_DRH		0x238
94 
95 /* SATA Interface registers */
96 #define SIR_ICFG		0x050
97 #define SIR_CFG_GEN2EN		(0x1 << 7)
98 #define SIR_PLL_CFG		0x054
99 #define SIR_SSTATUS		0x300
100 #define SSTATUS_DET_MASK	(0x0f << 0)
101 #define SIR_SERROR		0x304
102 #define SIR_SCONTROL		0x308
103 #define SIR_SCONTROL_DETEN	(0x01 << 0)
104 #define SIR_LTMODE		0x30c
105 #define SIR_LTMODE_NELBE	(0x01 << 7)
106 #define SIR_PHYMODE3		0x310
107 #define SIR_PHYMODE4		0x314
108 #define SIR_PHYMODE1		0x32c
109 #define SIR_PHYMODE2		0x330
110 #define SIR_BIST_CTRL		0x334
111 #define SIR_BIST_DW1		0x338
112 #define SIR_BIST_DW2		0x33c
113 #define SIR_SERR_IRQ_MASK	0x340
114 #define SIR_SATA_IFCTRL		0x344
115 #define SIR_SATA_TESTCTRL	0x348
116 #define SIR_SATA_IFSTATUS	0x34c
117 #define SIR_VEND_UNIQ		0x35c
118 #define SIR_FIS_CFG		0x360
119 #define SIR_FIS_IRQ_CAUSE	0x364
120 #define SIR_FIS_IRQ_MASK	0x368
121 #define SIR_FIS_DWORD0		0x370
122 #define SIR_FIS_DWORD1		0x374
123 #define SIR_FIS_DWORD2		0x378
124 #define SIR_FIS_DWORD3		0x37c
125 #define SIR_FIS_DWORD4		0x380
126 #define SIR_FIS_DWORD5		0x384
127 #define SIR_FIS_DWORD6		0x388
128 #define SIR_PHYM9_GEN2		0x398
129 #define SIR_PHYM9_GEN1		0x39c
130 #define SIR_PHY_CFG		0x3a0
131 #define SIR_PHYCTL		0x3a4
132 #define SIR_PHYM10		0x3a8
133 #define SIR_PHYM12		0x3b0
134 
135 /* Shadow registers */
136 #define	PIO_DATA		0x100
137 #define PIO_ERR_FEATURES	0x104
138 #define PIO_SECTOR_COUNT	0x108
139 #define PIO_LBA_LOW		0x10c
140 #define PIO_LBA_MID		0x110
141 #define PIO_LBA_HI		0x114
142 #define PIO_DEVICE		0x118
143 #define PIO_CMD_STATUS		0x11c
144 #define PIO_STATUS_ERR		(0x01 << 0)
145 #define PIO_STATUS_DRQ		(0x01 << 3)
146 #define PIO_STATUS_DF		(0x01 << 5)
147 #define PIO_STATUS_DRDY		(0x01 << 6)
148 #define PIO_STATUS_BSY		(0x01 << 7)
149 #define PIO_CTRL_ALTSTAT	0x120
150 
151 /* SATAHC arbiter registers */
152 #define SATAHC_CFG		0x000
153 #define SATAHC_RQOP		0x004
154 #define SATAHC_RQIP		0x008
155 #define SATAHC_ICT		0x00c
156 #define SATAHC_ITT		0x010
157 #define SATAHC_ICR		0x014
158 #define SATAHC_ICR_PORT0	(0x01 << 0)
159 #define SATAHC_ICR_PORT1	(0x01 << 1)
160 #define SATAHC_MIC		0x020
161 #define SATAHC_MIM		0x024
162 #define SATAHC_LED_CFG		0x02c
163 
164 #define REQUEST_QUEUE_SIZE	32
165 #define RESPONSE_QUEUE_SIZE	REQUEST_QUEUE_SIZE
166 
167 struct crqb {
168 	u32 dtb_low;		/* DW0 */
169 	u32 dtb_high;		/* DW1 */
170 	u32 control_flags;	/* DW2 */
171 	u32 drb_count;		/* DW3 */
172 	u32 ata_cmd_feat;	/* DW4 */
173 	u32 ata_addr;		/* DW5 */
174 	u32 ata_addr_exp;	/* DW6 */
175 	u32 ata_sect_count;	/* DW7 */
176 };
177 
178 #define CRQB_ALIGN			0x400
179 
180 #define CRQB_CNTRLFLAGS_DIR		(0x01 << 0)
181 #define CRQB_CNTRLFLAGS_DQTAGMASK	(0x1f << 1)
182 #define CRQB_CNTRLFLAGS_DQTAGSHIFT	1
183 #define CRQB_CNTRLFLAGS_PMPORTMASK	(0x0f << 12)
184 #define CRQB_CNTRLFLAGS_PMPORTSHIFT	12
185 #define CRQB_CNTRLFLAGS_PRDMODE		(0x01 << 16)
186 #define CRQB_CNTRLFLAGS_HQTAGMASK	(0x1f << 17)
187 #define CRQB_CNTRLFLAGS_HQTAGSHIFT	17
188 
189 #define CRQB_CMDFEAT_CMDMASK		(0xff << 16)
190 #define CRQB_CMDFEAT_CMDSHIFT		16
191 #define CRQB_CMDFEAT_FEATMASK		(0xff << 16)
192 #define CRQB_CMDFEAT_FEATSHIFT		24
193 
194 #define CRQB_ADDR_LBA_LOWMASK		(0xff << 0)
195 #define CRQB_ADDR_LBA_LOWSHIFT		0
196 #define CRQB_ADDR_LBA_MIDMASK		(0xff << 8)
197 #define CRQB_ADDR_LBA_MIDSHIFT		8
198 #define CRQB_ADDR_LBA_HIGHMASK		(0xff << 16)
199 #define CRQB_ADDR_LBA_HIGHSHIFT		16
200 #define CRQB_ADDR_DEVICE_MASK		(0xff << 24)
201 #define CRQB_ADDR_DEVICE_SHIFT		24
202 
203 #define CRQB_ADDR_LBA_LOW_EXP_MASK	(0xff << 0)
204 #define CRQB_ADDR_LBA_LOW_EXP_SHIFT	0
205 #define CRQB_ADDR_LBA_MID_EXP_MASK	(0xff << 8)
206 #define CRQB_ADDR_LBA_MID_EXP_SHIFT	8
207 #define CRQB_ADDR_LBA_HIGH_EXP_MASK	(0xff << 16)
208 #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT	16
209 #define CRQB_ADDR_FEATURE_EXP_MASK	(0xff << 24)
210 #define CRQB_ADDR_FEATURE_EXP_SHIFT	24
211 
212 #define CRQB_SECTCOUNT_COUNT_MASK	(0xff << 0)
213 #define CRQB_SECTCOUNT_COUNT_SHIFT	0
214 #define CRQB_SECTCOUNT_COUNT_EXP_MASK	(0xff << 8)
215 #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT	8
216 
217 #define MVSATA_WIN_CONTROL(w)	(MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
218 #define MVSATA_WIN_BASE(w)	(MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
219 
220 struct eprd {
221 	u32 phyaddr_low;
222 	u32 bytecount_eot;
223 	u32 phyaddr_hi;
224 	u32 reserved;
225 };
226 
227 #define EPRD_PHYADDR_MASK	0xfffffffe
228 #define EPRD_BYTECOUNT_MASK	0x0000ffff
229 #define EPRD_EOT		(0x01 << 31)
230 
231 struct crpb {
232 	u32 id;
233 	u32 flags;
234 	u32 timestamp;
235 };
236 
237 #define CRPB_ALIGN		0x100
238 
239 #define READ_CMD		0
240 #define WRITE_CMD		1
241 
242 /*
243  * Since we don't use PRDs yet max transfer size
244  * is 64KB
245  */
246 #define MV_ATA_MAX_SECTORS	(65535 / ATA_SECT_SIZE)
247 
248 /* Keep track if hw is initialized or not */
249 static u32 hw_init;
250 
251 struct mv_priv {
252 	char name[12];
253 	u32 link;
254 	u32 regbase;
255 	u32 queue_depth;
256 	u16 pio;
257 	u16 mwdma;
258 	u16 udma;
259 
260 	void *crqb_alloc;
261 	struct crqb *request;
262 
263 	void *crpb_alloc;
264 	struct crpb *response;
265 };
266 
267 static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
268 {
269 	ulong start;
270 
271 	start = get_timer(0);
272 	do {
273 		if ((in_le32(addr) & mask) == val)
274 			return 0;
275 	} while (get_timer(start) < timeout_msec);
276 
277 	return -ETIMEDOUT;
278 }
279 
280 /* Cut from sata_mv in linux kernel */
281 static int mv_stop_edma_engine(int port)
282 {
283 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
284 	int i;
285 
286 	/* Disable eDMA. The disable bit auto clears. */
287 	out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
288 
289 	/* Wait for the chip to confirm eDMA is off. */
290 	for (i = 10000; i > 0; i--) {
291 		u32 reg = in_le32(priv->regbase + EDMA_CMD);
292 		if (!(reg & EDMA_CMD_ENEDMA)) {
293 			debug("EDMA stop on port %d succesful\n", port);
294 			return 0;
295 		}
296 		udelay(10);
297 	}
298 	debug("EDMA stop on port %d failed\n", port);
299 	return -1;
300 }
301 
302 static int mv_start_edma_engine(int port)
303 {
304 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
305 	u32 tmp;
306 
307 	/* Check preconditions */
308 	tmp = in_le32(priv->regbase + SIR_SSTATUS);
309 	if ((tmp & SSTATUS_DET_MASK) != 0x03) {
310 		printf("Device error on port: %d\n", port);
311 		return -1;
312 	}
313 
314 	tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
315 	if (tmp & (ATA_BUSY | ATA_DRQ)) {
316 		printf("Device not ready on port: %d\n", port);
317 		return -1;
318 	}
319 
320 	/* Clear interrupt cause */
321 	out_le32(priv->regbase + EDMA_IECR, 0x0);
322 
323 	tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
324 	tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
325 	out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
326 
327 	/* Configure edma operation */
328 	tmp = in_le32(priv->regbase + EDMA_CFG);
329 	tmp &= ~EDMA_CFG_NCQ;	/* No NCQ */
330 	tmp &= ~EDMA_CFG_EQUE;	/* Dont queue operations */
331 	out_le32(priv->regbase + EDMA_CFG, tmp);
332 
333 	out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
334 
335 	/* Configure fis, set all to no-wait for now */
336 	out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
337 
338 	/* Setup request queue */
339 	out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
340 	out_le32(priv->regbase + EDMA_RQIPR, priv->request);
341 	out_le32(priv->regbase + EDMA_RQOPR, 0x0);
342 
343 	/* Setup response queue */
344 	out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
345 	out_le32(priv->regbase + EDMA_RSOPR, priv->response);
346 	out_le32(priv->regbase + EDMA_RSIPR, 0x0);
347 
348 	/* Start edma */
349 	out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
350 
351 	return 0;
352 }
353 
354 static int mv_reset_channel(int port)
355 {
356 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
357 
358 	/* Make sure edma is stopped  */
359 	mv_stop_edma_engine(port);
360 
361 	out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
362 	udelay(25);		/* allow reset propagation */
363 	out_le32(priv->regbase + EDMA_CMD, 0);
364 	mdelay(10);
365 
366 	return 0;
367 }
368 
369 static void mv_reset_port(int port)
370 {
371 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
372 
373 	mv_reset_channel(port);
374 
375 	out_le32(priv->regbase + EDMA_CMD, 0x0);
376 	out_le32(priv->regbase + EDMA_CFG, 0x101f);
377 	out_le32(priv->regbase + EDMA_IECR, 0x0);
378 	out_le32(priv->regbase + EDMA_IEMR, 0x0);
379 	out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
380 	out_le32(priv->regbase + EDMA_RQIPR, 0x0);
381 	out_le32(priv->regbase + EDMA_RQOPR, 0x0);
382 	out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
383 	out_le32(priv->regbase + EDMA_RSIPR, 0x0);
384 	out_le32(priv->regbase + EDMA_RSOPR, 0x0);
385 	out_le32(priv->regbase + EDMA_IORTO, 0xfa);
386 }
387 
388 static void mv_reset_one_hc(void)
389 {
390 	out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
391 	out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
392 	out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
393 }
394 
395 static int probe_port(int port)
396 {
397 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
398 	int tries, tries2, set15 = 0;
399 	u32 tmp;
400 
401 	debug("Probe port: %d\n", port);
402 
403 	for (tries = 0; tries < 2; tries++) {
404 		/* Clear SError */
405 		out_le32(priv->regbase + SIR_SERROR, 0x0);
406 
407 		/* trigger com-init */
408 		tmp = in_le32(priv->regbase + SIR_SCONTROL);
409 		tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
410 		out_le32(priv->regbase + SIR_SCONTROL, tmp);
411 
412 		mdelay(1);
413 
414 		tmp = in_le32(priv->regbase + SIR_SCONTROL);
415 		tries2 = 5;
416 		do {
417 			tmp = (tmp & 0x0f0) | 0x300;
418 			out_le32(priv->regbase + SIR_SCONTROL, tmp);
419 			mdelay(10);
420 			tmp = in_le32(priv->regbase + SIR_SCONTROL);
421 		} while ((tmp & 0xf0f) != 0x300 && tries2--);
422 
423 		mdelay(10);
424 
425 		for (tries2 = 0; tries2 < 200; tries2++) {
426 			tmp = in_le32(priv->regbase + SIR_SSTATUS);
427 			if ((tmp & SSTATUS_DET_MASK) == 0x03) {
428 				debug("Found device on port\n");
429 				return 0;
430 			}
431 			mdelay(1);
432 		}
433 
434 		if ((tmp & SSTATUS_DET_MASK) == 0) {
435 			debug("No device attached on port %d\n", port);
436 			return -ENODEV;
437 		}
438 
439 		if (!set15) {
440 			/* Try on 1.5Gb/S */
441 			debug("Try 1.5Gb link\n");
442 			set15 = 1;
443 			out_le32(priv->regbase + SIR_SCONTROL, 0x304);
444 
445 			tmp = in_le32(priv->regbase + SIR_ICFG);
446 			tmp &= ~SIR_CFG_GEN2EN;
447 			out_le32(priv->regbase + SIR_ICFG, tmp);
448 
449 			mv_reset_channel(port);
450 		}
451 	}
452 
453 	debug("Failed to probe port\n");
454 	return -1;
455 }
456 
457 /* Get request queue in pointer */
458 static int get_reqip(int port)
459 {
460 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
461 	u32 tmp;
462 
463 	tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
464 	tmp = tmp >> EDMA_RQIPR_IPSHIFT;
465 
466 	return tmp;
467 }
468 
469 static void set_reqip(int port, int reqin)
470 {
471 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
472 	u32 tmp;
473 
474 	tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
475 	tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
476 	out_le32(priv->regbase + EDMA_RQIPR, tmp);
477 }
478 
479 /* Get next available slot, ignoring possible overwrite */
480 static int get_next_reqip(int port)
481 {
482 	int slot = get_reqip(port);
483 	slot = (slot + 1) % REQUEST_QUEUE_SIZE;
484 	return slot;
485 }
486 
487 /* Get response queue in pointer */
488 static int get_rspip(int port)
489 {
490 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
491 	u32 tmp;
492 
493 	tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
494 	tmp = tmp >> EDMA_RSIPR_IPSHIFT;
495 
496 	return tmp;
497 }
498 
499 /* Get response queue out pointer */
500 static int get_rspop(int port)
501 {
502 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
503 	u32 tmp;
504 
505 	tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
506 	tmp = tmp >> EDMA_RSOPR_OPSHIFT;
507 	return tmp;
508 }
509 
510 /* Get next response queue pointer  */
511 static int get_next_rspop(int port)
512 {
513 	return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE;
514 }
515 
516 /* Set response queue pointer */
517 static void set_rspop(int port, int reqin)
518 {
519 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
520 	u32 tmp;
521 
522 	tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
523 	tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
524 
525 	out_le32(priv->regbase + EDMA_RSOPR, tmp);
526 }
527 
528 static int wait_dma_completion(int port, int index, u32 timeout_msec)
529 {
530 	u32 tmp, res;
531 
532 	tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
533 	res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
534 				tmp, timeout_msec);
535 	if (res)
536 		printf("Failed to wait for completion on port %d\n", port);
537 
538 	return res;
539 }
540 
541 static void process_responses(int port)
542 {
543 #ifdef DEBUG
544 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
545 #endif
546 	u32 tmp;
547 	u32 outind = get_rspop(port);
548 
549 	/* Ack interrupts */
550 	tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
551 	if (port == 0)
552 		tmp &= ~(BIT(0) | BIT(8));
553 	else
554 		tmp &= ~(BIT(1) | BIT(9));
555 	tmp &= ~(BIT(4));
556 	out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
557 
558 	while (get_rspip(port) != outind) {
559 #ifdef DEBUG
560 		debug("Response index %d flags %08x on port %d\n", outind,
561 		      priv->response[outind].flags, port);
562 #endif
563 		outind = get_next_rspop(port);
564 		set_rspop(port, outind);
565 	}
566 }
567 
568 static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
569 			       u8 *buffer, u32 len, u32 iswrite)
570 {
571 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
572 	struct crqb *req;
573 	int slot;
574 	u32 start;
575 
576 	if (len >= 64 * 1024) {
577 		printf("We only support <64K transfers for now\n");
578 		return -1;
579 	}
580 
581 	/* Initialize request */
582 	slot = get_reqip(port);
583 	memset(&priv->request[slot], 0, sizeof(struct crqb));
584 	req = &priv->request[slot];
585 
586 	req->dtb_low = (u32)buffer;
587 
588 	/* Dont use PRDs */
589 	req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
590 	req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
591 	req->control_flags |=
592 	    ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
593 	     & CRQB_CNTRLFLAGS_PMPORTMASK);
594 
595 	req->drb_count = len;
596 
597 	req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
598 		CRQB_CMDFEAT_CMDMASK;
599 	req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
600 		CRQB_CMDFEAT_FEATMASK;
601 
602 	req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
603 		CRQB_ADDR_LBA_LOWMASK;
604 	req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
605 		CRQB_ADDR_LBA_MIDMASK;
606 	req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
607 		CRQB_ADDR_LBA_HIGHMASK;
608 	req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
609 		CRQB_ADDR_DEVICE_MASK;
610 
611 	req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
612 		CRQB_ADDR_LBA_LOW_EXP_MASK;
613 	req->ata_addr_exp |=
614 		(cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
615 		CRQB_ADDR_LBA_MID_EXP_MASK;
616 	req->ata_addr_exp |=
617 		(cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
618 		CRQB_ADDR_LBA_HIGH_EXP_MASK;
619 	req->ata_addr_exp |=
620 		(cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
621 		CRQB_ADDR_FEATURE_EXP_MASK;
622 
623 	req->ata_sect_count =
624 		(cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
625 		CRQB_SECTCOUNT_COUNT_MASK;
626 	req->ata_sect_count |=
627 		(cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
628 		CRQB_SECTCOUNT_COUNT_EXP_MASK;
629 
630 	/* Flush data */
631 	start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
632 	flush_dcache_range(start,
633 			   start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
634 
635 	/* Trigger operation */
636 	slot = get_next_reqip(port);
637 	set_reqip(port, slot);
638 
639 	/* Wait for completion */
640 	if (wait_dma_completion(port, slot, 10000)) {
641 		printf("ATA operation timed out\n");
642 		return -1;
643 	}
644 
645 	process_responses(port);
646 
647 	/* Invalidate data on read */
648 	if (buffer && len) {
649 		start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
650 		invalidate_dcache_range(start,
651 					start + ALIGN(len, ARCH_DMA_MINALIGN));
652 	}
653 
654 	return len;
655 }
656 
657 static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
658 			      u8 *buffer, int is_write)
659 {
660 	struct sata_fis_h2d cfis;
661 	u32 res;
662 	u64 block;
663 
664 	block = (u64)start;
665 
666 	memset(&cfis, 0, sizeof(struct sata_fis_h2d));
667 
668 	cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
669 	cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
670 
671 	cfis.lba_high_exp = (block >> 40) & 0xff;
672 	cfis.lba_mid_exp = (block >> 32) & 0xff;
673 	cfis.lba_low_exp = (block >> 24) & 0xff;
674 	cfis.lba_high = (block >> 16) & 0xff;
675 	cfis.lba_mid = (block >> 8) & 0xff;
676 	cfis.lba_low = block & 0xff;
677 	cfis.device = ATA_LBA;
678 	cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
679 	cfis.sector_count = blkcnt & 0xff;
680 
681 	res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
682 				  is_write);
683 
684 	return res >= 0 ? blkcnt : res;
685 }
686 
687 static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
688 			  int is_write)
689 {
690 	struct sata_fis_h2d cfis;
691 	lbaint_t block;
692 	u32 res;
693 
694 	block = start;
695 
696 	memset(&cfis, 0, sizeof(struct sata_fis_h2d));
697 
698 	cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
699 	cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
700 	cfis.device = ATA_LBA;
701 
702 	cfis.device |= (block >> 24) & 0xf;
703 	cfis.lba_high = (block >> 16) & 0xff;
704 	cfis.lba_mid = (block >> 8) & 0xff;
705 	cfis.lba_low = block & 0xff;
706 	cfis.sector_count = (u8)(blkcnt & 0xff);
707 
708 	res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
709 				  is_write);
710 
711 	return res >= 0 ? blkcnt : res;
712 }
713 
714 static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
715 			    void *buffer, int is_write)
716 {
717 	lbaint_t start, blks;
718 	u8 *addr;
719 	int max_blks;
720 
721 	debug("%s: %ld %ld\n", __func__, blknr, blkcnt);
722 
723 	start = blknr;
724 	blks = blkcnt;
725 	addr = (u8 *)buffer;
726 
727 	max_blks = MV_ATA_MAX_SECTORS;
728 	do {
729 		if (blks > max_blks) {
730 			if (sata_dev_desc[dev].lba48) {
731 				mv_sata_rw_cmd_ext(dev, start, max_blks, addr,
732 						   is_write);
733 			} else {
734 				mv_sata_rw_cmd(dev, start, max_blks, addr,
735 					       is_write);
736 			}
737 			start += max_blks;
738 			blks -= max_blks;
739 			addr += ATA_SECT_SIZE * max_blks;
740 		} else {
741 			if (sata_dev_desc[dev].lba48) {
742 				mv_sata_rw_cmd_ext(dev, start, blks, addr,
743 						   is_write);
744 			} else {
745 				mv_sata_rw_cmd(dev, start, blks, addr,
746 					       is_write);
747 			}
748 			start += blks;
749 			blks = 0;
750 			addr += ATA_SECT_SIZE * blks;
751 		}
752 	} while (blks != 0);
753 
754 	return blkcnt;
755 }
756 
757 static int mv_ata_exec_ata_cmd_nondma(int port,
758 				      struct sata_fis_h2d *cfis, u8 *buffer,
759 				      u32 len, u32 iswrite)
760 {
761 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
762 	int i;
763 	u16 *tp;
764 
765 	debug("%s\n", __func__);
766 
767 	out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
768 	out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
769 	out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
770 	out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
771 	out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
772 	out_le32(priv->regbase + PIO_DEVICE, cfis->device);
773 	out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
774 
775 	if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
776 			      ATA_BUSY, 0x0, 10000)) {
777 		debug("Failed to wait for completion\n");
778 		return -1;
779 	}
780 
781 	if (len > 0) {
782 		tp = (u16 *)buffer;
783 		for (i = 0; i < len / 2; i++) {
784 			if (iswrite)
785 				out_le16(priv->regbase + PIO_DATA, *tp++);
786 			else
787 				*tp++ = in_le16(priv->regbase + PIO_DATA);
788 		}
789 	}
790 
791 	return len;
792 }
793 
794 static int mv_sata_identify(int port, u16 *id)
795 {
796 	struct sata_fis_h2d h2d;
797 
798 	memset(&h2d, 0, sizeof(struct sata_fis_h2d));
799 
800 	h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
801 	h2d.command = ATA_CMD_ID_ATA;
802 
803 	/* Give device time to get operational */
804 	mdelay(10);
805 
806 	return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id,
807 					  ATA_ID_WORDS * 2, READ_CMD);
808 }
809 
810 static void mv_sata_xfer_mode(int port, u16 *id)
811 {
812 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
813 
814 	priv->pio = id[ATA_ID_PIO_MODES];
815 	priv->mwdma = id[ATA_ID_MWDMA_MODES];
816 	priv->udma = id[ATA_ID_UDMA_MODES];
817 	debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
818 	      priv->udma);
819 }
820 
821 static void mv_sata_set_features(int port)
822 {
823 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
824 	struct sata_fis_h2d cfis;
825 	u8 udma_cap;
826 
827 	memset(&cfis, 0, sizeof(struct sata_fis_h2d));
828 
829 	cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
830 	cfis.command = ATA_CMD_SET_FEATURES;
831 	cfis.features = SETFEATURES_XFER;
832 
833 	/* First check the device capablity */
834 	udma_cap = (u8) (priv->udma & 0xff);
835 
836 	if (udma_cap == ATA_UDMA6)
837 		cfis.sector_count = XFER_UDMA_6;
838 	if (udma_cap == ATA_UDMA5)
839 		cfis.sector_count = XFER_UDMA_5;
840 	if (udma_cap == ATA_UDMA4)
841 		cfis.sector_count = XFER_UDMA_4;
842 	if (udma_cap == ATA_UDMA3)
843 		cfis.sector_count = XFER_UDMA_3;
844 
845 	mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD);
846 }
847 
848 int mv_sata_spin_down(int dev)
849 {
850 	struct sata_fis_h2d cfis;
851 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
852 
853 	if (priv->link == 0) {
854 		debug("No device on port: %d\n", dev);
855 		return 1;
856 	}
857 
858 	memset(&cfis, 0, sizeof(struct sata_fis_h2d));
859 
860 	cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
861 	cfis.command = ATA_CMD_STANDBY;
862 
863 	return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
864 }
865 
866 int mv_sata_spin_up(int dev)
867 {
868 	struct sata_fis_h2d cfis;
869 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
870 
871 	if (priv->link == 0) {
872 		debug("No device on port: %d\n", dev);
873 		return 1;
874 	}
875 
876 	memset(&cfis, 0, sizeof(struct sata_fis_h2d));
877 
878 	cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
879 	cfis.command = ATA_CMD_IDLE;
880 
881 	return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
882 }
883 
884 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
885 {
886 	return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD);
887 }
888 
889 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
890 {
891 	return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD);
892 }
893 
894 /*
895  * Initialize SATA memory windows
896  */
897 static void mvsata_ide_conf_mbus_windows(void)
898 {
899 	const struct mbus_dram_target_info *dram;
900 	int i;
901 
902 	dram = mvebu_mbus_dram_info();
903 
904 	/* Disable windows, Set Size/Base to 0  */
905 	for (i = 0; i < 4; i++) {
906 		writel(0, MVSATA_WIN_CONTROL(i));
907 		writel(0, MVSATA_WIN_BASE(i));
908 	}
909 
910 	for (i = 0; i < dram->num_cs; i++) {
911 		const struct mbus_dram_window *cs = dram->cs + i;
912 		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
913 		       (dram->mbus_dram_target_id << 4) | 1,
914 		       MVSATA_WIN_CONTROL(i));
915 		writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
916 	}
917 }
918 
919 int init_sata(int dev)
920 {
921 	struct mv_priv *priv;
922 
923 	debug("Initialize sata dev: %d\n", dev);
924 
925 	if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
926 		printf("Invalid sata device %d\n", dev);
927 		return -1;
928 	}
929 
930 	priv = (struct mv_priv *)malloc(sizeof(struct mv_priv));
931 	if (!priv) {
932 		printf("Failed to allocate memory for private sata data\n");
933 		return -ENOMEM;
934 	}
935 
936 	memset((void *)priv, 0, sizeof(struct mv_priv));
937 
938 	/* Allocate and align request buffer */
939 	priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
940 				  CRQB_ALIGN);
941 	if (!priv->crqb_alloc) {
942 		printf("Unable to allocate memory for request queue\n");
943 		return -ENOMEM;
944 	}
945 	memset(priv->crqb_alloc, 0,
946 	       sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
947 	priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
948 					~(CRQB_ALIGN - 1));
949 
950 	/* Allocate and align response buffer */
951 	priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
952 				  CRPB_ALIGN);
953 	if (!priv->crpb_alloc) {
954 		printf("Unable to allocate memory for response queue\n");
955 		return -ENOMEM;
956 	}
957 	memset(priv->crpb_alloc, 0,
958 	       sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
959 	priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
960 					 ~(CRPB_ALIGN - 1));
961 
962 	sata_dev_desc[dev].priv = (void *)priv;
963 
964 	sprintf(priv->name, "SATA%d", dev);
965 
966 	priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE;
967 
968 	if (!hw_init) {
969 		debug("Initialize sata hw\n");
970 		hw_init = 1;
971 		mv_reset_one_hc();
972 		mvsata_ide_conf_mbus_windows();
973 	}
974 
975 	mv_reset_port(dev);
976 
977 	if (probe_port(dev)) {
978 		priv->link = 0;
979 		return -ENODEV;
980 	}
981 	priv->link = 1;
982 
983 	return 0;
984 }
985 
986 int reset_sata(int dev)
987 {
988 	return 0;
989 }
990 
991 int scan_sata(int port)
992 {
993 	unsigned char serial[ATA_ID_SERNO_LEN + 1];
994 	unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
995 	unsigned char product[ATA_ID_PROD_LEN + 1];
996 	u64 n_sectors;
997 	u16 *id;
998 	struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
999 
1000 	if (!priv->link)
1001 		return -ENODEV;
1002 
1003 	id = (u16 *)malloc(ATA_ID_WORDS * 2);
1004 	if (!id) {
1005 		printf("Failed to malloc id data\n");
1006 		return -ENOMEM;
1007 	}
1008 
1009 	mv_sata_identify(port, id);
1010 	ata_swap_buf_le16(id, ATA_ID_WORDS);
1011 #ifdef DEBUG
1012 	ata_dump_id(id);
1013 #endif
1014 
1015 	/* Serial number */
1016 	ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
1017 	memcpy(sata_dev_desc[port].product, serial, sizeof(serial));
1018 
1019 	/* Firmware version */
1020 	ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
1021 	memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware));
1022 
1023 	/* Product model */
1024 	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
1025 	memcpy(sata_dev_desc[port].vendor, product, sizeof(product));
1026 
1027 	/* Total sectors */
1028 	n_sectors = ata_id_n_sectors(id);
1029 	sata_dev_desc[port].lba = n_sectors;
1030 
1031 	/* Check if support LBA48 */
1032 	if (ata_id_has_lba48(id)) {
1033 		sata_dev_desc[port].lba48 = 1;
1034 		debug("Device support LBA48\n");
1035 	}
1036 
1037 	/* Get the NCQ queue depth from device */
1038 	priv->queue_depth = ata_id_queue_depth(id);
1039 
1040 	/* Get the xfer mode from device */
1041 	mv_sata_xfer_mode(port, id);
1042 
1043 	/* Set the xfer mode to highest speed */
1044 	mv_sata_set_features(port);
1045 
1046 	/* Start up */
1047 	mv_start_edma_engine(port);
1048 
1049 	return 0;
1050 }
1051