xref: /openbmc/u-boot/drivers/ata/mvsata_ide.c (revision f77d4410)
1  // SPDX-License-Identifier: GPL-2.0+
2  /*
3   * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4   *
5   * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
6   */
7  
8  #include <common.h>
9  #include <asm/io.h>
10  
11  #if defined(CONFIG_ORION5X)
12  #include <asm/arch/orion5x.h>
13  #elif defined(CONFIG_KIRKWOOD)
14  #include <asm/arch/soc.h>
15  #elif defined(CONFIG_ARCH_MVEBU)
16  #include <linux/mbus.h>
17  #endif
18  
19  /* SATA port registers */
20  struct mvsata_port_registers {
21  	u32 reserved0[10];
22  	u32 edma_cmd;
23  	u32 reserved1[181];
24  	/* offset 0x300 : ATA Interface registers */
25  	u32 sstatus;
26  	u32 serror;
27  	u32 scontrol;
28  	u32 ltmode;
29  	u32 phymode3;
30  	u32 phymode4;
31  	u32 reserved2[5];
32  	u32 phymode1;
33  	u32 phymode2;
34  	u32 bist_cr;
35  	u32 bist_dw1;
36  	u32 bist_dw2;
37  	u32 serrorintrmask;
38  };
39  
40  /*
41   * Sanity checks:
42   * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
43   * - for ide_preinit to make sense, we need at least one of
44   *   CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
45   * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
46   * Fail with an explanation message if these conditions are not met.
47   * This is particularly important for CONFIG_IDE_PREINIT, because
48   * its lack would not cause a build error.
49   */
50  
51  #if !defined(CONFIG_SYS_ATA_BASE_ADDR)
52  #error CONFIG_SYS_ATA_BASE_ADDR must be defined
53  #elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
54     && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
55  #error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
56     must be defined
57  #elif !defined(CONFIG_IDE_PREINIT)
58  #error CONFIG_IDE_PREINIT must be defined
59  #endif
60  
61  /*
62   * Masks and values for SControl DETection and Interface Power Management,
63   * and for SStatus DETection.
64   */
65  
66  #define MVSATA_EDMA_CMD_ATA_RST		0x00000004
67  #define MVSATA_SCONTROL_DET_MASK		0x0000000F
68  #define MVSATA_SCONTROL_DET_NONE		0x00000000
69  #define MVSATA_SCONTROL_DET_INIT		0x00000001
70  #define MVSATA_SCONTROL_IPM_MASK		0x00000F00
71  #define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED	0x00000300
72  #define MVSATA_SCONTROL_MASK \
73  	(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
74  #define MVSATA_PORT_INIT \
75  	(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
76  #define MVSATA_PORT_USE \
77  	(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
78  #define MVSATA_SSTATUS_DET_MASK			0x0000000F
79  #define MVSATA_SSTATUS_DET_DEVCOMM		0x00000003
80  
81  /*
82   * Status codes to return to client callers. Currently, callers ignore
83   * exact value and only care for zero or nonzero, so no need to make this
84   * public, it is only #define'd for clarity.
85   * If/when standard negative codes are implemented in U-Boot, then these
86   * #defines should be moved to, or replaced by ones from, the common list
87   * of status codes.
88   */
89  
90  #define MVSATA_STATUS_OK	0
91  #define MVSATA_STATUS_TIMEOUT	-1
92  
93  /*
94   * Registers for SATA MBUS memory windows
95   */
96  
97  #define MVSATA_WIN_CONTROL(w)	(MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
98  #define MVSATA_WIN_BASE(w)	(MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
99  
100  /*
101   * Initialize SATA memory windows for Armada XP
102   */
103  
104  #ifdef CONFIG_ARCH_MVEBU
105  static void mvsata_ide_conf_mbus_windows(void)
106  {
107  	const struct mbus_dram_target_info *dram;
108  	int i;
109  
110  	dram = mvebu_mbus_dram_info();
111  
112  	/* Disable windows, Set Size/Base to 0  */
113  	for (i = 0; i < 4; i++) {
114  		writel(0, MVSATA_WIN_CONTROL(i));
115  		writel(0, MVSATA_WIN_BASE(i));
116  	}
117  
118  	for (i = 0; i < dram->num_cs; i++) {
119  		const struct mbus_dram_window *cs = dram->cs + i;
120  		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
121  				(dram->mbus_dram_target_id << 4) | 1,
122  				MVSATA_WIN_CONTROL(i));
123  		writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
124  	}
125  }
126  #endif
127  
128  /*
129   * Initialize one MVSATAHC port: set SControl's IPM to "always active"
130   * and DET to "reset", then wait for SStatus's DET to become "device and
131   * comm ok" (or time out after 50 us if no device), then set SControl's
132   * DET back to "no action".
133   */
134  
135  static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
136  {
137  	u32 control;
138  	u32 status;
139  	u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
140  
141  	/* Hard reset */
142  	writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
143  	udelay(25); /* taken from original marvell port */
144  	writel(0, &port->edma_cmd);
145  
146  	/* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
147  	control = readl(&port->scontrol);
148  	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
149  	writel(control, &port->scontrol);
150  	/* Toggle control DET back to 0 (normal operation) */
151  	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
152  	writel(control, &port->scontrol);
153  	/* wait for status DET to become 3 (device and communication OK) */
154  	while (--timeleft) {
155  		status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
156  		if (status == MVSATA_SSTATUS_DET_DEVCOMM)
157  			break;
158  		udelay(1);
159  	}
160  	/* return success or time-out error depending on time left */
161  	if (!timeleft)
162  		return MVSATA_STATUS_TIMEOUT;
163  	return MVSATA_STATUS_OK;
164  }
165  
166  /*
167   * ide_preinit() will be called by ide_init in cmd_ide.c and will
168   * reset the MVSTATHC ports needed by the board.
169   */
170  
171  int ide_preinit(void)
172  {
173  	int ret = MVSATA_STATUS_TIMEOUT;
174  	int status;
175  
176  #ifdef CONFIG_ARCH_MVEBU
177  	mvsata_ide_conf_mbus_windows();
178  #endif
179  
180  	/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
181  #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
182  	status = mvsata_ide_initialize_port(
183  		(struct mvsata_port_registers *)
184  		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
185  	if (status == MVSATA_STATUS_OK)
186  		ret = MVSATA_STATUS_OK;
187  #endif
188  	/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
189  #if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
190  	status = mvsata_ide_initialize_port(
191  		(struct mvsata_port_registers *)
192  		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
193  	if (status == MVSATA_STATUS_OK)
194  		ret = MVSATA_STATUS_OK;
195  #endif
196  	/* Return success if at least one port initialization succeeded */
197  	return ret;
198  }
199