1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 * Author: Jason Jin<Jason.jin@freescale.com> 5 * Zhang Wei<wei.zhang@freescale.com> 6 * 7 * with the reference on libata and ahci drvier in kernel 8 * 9 * This driver provides a SCSI interface to SATA. 10 */ 11 #include <common.h> 12 13 #include <command.h> 14 #include <dm.h> 15 #include <pci.h> 16 #include <asm/processor.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <malloc.h> 20 #include <memalign.h> 21 #include <pci.h> 22 #include <scsi.h> 23 #include <libata.h> 24 #include <linux/ctype.h> 25 #include <ahci.h> 26 #include <dm/device-internal.h> 27 #include <dm/lists.h> 28 29 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); 30 31 #ifndef CONFIG_DM_SCSI 32 struct ahci_uc_priv *probe_ent = NULL; 33 #endif 34 35 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) 36 37 /* 38 * Some controllers limit number of blocks they can read/write at once. 39 * Contemporary SSD devices work much faster if the read/write size is aligned 40 * to a power of 2. Let's set default to 128 and allowing to be overwritten if 41 * needed. 42 */ 43 #ifndef MAX_SATA_BLOCKS_READ_WRITE 44 #define MAX_SATA_BLOCKS_READ_WRITE 0x80 45 #endif 46 47 /* Maximum timeouts for each event */ 48 #define WAIT_MS_SPINUP 20000 49 #define WAIT_MS_DATAIO 10000 50 #define WAIT_MS_FLUSH 5000 51 #define WAIT_MS_LINKUP 200 52 53 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port) 54 { 55 return base + 0x100 + (port * 0x80); 56 } 57 58 59 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, 60 unsigned int port_idx) 61 { 62 base = ahci_port_base(base, port_idx); 63 64 port->cmd_addr = base; 65 port->scr_addr = base + PORT_SCR; 66 } 67 68 69 #define msleep(a) udelay(a * 1000) 70 71 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) 72 { 73 const unsigned long start = begin; 74 const unsigned long end = start + len; 75 76 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); 77 flush_dcache_range(start, end); 78 } 79 80 /* 81 * SATA controller DMAs to physical RAM. Ensure data from the 82 * controller is invalidated from dcache; next access comes from 83 * physical RAM. 84 */ 85 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) 86 { 87 const unsigned long start = begin; 88 const unsigned long end = start + len; 89 90 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); 91 invalidate_dcache_range(start, end); 92 } 93 94 /* 95 * Ensure data for SATA controller is flushed out of dcache and 96 * written to physical memory. 97 */ 98 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) 99 { 100 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, 101 AHCI_PORT_PRIV_DMA_SZ); 102 } 103 104 static int waiting_for_cmd_completed(void __iomem *offset, 105 int timeout_msec, 106 u32 sign) 107 { 108 int i; 109 u32 status; 110 111 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) 112 msleep(1); 113 114 return (i < timeout_msec) ? 0 : -1; 115 } 116 117 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port) 118 { 119 u32 tmp; 120 int j = 0; 121 void __iomem *port_mmio = uc_priv->port[port].port_mmio; 122 123 /* 124 * Bring up SATA link. 125 * SATA link bringup time is usually less than 1 ms; only very 126 * rarely has it taken between 1-2 ms. Never seen it above 2 ms. 127 */ 128 while (j < WAIT_MS_LINKUP) { 129 tmp = readl(port_mmio + PORT_SCR_STAT); 130 tmp &= PORT_SCR_STAT_DET_MASK; 131 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 132 return 0; 133 udelay(1000); 134 j++; 135 } 136 return 1; 137 } 138 139 #ifdef CONFIG_SUNXI_AHCI 140 /* The sunxi AHCI controller requires this undocumented setup */ 141 static void sunxi_dma_init(void __iomem *port_mmio) 142 { 143 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); 144 } 145 #endif 146 147 int ahci_reset(void __iomem *base) 148 { 149 int i = 1000; 150 u32 __iomem *host_ctl_reg = base + HOST_CTL; 151 u32 tmp = readl(host_ctl_reg); /* global controller reset */ 152 153 if ((tmp & HOST_RESET) == 0) 154 writel_with_flush(tmp | HOST_RESET, host_ctl_reg); 155 156 /* 157 * reset must complete within 1 second, or 158 * the hardware should be considered fried. 159 */ 160 do { 161 udelay(1000); 162 tmp = readl(host_ctl_reg); 163 i--; 164 } while ((i > 0) && (tmp & HOST_RESET)); 165 166 if (i == 0) { 167 printf("controller reset failed (0x%x)\n", tmp); 168 return -1; 169 } 170 171 return 0; 172 } 173 174 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 175 { 176 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 177 # ifdef CONFIG_DM_PCI 178 struct udevice *dev = uc_priv->dev; 179 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 180 # else 181 pci_dev_t pdev = uc_priv->dev; 182 unsigned short vendor; 183 # endif 184 u16 tmp16; 185 #endif 186 void __iomem *mmio = uc_priv->mmio_base; 187 u32 tmp, cap_save, cmd; 188 int i, j, ret; 189 void __iomem *port_mmio; 190 u32 port_map; 191 192 debug("ahci_host_init: start\n"); 193 194 cap_save = readl(mmio + HOST_CAP); 195 cap_save &= ((1 << 28) | (1 << 17)); 196 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ 197 198 ret = ahci_reset(uc_priv->mmio_base); 199 if (ret) 200 return ret; 201 202 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); 203 writel(cap_save, mmio + HOST_CAP); 204 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); 205 206 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 207 # ifdef CONFIG_DM_PCI 208 if (pplat->vendor == PCI_VENDOR_ID_INTEL) { 209 u16 tmp16; 210 211 dm_pci_read_config16(dev, 0x92, &tmp16); 212 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); 213 } 214 # else 215 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 216 217 if (vendor == PCI_VENDOR_ID_INTEL) { 218 u16 tmp16; 219 pci_read_config_word(pdev, 0x92, &tmp16); 220 tmp16 |= 0xf; 221 pci_write_config_word(pdev, 0x92, tmp16); 222 } 223 # endif 224 #endif 225 uc_priv->cap = readl(mmio + HOST_CAP); 226 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL); 227 port_map = uc_priv->port_map; 228 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1; 229 230 debug("cap 0x%x port_map 0x%x n_ports %d\n", 231 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 232 233 #if !defined(CONFIG_DM_SCSI) 234 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) 235 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; 236 #endif 237 238 for (i = 0; i < uc_priv->n_ports; i++) { 239 if (!(port_map & (1 << i))) 240 continue; 241 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i); 242 port_mmio = (u8 *)uc_priv->port[i].port_mmio; 243 ahci_setup_port(&uc_priv->port[i], mmio, i); 244 245 /* make sure port is not active */ 246 tmp = readl(port_mmio + PORT_CMD); 247 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 248 PORT_CMD_FIS_RX | PORT_CMD_START)) { 249 debug("Port %d is active. Deactivating.\n", i); 250 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 251 PORT_CMD_FIS_RX | PORT_CMD_START); 252 writel_with_flush(tmp, port_mmio + PORT_CMD); 253 254 /* spec says 500 msecs for each bit, so 255 * this is slightly incorrect. 256 */ 257 msleep(500); 258 } 259 260 #ifdef CONFIG_SUNXI_AHCI 261 sunxi_dma_init(port_mmio); 262 #endif 263 264 /* Add the spinup command to whatever mode bits may 265 * already be on in the command register. 266 */ 267 cmd = readl(port_mmio + PORT_CMD); 268 cmd |= PORT_CMD_SPIN_UP; 269 writel_with_flush(cmd, port_mmio + PORT_CMD); 270 271 /* Bring up SATA link. */ 272 ret = ahci_link_up(uc_priv, i); 273 if (ret) { 274 printf("SATA link %d timeout.\n", i); 275 continue; 276 } else { 277 debug("SATA link ok.\n"); 278 } 279 280 /* Clear error status */ 281 tmp = readl(port_mmio + PORT_SCR_ERR); 282 if (tmp) 283 writel(tmp, port_mmio + PORT_SCR_ERR); 284 285 debug("Spinning up device on SATA port %d... ", i); 286 287 j = 0; 288 while (j < WAIT_MS_SPINUP) { 289 tmp = readl(port_mmio + PORT_TFDATA); 290 if (!(tmp & (ATA_BUSY | ATA_DRQ))) 291 break; 292 udelay(1000); 293 tmp = readl(port_mmio + PORT_SCR_STAT); 294 tmp &= PORT_SCR_STAT_DET_MASK; 295 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 296 break; 297 j++; 298 } 299 300 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; 301 if (tmp == PORT_SCR_STAT_DET_COMINIT) { 302 debug("SATA link %d down (COMINIT received), retrying...\n", i); 303 i--; 304 continue; 305 } 306 307 printf("Target spinup took %d ms.\n", j); 308 if (j == WAIT_MS_SPINUP) 309 debug("timeout.\n"); 310 else 311 debug("ok.\n"); 312 313 tmp = readl(port_mmio + PORT_SCR_ERR); 314 debug("PORT_SCR_ERR 0x%x\n", tmp); 315 writel(tmp, port_mmio + PORT_SCR_ERR); 316 317 /* ack any pending irq events for this port */ 318 tmp = readl(port_mmio + PORT_IRQ_STAT); 319 debug("PORT_IRQ_STAT 0x%x\n", tmp); 320 if (tmp) 321 writel(tmp, port_mmio + PORT_IRQ_STAT); 322 323 writel(1 << i, mmio + HOST_IRQ_STAT); 324 325 /* register linkup ports */ 326 tmp = readl(port_mmio + PORT_SCR_STAT); 327 debug("SATA port %d status: 0x%x\n", i, tmp); 328 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) 329 uc_priv->link_port_map |= (0x01 << i); 330 } 331 332 tmp = readl(mmio + HOST_CTL); 333 debug("HOST_CTL 0x%x\n", tmp); 334 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 335 tmp = readl(mmio + HOST_CTL); 336 debug("HOST_CTL 0x%x\n", tmp); 337 #if !defined(CONFIG_DM_SCSI) 338 #ifndef CONFIG_SCSI_AHCI_PLAT 339 # ifdef CONFIG_DM_PCI 340 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); 341 tmp |= PCI_COMMAND_MASTER; 342 dm_pci_write_config16(dev, PCI_COMMAND, tmp16); 343 # else 344 pci_read_config_word(pdev, PCI_COMMAND, &tmp16); 345 tmp |= PCI_COMMAND_MASTER; 346 pci_write_config_word(pdev, PCI_COMMAND, tmp16); 347 # endif 348 #endif 349 #endif 350 return 0; 351 } 352 353 354 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 355 { 356 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 357 # if defined(CONFIG_DM_PCI) 358 struct udevice *dev = uc_priv->dev; 359 # else 360 pci_dev_t pdev = uc_priv->dev; 361 # endif 362 u16 cc; 363 #endif 364 void __iomem *mmio = uc_priv->mmio_base; 365 u32 vers, cap, cap2, impl, speed; 366 const char *speed_s; 367 const char *scc_s; 368 369 vers = readl(mmio + HOST_VERSION); 370 cap = uc_priv->cap; 371 cap2 = readl(mmio + HOST_CAP2); 372 impl = uc_priv->port_map; 373 374 speed = (cap >> 20) & 0xf; 375 if (speed == 1) 376 speed_s = "1.5"; 377 else if (speed == 2) 378 speed_s = "3"; 379 else if (speed == 3) 380 speed_s = "6"; 381 else 382 speed_s = "?"; 383 384 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) 385 scc_s = "SATA"; 386 #else 387 # ifdef CONFIG_DM_PCI 388 dm_pci_read_config16(dev, 0x0a, &cc); 389 # else 390 pci_read_config_word(pdev, 0x0a, &cc); 391 # endif 392 if (cc == 0x0101) 393 scc_s = "IDE"; 394 else if (cc == 0x0106) 395 scc_s = "SATA"; 396 else if (cc == 0x0104) 397 scc_s = "RAID"; 398 else 399 scc_s = "unknown"; 400 #endif 401 printf("AHCI %02x%02x.%02x%02x " 402 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 403 (vers >> 24) & 0xff, 404 (vers >> 16) & 0xff, 405 (vers >> 8) & 0xff, 406 vers & 0xff, 407 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); 408 409 printf("flags: " 410 "%s%s%s%s%s%s%s" 411 "%s%s%s%s%s%s%s" 412 "%s%s%s%s%s%s\n", 413 cap & (1 << 31) ? "64bit " : "", 414 cap & (1 << 30) ? "ncq " : "", 415 cap & (1 << 28) ? "ilck " : "", 416 cap & (1 << 27) ? "stag " : "", 417 cap & (1 << 26) ? "pm " : "", 418 cap & (1 << 25) ? "led " : "", 419 cap & (1 << 24) ? "clo " : "", 420 cap & (1 << 19) ? "nz " : "", 421 cap & (1 << 18) ? "only " : "", 422 cap & (1 << 17) ? "pmp " : "", 423 cap & (1 << 16) ? "fbss " : "", 424 cap & (1 << 15) ? "pio " : "", 425 cap & (1 << 14) ? "slum " : "", 426 cap & (1 << 13) ? "part " : "", 427 cap & (1 << 7) ? "ccc " : "", 428 cap & (1 << 6) ? "ems " : "", 429 cap & (1 << 5) ? "sxs " : "", 430 cap2 & (1 << 2) ? "apst " : "", 431 cap2 & (1 << 1) ? "nvmp " : "", 432 cap2 & (1 << 0) ? "boh " : ""); 433 } 434 435 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT) 436 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 437 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) 438 # else 439 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev) 440 # endif 441 { 442 #if !defined(CONFIG_DM_SCSI) 443 u16 vendor; 444 #endif 445 int rc; 446 447 uc_priv->dev = dev; 448 449 uc_priv->host_flags = ATA_FLAG_SATA 450 | ATA_FLAG_NO_LEGACY 451 | ATA_FLAG_MMIO 452 | ATA_FLAG_PIO_DMA 453 | ATA_FLAG_NO_ATAPI; 454 uc_priv->pio_mask = 0x1f; 455 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 456 457 #if !defined(CONFIG_DM_SCSI) 458 #ifdef CONFIG_DM_PCI 459 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 460 PCI_REGION_MEM); 461 462 /* Take from kernel: 463 * JMicron-specific fixup: 464 * make sure we're in AHCI mode 465 */ 466 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); 467 if (vendor == 0x197b) 468 dm_pci_write_config8(dev, 0x41, 0xa1); 469 #else 470 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, 471 PCI_REGION_MEM); 472 473 /* Take from kernel: 474 * JMicron-specific fixup: 475 * make sure we're in AHCI mode 476 */ 477 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); 478 if (vendor == 0x197b) 479 pci_write_config_byte(dev, 0x41, 0xa1); 480 #endif 481 #else 482 struct scsi_platdata *plat = dev_get_uclass_platdata(dev); 483 uc_priv->mmio_base = (void *)plat->base; 484 #endif 485 486 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base); 487 /* initialize adapter */ 488 rc = ahci_host_init(uc_priv); 489 if (rc) 490 goto err_out; 491 492 ahci_print_info(uc_priv); 493 494 return 0; 495 496 err_out: 497 return rc; 498 } 499 #endif 500 501 #define MAX_DATA_BYTE_COUNT (4*1024*1024) 502 503 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 504 unsigned char *buf, int buf_len) 505 { 506 struct ahci_ioports *pp = &(uc_priv->port[port]); 507 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 508 u32 sg_count; 509 int i; 510 511 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; 512 if (sg_count > AHCI_MAX_SG) { 513 printf("Error:Too much sg!\n"); 514 return -1; 515 } 516 517 for (i = 0; i < sg_count; i++) { 518 ahci_sg->addr = 519 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); 520 ahci_sg->addr_hi = 0; 521 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 522 (buf_len < MAX_DATA_BYTE_COUNT 523 ? (buf_len - 1) 524 : (MAX_DATA_BYTE_COUNT - 1))); 525 ahci_sg++; 526 buf_len -= MAX_DATA_BYTE_COUNT; 527 } 528 529 return sg_count; 530 } 531 532 533 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) 534 { 535 pp->cmd_slot->opts = cpu_to_le32(opts); 536 pp->cmd_slot->status = 0; 537 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 538 #ifdef CONFIG_PHYS_64BIT 539 pp->cmd_slot->tbl_addr_hi = 540 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 541 #endif 542 } 543 544 static int wait_spinup(void __iomem *port_mmio) 545 { 546 ulong start; 547 u32 tf_data; 548 549 start = get_timer(0); 550 do { 551 tf_data = readl(port_mmio + PORT_TFDATA); 552 if (!(tf_data & ATA_BUSY)) 553 return 0; 554 } while (get_timer(start) < WAIT_MS_SPINUP); 555 556 return -ETIMEDOUT; 557 } 558 559 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 560 { 561 struct ahci_ioports *pp = &(uc_priv->port[port]); 562 void __iomem *port_mmio = pp->port_mmio; 563 u32 port_status; 564 void __iomem *mem; 565 566 debug("Enter start port: %d\n", port); 567 port_status = readl(port_mmio + PORT_SCR_STAT); 568 debug("Port %d status: %x\n", port, port_status); 569 if ((port_status & 0xf) != 0x03) { 570 printf("No Link on this port!\n"); 571 return -1; 572 } 573 574 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); 575 if (!mem) { 576 free(pp); 577 printf("%s: No mem for table!\n", __func__); 578 return -ENOMEM; 579 } 580 581 /* Aligned to 2048-bytes */ 582 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); 583 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 584 585 /* 586 * First item in chunk of DMA memory: 32-slot command table, 587 * 32 bytes each in size 588 */ 589 pp->cmd_slot = 590 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); 591 debug("cmd_slot = %p\n", pp->cmd_slot); 592 mem += (AHCI_CMD_SLOT_SZ + 224); 593 594 /* 595 * Second item: Received-FIS area 596 */ 597 pp->rx_fis = virt_to_phys((void *)mem); 598 mem += AHCI_RX_FIS_SZ; 599 600 /* 601 * Third item: data area for storing a single command 602 * and its scatter-gather table 603 */ 604 pp->cmd_tbl = virt_to_phys((void *)mem); 605 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); 606 607 mem += AHCI_CMD_TBL_HDR; 608 pp->cmd_tbl_sg = 609 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); 610 611 writel_with_flush((unsigned long)pp->cmd_slot, 612 port_mmio + PORT_LST_ADDR); 613 614 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); 615 616 #ifdef CONFIG_SUNXI_AHCI 617 sunxi_dma_init(port_mmio); 618 #endif 619 620 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 621 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 622 PORT_CMD_START, port_mmio + PORT_CMD); 623 624 debug("Exit start port %d\n", port); 625 626 /* 627 * Make sure interface is not busy based on error and status 628 * information from task file data register before proceeding 629 */ 630 return wait_spinup(port_mmio); 631 } 632 633 634 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis, 635 int fis_len, u8 *buf, int buf_len, u8 is_write) 636 { 637 638 struct ahci_ioports *pp = &(uc_priv->port[port]); 639 void __iomem *port_mmio = pp->port_mmio; 640 u32 opts; 641 u32 port_status; 642 int sg_count; 643 644 debug("Enter %s: for port %d\n", __func__, port); 645 646 if (port > uc_priv->n_ports) { 647 printf("Invalid port number %d\n", port); 648 return -1; 649 } 650 651 port_status = readl(port_mmio + PORT_SCR_STAT); 652 if ((port_status & 0xf) != 0x03) { 653 debug("No Link on port %d!\n", port); 654 return -1; 655 } 656 657 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); 658 659 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 660 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); 661 ahci_fill_cmd_slot(pp, opts); 662 663 ahci_dcache_flush_sata_cmd(pp); 664 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); 665 666 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 667 668 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 669 WAIT_MS_DATAIO, 0x1)) { 670 printf("timeout exit!\n"); 671 return -1; 672 } 673 674 ahci_dcache_invalidate_range((unsigned long)buf, 675 (unsigned long)buf_len); 676 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); 677 678 return 0; 679 } 680 681 682 static char *ata_id_strcpy(u16 *target, u16 *src, int len) 683 { 684 int i; 685 for (i = 0; i < len / 2; i++) 686 target[i] = swab16(src[i]); 687 return (char *)target; 688 } 689 690 /* 691 * SCSI INQUIRY command operation. 692 */ 693 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv, 694 struct scsi_cmd *pccb) 695 { 696 static const u8 hdr[] = { 697 0, 698 0, 699 0x5, /* claim SPC-3 version compatibility */ 700 2, 701 95 - 4, 702 }; 703 u8 fis[20]; 704 u16 *idbuf; 705 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); 706 u8 port; 707 708 /* Clean ccb data buffer */ 709 memset(pccb->pdata, 0, pccb->datalen); 710 711 memcpy(pccb->pdata, hdr, sizeof(hdr)); 712 713 if (pccb->datalen <= 35) 714 return 0; 715 716 memset(fis, 0, sizeof(fis)); 717 /* Construct the FIS */ 718 fis[0] = 0x27; /* Host to device FIS. */ 719 fis[1] = 1 << 7; /* Command FIS. */ 720 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ 721 722 /* Read id from sata */ 723 port = pccb->target; 724 725 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis), 726 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) { 727 debug("scsi_ahci: SCSI inquiry command failure.\n"); 728 return -EIO; 729 } 730 731 if (!uc_priv->ataid[port]) { 732 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2); 733 if (!uc_priv->ataid[port]) { 734 printf("%s: No memory for ataid[port]\n", __func__); 735 return -ENOMEM; 736 } 737 } 738 739 idbuf = uc_priv->ataid[port]; 740 741 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); 742 ata_swap_buf_le16(idbuf, ATA_ID_WORDS); 743 744 memcpy(&pccb->pdata[8], "ATA ", 8); 745 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); 746 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); 747 748 #ifdef DEBUG 749 ata_dump_id(idbuf); 750 #endif 751 return 0; 752 } 753 754 755 /* 756 * SCSI READ10/WRITE10 command operation. 757 */ 758 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv, 759 struct scsi_cmd *pccb, u8 is_write) 760 { 761 lbaint_t lba = 0; 762 u16 blocks = 0; 763 u8 fis[20]; 764 u8 *user_buffer = pccb->pdata; 765 u32 user_buffer_size = pccb->datalen; 766 767 /* Retrieve the base LBA number from the ccb structure. */ 768 if (pccb->cmd[0] == SCSI_READ16) { 769 memcpy(&lba, pccb->cmd + 2, 8); 770 lba = be64_to_cpu(lba); 771 } else { 772 u32 temp; 773 memcpy(&temp, pccb->cmd + 2, 4); 774 lba = be32_to_cpu(temp); 775 } 776 777 /* 778 * Retrieve the base LBA number and the block count from 779 * the ccb structure. 780 * 781 * For 10-byte and 16-byte SCSI R/W commands, transfer 782 * length 0 means transfer 0 block of data. 783 * However, for ATA R/W commands, sector count 0 means 784 * 256 or 65536 sectors, not 0 sectors as in SCSI. 785 * 786 * WARNING: one or two older ATA drives treat 0 as 0... 787 */ 788 if (pccb->cmd[0] == SCSI_READ16) 789 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]); 790 else 791 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); 792 793 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n", 794 is_write ? "write" : "read", blocks, lba); 795 796 /* Preset the FIS */ 797 memset(fis, 0, sizeof(fis)); 798 fis[0] = 0x27; /* Host to device FIS. */ 799 fis[1] = 1 << 7; /* Command FIS. */ 800 /* Command byte (read/write). */ 801 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 802 803 while (blocks) { 804 u16 now_blocks; /* number of blocks per iteration */ 805 u32 transfer_size; /* number of bytes per iteration */ 806 807 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); 808 809 transfer_size = ATA_SECT_SIZE * now_blocks; 810 if (transfer_size > user_buffer_size) { 811 printf("scsi_ahci: Error: buffer too small.\n"); 812 return -EIO; 813 } 814 815 /* 816 * LBA48 SATA command but only use 32bit address range within 817 * that (unless we've enabled 64bit LBA support). The next 818 * smaller command range (28bit) is too small. 819 */ 820 fis[4] = (lba >> 0) & 0xff; 821 fis[5] = (lba >> 8) & 0xff; 822 fis[6] = (lba >> 16) & 0xff; 823 fis[7] = 1 << 6; /* device reg: set LBA mode */ 824 fis[8] = ((lba >> 24) & 0xff); 825 #ifdef CONFIG_SYS_64BIT_LBA 826 if (pccb->cmd[0] == SCSI_READ16) { 827 fis[9] = ((lba >> 32) & 0xff); 828 fis[10] = ((lba >> 40) & 0xff); 829 } 830 #endif 831 832 fis[3] = 0xe0; /* features */ 833 834 /* Block (sector) count */ 835 fis[12] = (now_blocks >> 0) & 0xff; 836 fis[13] = (now_blocks >> 8) & 0xff; 837 838 /* Read/Write from ahci */ 839 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis, 840 sizeof(fis), user_buffer, transfer_size, 841 is_write)) { 842 debug("scsi_ahci: SCSI %s10 command failure.\n", 843 is_write ? "WRITE" : "READ"); 844 return -EIO; 845 } 846 847 /* If this transaction is a write, do a following flush. 848 * Writes in u-boot are so rare, and the logic to know when is 849 * the last write and do a flush only there is sufficiently 850 * difficult. Just do a flush after every write. This incurs, 851 * usually, one extra flush when the rare writes do happen. 852 */ 853 if (is_write) { 854 if (-EIO == ata_io_flush(uc_priv, pccb->target)) 855 return -EIO; 856 } 857 user_buffer += transfer_size; 858 user_buffer_size -= transfer_size; 859 blocks -= now_blocks; 860 lba += now_blocks; 861 } 862 863 return 0; 864 } 865 866 867 /* 868 * SCSI READ CAPACITY10 command operation. 869 */ 870 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv, 871 struct scsi_cmd *pccb) 872 { 873 u32 cap; 874 u64 cap64; 875 u32 block_size; 876 877 if (!uc_priv->ataid[pccb->target]) { 878 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " 879 "\tNo ATA info!\n" 880 "\tPlease run SCSI command INQUIRY first!\n"); 881 return -EPERM; 882 } 883 884 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]); 885 if (cap64 > 0x100000000ULL) 886 cap64 = 0xffffffff; 887 888 cap = cpu_to_be32(cap64); 889 memcpy(pccb->pdata, &cap, sizeof(cap)); 890 891 block_size = cpu_to_be32((u32)512); 892 memcpy(&pccb->pdata[4], &block_size, 4); 893 894 return 0; 895 } 896 897 898 /* 899 * SCSI READ CAPACITY16 command operation. 900 */ 901 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv, 902 struct scsi_cmd *pccb) 903 { 904 u64 cap; 905 u64 block_size; 906 907 if (!uc_priv->ataid[pccb->target]) { 908 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " 909 "\tNo ATA info!\n" 910 "\tPlease run SCSI command INQUIRY first!\n"); 911 return -EPERM; 912 } 913 914 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]); 915 cap = cpu_to_be64(cap); 916 memcpy(pccb->pdata, &cap, sizeof(cap)); 917 918 block_size = cpu_to_be64((u64)512); 919 memcpy(&pccb->pdata[8], &block_size, 8); 920 921 return 0; 922 } 923 924 925 /* 926 * SCSI TEST UNIT READY command operation. 927 */ 928 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv, 929 struct scsi_cmd *pccb) 930 { 931 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM; 932 } 933 934 935 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) 936 { 937 struct ahci_uc_priv *uc_priv; 938 #ifdef CONFIG_DM_SCSI 939 uc_priv = dev_get_uclass_priv(dev->parent); 940 #else 941 uc_priv = probe_ent; 942 #endif 943 int ret; 944 945 switch (pccb->cmd[0]) { 946 case SCSI_READ16: 947 case SCSI_READ10: 948 ret = ata_scsiop_read_write(uc_priv, pccb, 0); 949 break; 950 case SCSI_WRITE10: 951 ret = ata_scsiop_read_write(uc_priv, pccb, 1); 952 break; 953 case SCSI_RD_CAPAC10: 954 ret = ata_scsiop_read_capacity10(uc_priv, pccb); 955 break; 956 case SCSI_RD_CAPAC16: 957 ret = ata_scsiop_read_capacity16(uc_priv, pccb); 958 break; 959 case SCSI_TST_U_RDY: 960 ret = ata_scsiop_test_unit_ready(uc_priv, pccb); 961 break; 962 case SCSI_INQUIRY: 963 ret = ata_scsiop_inquiry(uc_priv, pccb); 964 break; 965 default: 966 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); 967 return -ENOTSUPP; 968 } 969 970 if (ret) { 971 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); 972 return ret; 973 } 974 return 0; 975 976 } 977 978 static int ahci_start_ports(struct ahci_uc_priv *uc_priv) 979 { 980 u32 linkmap; 981 int i; 982 983 linkmap = uc_priv->link_port_map; 984 985 for (i = 0; i < uc_priv->n_ports; i++) { 986 if (((linkmap >> i) & 0x01)) { 987 if (ahci_port_start(uc_priv, (u8) i)) { 988 printf("Can not start port %d\n", i); 989 continue; 990 } 991 } 992 } 993 994 return 0; 995 } 996 997 #ifndef CONFIG_DM_SCSI 998 void scsi_low_level_init(int busdevfunc) 999 { 1000 struct ahci_uc_priv *uc_priv; 1001 1002 #ifndef CONFIG_SCSI_AHCI_PLAT 1003 probe_ent = calloc(1, sizeof(struct ahci_uc_priv)); 1004 if (!probe_ent) { 1005 printf("%s: No memory for uc_priv\n", __func__); 1006 return; 1007 } 1008 uc_priv = probe_ent; 1009 # if defined(CONFIG_DM_PCI) 1010 struct udevice *dev; 1011 int ret; 1012 1013 ret = dm_pci_bus_find_bdf(busdevfunc, &dev); 1014 if (ret) 1015 return; 1016 ahci_init_one(uc_priv, dev); 1017 # else 1018 ahci_init_one(uc_priv, busdevfunc); 1019 # endif 1020 #else 1021 uc_priv = probe_ent; 1022 #endif 1023 1024 ahci_start_ports(uc_priv); 1025 } 1026 #endif 1027 1028 #ifndef CONFIG_SCSI_AHCI_PLAT 1029 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 1030 int ahci_init_one_dm(struct udevice *dev) 1031 { 1032 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1033 1034 return ahci_init_one(uc_priv, dev); 1035 } 1036 #endif 1037 #endif 1038 1039 int ahci_start_ports_dm(struct udevice *dev) 1040 { 1041 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1042 1043 return ahci_start_ports(uc_priv); 1044 } 1045 1046 #ifdef CONFIG_SCSI_AHCI_PLAT 1047 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base) 1048 { 1049 int rc; 1050 1051 uc_priv->host_flags = ATA_FLAG_SATA 1052 | ATA_FLAG_NO_LEGACY 1053 | ATA_FLAG_MMIO 1054 | ATA_FLAG_PIO_DMA 1055 | ATA_FLAG_NO_ATAPI; 1056 uc_priv->pio_mask = 0x1f; 1057 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 1058 1059 uc_priv->mmio_base = base; 1060 1061 /* initialize adapter */ 1062 rc = ahci_host_init(uc_priv); 1063 if (rc) 1064 goto err_out; 1065 1066 ahci_print_info(uc_priv); 1067 1068 rc = ahci_start_ports(uc_priv); 1069 1070 err_out: 1071 return rc; 1072 } 1073 1074 #ifndef CONFIG_DM_SCSI 1075 int ahci_init(void __iomem *base) 1076 { 1077 struct ahci_uc_priv *uc_priv; 1078 1079 probe_ent = malloc(sizeof(struct ahci_uc_priv)); 1080 if (!probe_ent) { 1081 printf("%s: No memory for uc_priv\n", __func__); 1082 return -ENOMEM; 1083 } 1084 1085 uc_priv = probe_ent; 1086 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 1087 1088 return ahci_init_common(uc_priv, base); 1089 } 1090 #endif 1091 1092 int ahci_init_dm(struct udevice *dev, void __iomem *base) 1093 { 1094 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1095 1096 return ahci_init_common(uc_priv, base); 1097 } 1098 1099 void __weak scsi_init(void) 1100 { 1101 } 1102 1103 #endif /* CONFIG_SCSI_AHCI_PLAT */ 1104 1105 /* 1106 * In the general case of generic rotating media it makes sense to have a 1107 * flush capability. It probably even makes sense in the case of SSDs because 1108 * one cannot always know for sure what kind of internal cache/flush mechanism 1109 * is embodied therein. At first it was planned to invoke this after the last 1110 * write to disk and before rebooting. In practice, knowing, a priori, which 1111 * is the last write is difficult. Because writing to the disk in u-boot is 1112 * very rare, this flush command will be invoked after every block write. 1113 */ 1114 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port) 1115 { 1116 u8 fis[20]; 1117 struct ahci_ioports *pp = &(uc_priv->port[port]); 1118 void __iomem *port_mmio = pp->port_mmio; 1119 u32 cmd_fis_len = 5; /* five dwords */ 1120 1121 /* Preset the FIS */ 1122 memset(fis, 0, 20); 1123 fis[0] = 0x27; /* Host to device FIS. */ 1124 fis[1] = 1 << 7; /* Command FIS. */ 1125 fis[2] = ATA_CMD_FLUSH_EXT; 1126 1127 memcpy((unsigned char *)pp->cmd_tbl, fis, 20); 1128 ahci_fill_cmd_slot(pp, cmd_fis_len); 1129 ahci_dcache_flush_sata_cmd(pp); 1130 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 1131 1132 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 1133 WAIT_MS_FLUSH, 0x1)) { 1134 debug("scsi_ahci: flush command timeout on port %d.\n", port); 1135 return -EIO; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int ahci_scsi_bus_reset(struct udevice *dev) 1142 { 1143 /* Not implemented */ 1144 1145 return 0; 1146 } 1147 1148 #ifdef CONFIG_DM_SCSI 1149 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp) 1150 { 1151 struct udevice *dev; 1152 int ret; 1153 1154 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev); 1155 if (ret) 1156 return ret; 1157 *devp = dev; 1158 1159 return 0; 1160 } 1161 1162 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base) 1163 { 1164 struct ahci_uc_priv *uc_priv; 1165 struct scsi_platdata *uc_plat; 1166 struct udevice *dev; 1167 int ret; 1168 1169 device_find_first_child(ahci_dev, &dev); 1170 if (!dev) 1171 return -ENODEV; 1172 uc_plat = dev_get_uclass_platdata(dev); 1173 uc_plat->base = base; 1174 uc_plat->max_lun = 1; 1175 uc_plat->max_id = 2; 1176 1177 uc_priv = dev_get_uclass_priv(ahci_dev); 1178 ret = ahci_init_one(uc_priv, dev); 1179 if (ret) 1180 return ret; 1181 ret = ahci_start_ports(uc_priv); 1182 if (ret) 1183 return ret; 1184 1185 return 0; 1186 } 1187 1188 #ifdef CONFIG_DM_PCI 1189 int ahci_probe_scsi_pci(struct udevice *ahci_dev) 1190 { 1191 ulong base; 1192 1193 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 1194 PCI_REGION_MEM); 1195 1196 return ahci_probe_scsi(ahci_dev, base); 1197 } 1198 #endif 1199 1200 struct scsi_ops scsi_ops = { 1201 .exec = ahci_scsi_exec, 1202 .bus_reset = ahci_scsi_bus_reset, 1203 }; 1204 1205 U_BOOT_DRIVER(ahci_scsi) = { 1206 .name = "ahci_scsi", 1207 .id = UCLASS_SCSI, 1208 .ops = &scsi_ops, 1209 }; 1210 #else 1211 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) 1212 { 1213 return ahci_scsi_exec(dev, pccb); 1214 } 1215 1216 __weak int scsi_bus_reset(struct udevice *dev) 1217 { 1218 return ahci_scsi_bus_reset(dev); 1219 1220 return 0; 1221 } 1222 #endif 1223