1Cadence QSPI controller device tree bindings
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3
4Required properties:
5- compatible		: should be "cadence,qspi".
6- reg			: 1.Physical base address and size of SPI registers map.
7			  2. Physical base address & size of NOR Flash.
8- clocks		: Clock phandles (see clock bindings for details).
9- cdns,fifo-depth	: Size of the data FIFO in words.
10- cdns,fifo-width	: Bus width of the data FIFO in bytes.
11- cdns,trigger-address	: 32-bit indirect AHB trigger address.
12- cdns,is-decoded-cs	: Flag to indicate whether decoder is used or not.
13- status		: enable in requried dts.
14
15connected flash properties
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17
18- spi-max-frequency	: Max supported spi frequency.
19- page-size		: Flash page size.
20- block-size		: Flash memory block size.
21- cdns,tshsl-ns		: Added delay in master reference clocks (ref_clk) for
22			  the length that the master mode chip select outputs
23			  are de-asserted between transactions.
24- cdns,tsd2d-ns		: Delay in master reference clocks (ref_clk) between one
25			  chip select being de-activated and the activation of
26			  another.
27- cdns,tchsh-ns		: Delay in master reference clocks between last bit of
28			  current transaction and de-asserting the device chip
29			  select (n_ss_out).
30- cdns,tslch-ns		: Delay in master reference clocks between setting
31			  n_ss_out low and first bit transfer
32