1Soft SPI
2
3The soft SPI bus implementation allows the use of GPIO pins to simulate a
4SPI bus. No SPI host is required for this to work. The down-side is that the
5performance will typically be much lower than a real SPI bus.
6
7The soft SPI node requires the following properties:
8
9Mandatory properties:
10compatible: "spi-gpio"
11cs-gpios: GPIOs to use for SPI chip select (output)
12gpio-sck: GPIO to use for SPI clock (output)
13And at least one of:
14gpio-mosi: GPIO to use for SPI MOSI line (output)
15gpio-miso: GPIO to use for SPI MISO line (input)
16
17Optional propertie:
18spi-delay-us: Number of microseconds of delay between each CS transition
19
20The GPIOs should be specified as required by the GPIO controller referenced.
21The first cell holds the phandle of the controller and the second cell
22typically holds the GPIO number.
23
24
25Example:
26
27	soft-spi {
28		compatible = "spi-gpio";
29		cs-gpios = <&gpio 235 0>;	/* Y43 */
30		gpio-sck = <&gpio 225 0>;	/* Y31 */
31		gpio-mosi = <&gpio 227 0>;	/* Y33 */
32		gpio-miso = <&gpio 224 0>;	/* Y30 */
33		spi-delay-us = <1>;
34		#address-cells = <1>;
35		#size-cells = <0>;
36		cs@0 {
37		};
38	};
39